Thierry Reding [Fri, 30 Jun 2023 13:07:48 +0000 (15:07 +0200)]
clk: tegra: Avoid calling an uninitialized function
Commit 493ffb046cf5 ("clk: tegra: super: Switch to determine_rate")
replaced clk_super_round_rate() by clk_super_determine_rate(), but
didn't update one callsite that was explicitly calling the old
tegra_clk_super_ops.round_rate() function, which was now NULL. This
resulted in a crash on Tegra30 systems during early boot.
Switch this callsite over to the clk_super_determine_rate() equivalent
to avoid the crash.
Stephen Boyd [Mon, 26 Jun 2023 23:36:14 +0000 (16:36 -0700)]
Merge branches 'clk-qcom' and 'clk-microchip' into clk-next
* clk-qcom: (63 commits)
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
clk: qcom: gpucc-sm6375: Enable runtime pm
dt-bindings: clock: sm6375-gpucc: Add VDD_GX
clk: qcom: gcc-sm6115: Add missing PLL config properties
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-ipq6018: remove duplicate initializers
clk: qcom: gcc-ipq9574: Enable crypto clocks
dt-bindings: clock: Add crypto clock and reset definitions
clk: qcom: Add lpass audio clock controller driver for SC8280XP
clk: qcom: Add lpass clock controller driver for SC8280XP
dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226
clk: qcom: gpucc-sm8550: Add support for graphics clock controller
clk: qcom: Add support for SM8450 GPUCC
clk: qcom: gcc-sm8450: Enable hw_clk_ctrl
clk: qcom: rcg2: Make hw_clk_ctrl toggleable
dt-bindings: clock: qcom: Add SM8550 graphics clock controller
...
* clk-microchip:
clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
clk: at91: sama7g5: switch to parent_hw and parent_data
clk: at91: sckc: switch to parent_data/parent_hw
clk: at91: clk-sam9x60-pll: add support for parent_hw
clk: at91: clk-utmi: add support for parent_hw
clk: at91: clk-system: add support for parent_hw
clk: at91: clk-programmable: add support for parent_hw
clk: at91: clk-peripheral: add support for parent_hw
clk: at91: clk-master: add support for parent_hw
clk: at91: clk-generated: add support for parent_hw
clk: at91: clk-main: add support for parent_data/parent_hw
Stephen Boyd [Mon, 26 Jun 2023 23:29:58 +0000 (16:29 -0700)]
Merge tag 'clk-microchip-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Claudiu Beznea:
It contains support for parent_data, parent_hw in AT91 clock drivers
used by SAMA7G5 SoC (e.g. main, master, generic, peripheral, programmable,
system, utmi, slow clocks) and also the update of SAMA7G5 to use
this new support.
* tag 'clk-microchip-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
clk: at91: sama7g5: switch to parent_hw and parent_data
clk: at91: sckc: switch to parent_data/parent_hw
clk: at91: clk-sam9x60-pll: add support for parent_hw
clk: at91: clk-utmi: add support for parent_hw
clk: at91: clk-system: add support for parent_hw
clk: at91: clk-programmable: add support for parent_hw
clk: at91: clk-peripheral: add support for parent_hw
clk: at91: clk-master: add support for parent_hw
clk: at91: clk-generated: add support for parent_hw
clk: at91: clk-main: add support for parent_data/parent_hw
Stephen Boyd [Mon, 26 Jun 2023 21:56:06 +0000 (14:56 -0700)]
Merge tag 'qcom-clk-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
This introduces Global Clock Controller for SDX75, LPASS clock
controllers for SC8280XP, video clock controller for SM8350, SM8450 and
SM8550, GPU clock controller for SM8450 and SM8550, RPMH clock support
for SDX75 and IPQ9574 support in APSS IPQ PLL driver.
Support for branch2 clocks with inverted off-bit is introduced and a
couple of fixes to Alpha PLLs handling of TEST_CTL updates.
The handling of active-only clocks in SMD RPM is improved, to ensure
votes are appropriately placed.
SC7180 camera GDSCs are made children of the titan_top GDSC.
A couple of fixes to the display clocks on QCM2290 and shared RCGs in
GCC are marked as such.
SDCC clocks for IPQ6018 and IPQ5332 are corrected to use floor ops, and
network-related resets on IPQ6018 are updated to cover all bits of each
reset.
Crypto clocks are added to IPQ9574 global clock controller, together
with a few cleanups.
Runtime PM is enabeld for SC8280XP GCC and GPUCC, and SM6375 GPUCC.
A few fixes for MSM8974 multi-media clock controller.
Support for some RCG clocks to be automatically controlled by downstream
branches, and added to SM8450 GCC clocks.
Further Kconfig depdenencies are introduce to avoid building Qualcomm
clock drivers on unrelated architectures.
Lastly, related DeviceTree binding updates are made.
The tail of this is not bisectable, due to the missing DeviceTree
binding include files. Rebase at this point in time is not desirable.
* tag 'qcom-clk-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (63 commits)
clk: qcom: gcc-sc8280xp: Add runtime PM
clk: qcom: gpucc-sc8280xp: Add runtime PM
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
clk: qcom: gpucc-sm6375: Enable runtime pm
dt-bindings: clock: sm6375-gpucc: Add VDD_GX
clk: qcom: gcc-sm6115: Add missing PLL config properties
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-ipq6018: remove duplicate initializers
clk: qcom: gcc-ipq9574: Enable crypto clocks
dt-bindings: clock: Add crypto clock and reset definitions
clk: qcom: Add lpass audio clock controller driver for SC8280XP
clk: qcom: Add lpass clock controller driver for SC8280XP
dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP
dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226
clk: qcom: gpucc-sm8550: Add support for graphics clock controller
clk: qcom: Add support for SM8450 GPUCC
clk: qcom: gcc-sm8450: Enable hw_clk_ctrl
clk: qcom: rcg2: Make hw_clk_ctrl toggleable
dt-bindings: clock: qcom: Add SM8550 graphics clock controller
...
Bjorn Andersson [Mon, 26 Jun 2023 16:26:48 +0000 (09:26 -0700)]
Merge branch '20230608125315.11454-2-srinivas.kandagatla@linaro.org' into clk-for-6.5
Merge the missing SC8280XP LPASS DeviceTree changes, which where brought
in through a topic branch in order to be shared with the DeviceTree
source files, but not merged into the clock tree until now.
Stephen Boyd [Mon, 26 Jun 2023 15:55:22 +0000 (08:55 -0700)]
Merge branches 'clk-imx', 'clk-microchip', 'clk-cleanup', 'clk-bindings', 'clk-ti' and 'clk-kasprintf' into clk-next
- Handle allocation failures from kasprintf() and friends
* clk-imx:
clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()
clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe
clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe
dt-bindings: clock: imx8m: Add missing interrupt property
clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe
clk: imx: composite-8m: Add imx8m_divider_determine_rate
clk: imx: scu: use _safe list iterator to avoid a use after free
clk: imx: drop imx_unregister_clocks
clk: imx6ul: retain early UART clocks during kernel init
clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks
* clk-microchip:
dt-bindings: clocks: at91sam9x5-sckc: convert to yaml
dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml
clk: microchip: Use of_property_read_bool() for boolean properties
clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
* clk-cleanup:
clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro
clk: Fix memory leak in devm_clk_notifier_register()
clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes
clk: mvebu: Use of_get_cpu_hwid() to read CPU ID
MAINTAINERS: Add Marvell mvebu clock drivers
clk: mvebu: Use of_address_to_resource()
clk: tegra: tegra124-emc: Fix potential memory leak
clk: clocking-wizard: Fix Oops in clk_wzrd_register_divider()
clk: bcm: rpi: Fix off by one in raspberrypi_discover_clocks()
clk: sifive: Use devm_platform_ioremap_resource()
* clk-bindings:
dt-bindings: clock: drop unneeded quotes and use absolute /schemas path
dt-bindings: rcc: stm32: Sync with u-boot copy for STM32MP13 SoC
* clk-ti:
clk: keystone: syscon-clk: Add support for audio refclk
dt-bindings: clock: Add binding documentation for TI Audio REFCLK
dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible
clk: keystone: syscon-clk: Allow the clock node to not be of type syscon
* clk-kasprintf:
clk: clocking-wizard: check return value of devm_kasprintf()
clk: ti: clkctrl: check return value of kasprintf()
clk: keystone: sci-clk: check return value of kasprintf()
clk: si5341: free unused memory on probe failure
clk: si5341: check return value of {devm_}kasprintf()
clk: si5341: return error if one synth clock registration fails
clk: cdce925: check return value of kasprintf()
clk: vc5: check memory returned by kasprintf()
Stephen Boyd [Mon, 26 Jun 2023 15:54:19 +0000 (08:54 -0700)]
Merge branches 'clk-platform', 'clk-i2c', 'clk-mediatek', 'clk-i2cid' and 'clk-vc5' into clk-next
- Migrate platform clk drivers to .remove_new()
- Migrate i2c clk drivers to .probe() instead of .probe_new()
- Remove CLK_SET_PARENT from all Mediatek MSDC core clocks
- Add infra_ao reset support for Mediatek MT8188 SoCs
- Align driver_data to i2c_device_id tables in some i2c clk drivers
- Use device_get_match_data() in vc5 clk driver
* clk-platform:
clk: mediatek: Convert all remaining drivers to platform_driver's .remove_new()
clk: mediatek: Make mtk_clk_pdev_remove() return void
clk: mediatek: Make mtk_clk_simple_remove() return void
* clk-i2c:
clk: si521xx: Switch i2c driver back to use .probe()
clk: Switch i2c drivers back to use .probe()
* clk-mediatek:
clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue
clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error
clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks
clk: mediatek: fix of_iomap memory leak
clk: mediatek: reset: add infra_ao reset support for MT8188
dt-bindings: reset: mt8188: add thermal reset control bit
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag
clk: mediatek: Enable all MT8192 clocks by default
* clk-i2cid:
clk: rs9: Fix .driver_data content in i2c_device_id
clk: vc7: Fix .driver_data content in i2c_device_id
clk: vc5: Fix .driver_data content in i2c_device_id
* clk-vc5:
clk: vc7: Use device_get_match_data() instead of of_device_get_match_data()
clk: vc5: Use device_get_match_data() instead of of_device_get_match_data()
Claudiu Beznea [Thu, 15 Jun 2023 09:32:26 +0000 (12:32 +0300)]
clk: at91: sama7g5: switch to parent_hw and parent_data
Switch SAMA7G5 clocks to use parent_hw and parent_data. Having
parent_hw instead of parent names improves to clock registration
speed and re-parenting. Extra time saved on registration is
~250us when running at 800MHz.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:24 +0000 (12:32 +0300)]
clk: at91: clk-sam9x60-pll: add support for parent_hw
Add support for parent_hw in SAM9X60 PLL clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-sam9x60-pll were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:23 +0000 (12:32 +0300)]
clk: at91: clk-utmi: add support for parent_hw
Add support for parent_hw in utmi clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-utmi were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:22 +0000 (12:32 +0300)]
clk: at91: clk-system: add support for parent_hw
Add support for parent_hw in system clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-system were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:21 +0000 (12:32 +0300)]
clk: at91: clk-programmable: add support for parent_hw
Add support for parent_hw in programmable clock driver.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-programmable were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:20 +0000 (12:32 +0300)]
clk: at91: clk-peripheral: add support for parent_hw
Add support for parent_hw in peripheral clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-peripheral were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:19 +0000 (12:32 +0300)]
clk: at91: clk-master: add support for parent_hw
Add support for parent_hw in master clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-master were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:18 +0000 (12:32 +0300)]
clk: at91: clk-generated: add support for parent_hw
Add support for parent_hw in generic clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-generated were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 09:32:17 +0000 (12:32 +0300)]
clk: at91: clk-main: add support for parent_data/parent_hw
Add support for parent_data and parent_hw in main oscillator clock drivers.
With this parent-child relations are described with pointers rather
than strings making registration a bit faster.
All the SoC based drivers that rely on clk-main were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Claudiu Beznea [Thu, 15 Jun 2023 10:19:31 +0000 (13:19 +0300)]
clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro
clk_hw_register_fixed_rate_parent_data() 3rd parameter is parent_data
not parent_hw. Inner function (__clk_hw_register_fixed_rate()) is called
with parent_data parameter as valid. To have this parameter taken into
account update the name of the 3rd parameter of
clk_hw_register_fixed_rate_parent_data() macro to parent_data.
Fei Shao [Mon, 19 Jun 2023 03:22:53 +0000 (11:22 +0800)]
clk: Fix memory leak in devm_clk_notifier_register()
devm_clk_notifier_register() allocates a devres resource for clk
notifier but didn't register that to the device, so the notifier didn't
get unregistered on device detach and the allocated resource was leaked.
Fix the issue by registering the resource through devres_add().
This issue was found with kmemleak on a Chromebook.
Rob Herring [Fri, 9 Jun 2023 18:13:47 +0000 (12:13 -0600)]
clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes
Rework iterating over DT CPU nodes to iterate over possible CPUs
instead. There's no need to walk the DT CPU nodes again. Possible CPUs
is equal to the number of CPUs defined in the DT. Using the "reg" value
for an array index is fragile as it assumes "reg" is 0-N which often is
not the case.
Rob Herring [Fri, 9 Jun 2023 18:13:46 +0000 (12:13 -0600)]
clk: mvebu: Use of_get_cpu_hwid() to read CPU ID
Use of_get_cpu_hwid() rather than the open coded reading of the CPU
nodes "reg" property. The existing code is in fact wrong as the "reg"
address cells size is 2 cells for arm64. The existing code happens to
work because the DTS files are wrong as well.
Dmitry Baryshkov [Sun, 7 May 2023 17:53:35 +0000 (20:53 +0300)]
clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
Using PWRSTS_RET on msm8974's MDSS_GDSC causes display to stop working.
The gdsc doesn't fully come out of retention mode. Change it's pwrsts
flags to PWRSTS_OFF_ON.
Claudiu Beznea [Tue, 30 May 2023 09:39:13 +0000 (12:39 +0300)]
clk: clocking-wizard: check return value of devm_kasprintf()
devm_kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).
Claudiu Beznea [Tue, 30 May 2023 09:39:12 +0000 (12:39 +0300)]
clk: ti: clkctrl: check return value of kasprintf()
kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).
Fixes: 852049594b9a ("clk: ti: clkctrl: convert subclocks to use proper names also") Fixes: 6c3090520554 ("clk: ti: clkctrl: Fix hidden dependency to node name") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-8-claudiu.beznea@microchip.com Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Tue, 30 May 2023 09:39:11 +0000 (12:39 +0300)]
clk: keystone: sci-clk: check return value of kasprintf()
kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).
Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support")
Depends-on: 96488c09b0f4 ("clk: keystone: sci-clk: cut down the clock name length") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-7-claudiu.beznea@microchip.com Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Claudiu Beznea [Tue, 30 May 2023 09:39:09 +0000 (12:39 +0300)]
clk: si5341: check return value of {devm_}kasprintf()
{devm_}kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).
Claudiu Beznea [Tue, 30 May 2023 09:39:08 +0000 (12:39 +0300)]
clk: si5341: return error if one synth clock registration fails
In case devm_clk_hw_register() fails for one of synth clocks the probe
continues. Later on, when registering output clocks which have as parents
all the synth clocks, in case there is registration failure for at least
one synth clock the information passed to clk core for registering output
clock is not right: init.num_parents is fixed but init.parents may contain
an array with less parents.
kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).
Claudiu Beznea [Tue, 30 May 2023 09:39:06 +0000 (12:39 +0300)]
clk: vc5: check memory returned by kasprintf()
kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).
Fixes: f491276a5168 ("clk: vc5: Allow Versaclock driver to support multiple instances") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230530093913.1656095-2-claudiu.beznea@microchip.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 15 Jun 2023 12:20:51 +0000 (14:20 +0200)]
clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue
In case of error after of_ioremap() the resource must be released:
call iounmap() where appropriate to fix that.
Fixes: 41138fbf876c ("clk: mediatek: mt8173: Migrate to platform driver and common probe") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230615122051.546985-4-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 15 Jun 2023 12:20:50 +0000 (14:20 +0200)]
clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error
The of_iomap() function returns NULL in case of error so usage of
PTR_ERR() is wrong!
Change that to return -ENOMEM in case of failure.
Fixes: 41138fbf876c ("clk: mediatek: mt8173: Migrate to platform driver and common probe") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230615122051.546985-3-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Thu, 15 Jun 2023 12:20:49 +0000 (14:20 +0200)]
clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks
In the rare case in which one of the clock drivers has divider clocks
but not composite clocks, mtk_clk_simple_probe() would not io(re)map,
hence passing a NULL pointer to mtk_clk_register_dividers().
To fix this issue, extend the `if` conditional to also check if any
divider clocks are present. While at it, also make sure the iomem
pointer is NULL if no composite/divider clocks are declared, as we
are checking for that when iounmapping it in the error path.
This hasn't been seen on any MediaTek clock driver as the current ones
always declare composite clocks along with divider clocks, but this is
still an important fix for a future potential KP.
Fixes: 1fe074b1f112 ("clk: mediatek: Add divider clocks to mtk_clk_simple_{probe,remove}()") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230615122051.546985-2-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jai Luthra [Thu, 15 Jun 2023 11:55:36 +0000 (17:25 +0530)]
clk: keystone: syscon-clk: Add support for audio refclk
TI's AM62 SoC can optionally provide two audio reference clocks
(AUDIO_REFCLKx) to external peripherals.
By default this reference clock is looped-back inside the SoC to a mux
that goes to McASP AHCLK, but can optionally be enabled as an output to
peripherals outside the SoC by setting a bit through CTRL_MMR registers.
This bit only controls the direction of the clock, while the parent
is a muxed input from sci-clk [1] which may be a configurable PLL or a
master clock from one of the McASP instances.
This node's register space is not accessed by any other node, which
is the traditional use for the "syscon" hint. It looks to have been
added here to make use of a Linux kernel helper syscon_node_to_regmap().
The Linux driver now uses a more appropriate helper that does not
require the hint, so let's remove it from the binding.
Andrew Davis [Tue, 16 May 2023 18:46:25 +0000 (13:46 -0500)]
clk: keystone: syscon-clk: Allow the clock node to not be of type syscon
There is a helper device_node_to_regmap() we can use that does not force
this clock DT node to be a "syscon" node. It should work the same in
this case but allow us to remove the unneeded "syscon" compatible.
Krzysztof Kozlowski [Fri, 9 Jun 2023 14:07:51 +0000 (16:07 +0200)]
dt-bindings: clock: drop unneeded quotes and use absolute /schemas path
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint. Also absolute path
starting with /schemas is preferred.
Lukas Bulwahn [Wed, 14 Jun 2023 08:42:12 +0000 (10:42 +0200)]
MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK
Commit e6c6ddb397e2 ("dt-bindings: clock: meson: add A1 PLL clock
controller bindings") adds a file entry with pattern
"include/dt-bindings/clock/a1*" to the ARM/Amlogic Meson SoC CLOCK
FRAMEWORK section. However, all header files added in the patch series to
add Amlogic A1 clock controller drivers carry the prefix "amlogic,a1", and
there are not header files matching "a1*".
Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a
broken reference.
Adjust the pattern of this file entry to match the headers actually added.
Patrick Delaunay [Wed, 10 May 2023 16:51:40 +0000 (18:51 +0200)]
dt-bindings: rcc: stm32: Sync with u-boot copy for STM32MP13 SoC
Minor cosmetic change, aligned with files in U-Boot:
- change obsolete SPDX id : GPL-2.0+ and use the same license
GPL-2.0-only for the 2 files
- use correct mail address gabriel.fernandez@foss.st.com
- remove extra space
Dan Carpenter [Thu, 11 May 2023 17:01:20 +0000 (20:01 +0300)]
clk: clocking-wizard: Fix Oops in clk_wzrd_register_divider()
Smatch detected this potential error pointer dereference
clk_wzrd_register_divider(). If devm_clk_hw_register() fails then
it sets "hw" to an error pointer and then dereferences it on the
next line. Return the error directly instead.
Fixes: 5a853722eb32 ("staging: clocking-wizard: Add support for dynamic reconfiguration") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/f0e39b5c-4554-41e0-80d9-54ca3fabd060@kili.mountain Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dan Carpenter [Fri, 21 Apr 2023 10:41:01 +0000 (13:41 +0300)]
clk: bcm: rpi: Fix off by one in raspberrypi_discover_clocks()
Smatch detected an off by one in this code:
drivers/clk/bcm/clk-raspberrypi.c:374 raspberrypi_discover_clocks()
error: buffer overflow 'data->hws' 16 <= 16
The data->hws[] array has RPI_FIRMWARE_NUM_CLK_ID elements so the >
comparison needs to changed to >=.
Fixes: 12c90f3f27bb ("clk: bcm: rpi: Add variant structure") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/5a850b08-d2f5-4794-aceb-a6b468965139@kili.mountain Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Yang Li [Fri, 28 Apr 2023 07:00:05 +0000 (15:00 +0800)]
clk: sifive: Use devm_platform_ioremap_resource()
Convert platform_get_resource(),devm_ioremap_resource() to a single
call to devm_platform_ioremap_resource(), as this is exactly what this
function does.
Stephen Boyd [Wed, 14 Jun 2023 20:58:01 +0000 (13:58 -0700)]
Merge tag 'clk-microchip-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Claudiu Beznea:
Polarfire:
- new Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip FPGA
clock drivers
PIC32:
- use of_property_read_bool() to read "microchip,pic32mzda-sosc" boolean
DT property in clk-pic32mzda
AT91:
- convert clock dt-bindings to YAML
* tag 'clk-microchip-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
dt-bindings: clocks: at91sam9x5-sckc: convert to yaml
dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml
clk: microchip: Use of_property_read_bool() for boolean properties
clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
Stephen Boyd [Wed, 14 Jun 2023 20:43:35 +0000 (13:43 -0700)]
Merge tag 'clk-imx-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX
- Keep UART clocks enabled during kernel boot if earlycon is set
- Drop the imx_unregister_clocks as there are no users for it
- Switch to _safe iterator on imx_clk_scu_unregister to avoid use after free
- Add determine_rate op to the imx8m composite clock
- Use device managed API for iomap and kzalloc for i.MXRT1050,
i.MX8MN, i.MX8MP and i.MX93 clock controller drivers
- Add missing interrupt DT property for the i.MX8M clock controller
* tag 'clk-imx-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()
clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe
clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe
dt-bindings: clock: imx8m: Add missing interrupt property
clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe
clk: imx: composite-8m: Add imx8m_divider_determine_rate
clk: imx: scu: use _safe list iterator to avoid a use after free
clk: imx: drop imx_unregister_clocks
clk: imx6ul: retain early UART clocks during kernel init
clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks
The sprd_div_helper_round_rate() function calls divider_round_rate()
which calls divider_round_rate_parent() which calls
divider_determine_rate(). This call chain converts back and forth from
the rate request structure to make a determine_rate clk_op fit with a
round_rate clk_op. Simplify the code here by directly calling
divider_determine_rate() instead.
This fixes a smatch warning where an unsigned long is compared to less
than zero, which is impossible. This makes sprd_div_helper_round_rate()
unnecessary as well so simply remove it and fold it into the only caller
left.
Reported-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Closes: https://lore.kernel.org/r/45fdc54e-7ab6-edd6-d55a-473485608473@oracle.com Cc: Maxime Ripard <maxime@cerno.tech> Fixes: 302d2f836d78 ("clk: sprd: composite: Switch to determine_rate") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230613195443.1555132-1-sboyd@kernel.org Reviewed-by: Maxime Ripard <mripard@kernel.org>
Konrad Dybcio [Mon, 29 May 2023 13:14:24 +0000 (15:14 +0200)]
clk: qcom: gpucc-sm6375: Enable runtime pm
The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter
rail is not online, GX_GDSC will never turn on. Enable runtime pm so that
we can reference VDD_GX from the dt to ensure that.
Bjorn Andersson [Tue, 13 Jun 2023 22:19:18 +0000 (15:19 -0700)]
Merge branch '20230526161129.1454-2-quic_anusha@quicinc.com' into clk-for-6.5
Merge the DeviceTree binding updates for IPQ9574 GCC adding clocks and
resets related to Crypto Engine, through a topic branch in order to make
them available in the DeviceTree source tree as well.
Marek Szyprowski [Tue, 13 Jun 2023 13:16:31 +0000 (15:16 +0200)]
clk: Fix best_parent_rate after moving code into a separate function
best_parent_rate entry is still being used in the code and needs to be
always updated regardless of the CLK_SET_RATE_NO_REPARENT flag.
Fixes: 1b4e99fda73f ("clk: Move no reparent case into a separate function") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230613131631.270192-1-m.szyprowski@samsung.com Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Srinivas Kandagatla [Thu, 8 Jun 2023 12:53:13 +0000 (13:53 +0100)]
clk: qcom: Add lpass audio clock controller driver for SC8280XP
Add support for the lpass audio clock controller found on SC8280XP based
devices. This would allow lpass peripheral loader drivers to control the
clocks and bring the subsystems out of reset.
Currently this patch only supports resets as the Q6DSP is in control of
LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg
channel.
Srinivas Kandagatla [Thu, 8 Jun 2023 12:53:12 +0000 (13:53 +0100)]
clk: qcom: Add lpass clock controller driver for SC8280XP
Add support for the lpass clock controller found on SC8280XP based devices.
This would allow lpass peripheral loader drivers to control the clocks and
bring the subsystems out of reset.
Currently this patch only supports resets as the Q6DSP is in control of
LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg
channel.
Smatch reports:
drivers/clk/mediatek/clk-mtk.c:583 mtk_clk_simple_probe() warn:
'base' from of_iomap() not released on lines: 496.
This problem was also found in linux-next. In mtk_clk_simple_probe(),
base is not released when handling errors
if clk_data is not existed, which may cause a leak.
So free_base should be added here to release base.
Fixes: c58cd0e40ffa ("clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers") Signed-off-by: Bosi Zhang <u201911157@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Link: https://lore.kernel.org/r/20230422084331.47198-1-u201911157@hust.edu.cn Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Runyang Chen [Thu, 25 May 2023 07:50:11 +0000 (15:50 +0800)]
clk: mediatek: reset: add infra_ao reset support for MT8188
The infra_ao reset is needed for MT8188.
- Add mtk_clk_rst_desc for MT8188.
- Add register reset controller function for MT8188 infra_ao.
- Add infra_ao_idx_map for MT8188.
AngeloGioacchino Del Regno [Tue, 16 May 2023 13:52:05 +0000 (15:52 +0200)]
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances,
share the same parent(s): in order to add parents selection in the
mtk-sd driver to achieve an accurate clock rate for all modes, remove
the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
will make sure that a clk_set_rate() call performed for a clock on
a secondary controller will not change the rate of a common parent,
which would result in an overclock or underclock of one of the
controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Tue, 16 May 2023 13:52:04 +0000 (15:52 +0200)]
clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag
The clk-mux driver was forcing the CLK_SET_RATE_PARENT flag even for
the GATE_CLK_SET_UPD_FLAGS() macro, as in mtk_clk_register_mux() the
flag was unconditionally added.
In preparation for a change on MSDC clock muxes, stop forcing this
flag and, where necessary, update clock drivers to add it so that
with this commit we introduce no functional changes for the currently
supported SoCs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20230516135205.372951-2-angelogioacchino.delregno@collabora.com Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Uwe Kleine-König [Fri, 26 May 2023 06:09:55 +0000 (08:09 +0200)]
clk: si521xx: Switch i2c driver back to use .probe()
After commit b8a1a4cd5a98 ("i2c: Provide a temporary .probe_new()
call-back type"), all drivers being converted to .probe_new() and then 03c835f498b5 ("i2c: Switch .probe() to not take an id parameter")
convert back to (the new) .probe() to be able to eventually drop
.probe_new() from struct i2c_driver.
Stephen Boyd [Mon, 12 Jun 2023 18:27:57 +0000 (11:27 -0700)]
Merge tag 'samsung-clk-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski:
- Re-add support for Exynos4212 clock controller because we are
re-introducing the SoC in the mainline
- Add CONFIG_OF dependency to solve some objtool warnings
* tag 'samsung-clk-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: add CONFIG_OF dependency
clk: samsung: Re-add support for Exynos4212 CPU clock
clk: samsung: Add Exynos4212 compatible to CLKOUT driver
dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible
Arnd Bergmann [Fri, 9 Jun 2023 08:15:49 +0000 (10:15 +0200)]
clk: samsung: add CONFIG_OF dependency
When CONFIG_OF is disabled, build testing on x86 runs into a couple of
objtool warnings from functions that unconditionally call panic() but
have no __noreturn annotation:
vmlinux.o: warning: objtool: exynos3250_cmu_isp_probe+0x17: samsung_cmu_register_one() is missing a __noreturn annotation
vmlinux.o: warning: objtool: exynos7885_cmu_probe+0x16: exynos_arm64_register_cmu() is missing a __noreturn annotation
vmlinux.o: warning: objtool: exynos850_cmu_probe+0x16: exynos_arm64_register_cmu() is missing a __noreturn annotation
vmlinux.o: warning: objtool: exynosautov9_cmu_probe+0x16: exynos_arm64_register_cmu() is missing a __noreturn annotation
The objtool analysis is correct, and this could be addressed by just
returning success whenever CONFIG_OF is disabled to let all that code
be eliminated, but since the driver is no use without CONFIG_OF,
just add that as a dependency. It will still get compile tested on
all architectures since CONFIG_OF is enabled in allmodconfig and most
randconfig builds.
Yuxing Liu [Wed, 3 May 2023 07:06:07 +0000 (07:06 +0000)]
clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()
Replace of_iomap() and kzalloc() with devm_of_iomap() and devm_kzalloc()
which can automatically release the related memory when the device
or driver is removed or unloaded to avoid potential memory leak.
In this case, iounmap(anatop_base) in line 427,433 are removed
as manual release is not required.
Besides, referring to clk-imx8mq.c, check the return code of
of_clk_add_hw_provider, if it returns negtive, print error info
and unregister hws, which makes the program more robust.
Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Yuxing Liu <lyx2022@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230503070607.2462-1-lyx2022@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Hao Luo [Tue, 11 Apr 2023 01:51:07 +0000 (09:51 +0800)]
clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe
Use devm_of_iomap() instead of of_iomap() to automatically handle
the unused ioremap region.
If any error occurs, regions allocated by kzalloc() will leak,
but using devm_kzalloc() instead will automatically free the memory
using devm_kfree().
Fixes: daeb14545514 ("clk: imx: imx8mn: Switch to clk_hw based API") Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Hao Luo <m202171776@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230411015107.2645-1-m202171776@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Kai Ma [Tue, 18 Apr 2023 11:34:51 +0000 (11:34 +0000)]
clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe
Use devm_of_iomap() instead of of_iomap() to automatically
handle the unused ioremap region. If any error occurs, regions allocated by
kzalloc() will leak, but using devm_kzalloc() instead will automatically
free the memory using devm_kfree().
Also, fix error handling of hws by adding unregister_hws label, which
unregisters remaining hws when iomap failed.
Fixes: 7154b046d8f3 ("clk: imx: Add initial support for i.MXRT1050 clock driver") Signed-off-by: Kai Ma <kaima@hust.edu.cn> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230418113451.151312-1-kaima@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Currently, certain clocks are derrived as a divider from their
parent clock. For some clocks, even when CLK_SET_RATE_PARENT
is set, the parent clock is not properly set which can lead
to some relatively inaccurate clock values.
Unlike imx/clk-composite-93 and imx/clk-divider-gate, it
cannot rely on calling a standard determine_rate function,
because the 8m composite clocks have a pre-divider and
post-divider. Because of this, a custom determine_rate
function is necessary to determine the maximum clock
division which is equivalent to pre-divider * the
post-divider.
With this added, the system can attempt to adjust the parent rate
when the proper flags are set which can lead to a more precise clock
value.
On the imx8mplus, no clock changes are present.
On the Mini and Nano, this can help achieve more accurate
lcdif clocks. When trying to get a pixel clock of 31.500MHz
on an imx8m Nano, the clocks divided the 594MHz down, but
left the parent rate untouched which caused a calulation error.
All other clocks rates and parent were the same.
Similar results on imx8mm were found.
Fixes: 690dccc4a0bf ("Revert "clk: imx: composite-8m: Add support to determine_rate"") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20230506195325.876871-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Stephen Boyd [Fri, 9 Jun 2023 21:59:14 +0000 (14:59 -0700)]
Merge tag 'renesas-clk-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Convert the Renesas clock drivers to readl_poll_timeout_atomic()
* tag 'renesas-clk-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()
clk: renesas: mstp: Convert to readl_poll_timeout_atomic()
clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
iopoll: Do not use timekeeping in read_poll_timeout_atomic()
iopoll: Call cpu_relax() in busy loops
Maxime Ripard [Fri, 5 May 2023 11:26:10 +0000 (13:26 +0200)]
clk: Forbid to register a mux without determine_rate
The determine_rate hook allows to select the proper parent and its rate
for a given clock configuration. On another hand, set_parent is there to
change the parent of a mux.
Some clocks provide a set_parent hook but don't implement
determine_rate. In such a case, set_parent is pretty much useless since
the clock framework will always assume the current parent is to be used,
and we will thus never change it.
This situation can be solved in two ways:
- either we don't need to change the parent, and we thus shouldn't
implement set_parent;
- or we don't want to change the parent, in this case we should set
CLK_SET_RATE_NO_REPARENT;
- or we're missing a determine_rate implementation.
The latter is probably just an oversight from the driver's author, and
we should thus raise their awareness about the fact that the current
state of the driver is confusing.
All the drivers in-tree have been converted by now, so let's prevent any
clock with set_parent but without determine_rate to register so that it
can't sneak in again in the future.
Cc: Abel Vesa <abelvesa@kernel.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: "Andreas Färber" <afaerber@suse.de> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Baolin Wang <baolin.wang@linux.alibaba.com> Cc: Charles Keepax <ckeepax@opensource.cirrus.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Chen-Yu Tsai <wenst@chromium.org> Cc: Chunyan Zhang <zhang.lyra@gmail.com> Cc: Claudiu Beznea <claudiu.beznea@microchip.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: David Airlie <airlied@gmail.com> Cc: David Lechner <david@lechnology.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Luca Ceresoli <luca.ceresoli@bootlin.com> Cc: Manivannan Sadhasivam <mani@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Markus Schneider-Pargmann <msp@baylibre.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Miles Chen <miles.chen@mediatek.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Orson Zhai <orsonzhai@gmail.com> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Peng Fan <peng.fan@nxp.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Richard Fitzgerald <rf@opensource.cirrus.com> Cc: Samuel Holland <samuel@sholland.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Takashi Iwai <tiwai@suse.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: dri-devel@lists.freedesktop.org Cc: linux-actions@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-sunxi@lists.linux.dev Cc: linux-tegra@vger.kernel.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: patches@opensource.cirrus.com Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-68-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:09 +0000 (13:26 +0200)]
ASoC: tlv320aic32x4: div: Switch to determine_rate
The tlv320aic32x4 divider clocks implements a mux with a set_parent
hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Jaroslav Kysela <perex@perex.cz> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: Takashi Iwai <tiwai@suse.com> Cc: alsa-devel@alsa-project.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-67-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:08 +0000 (13:26 +0200)]
ASoC: tlv320aic32x4: pll: Switch to determine_rate
The tlv320aic32x4 PLL clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Jaroslav Kysela <perex@perex.cz> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: Takashi Iwai <tiwai@suse.com> Cc: alsa-devel@alsa-project.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-66-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:07 +0000 (13:26 +0200)]
clk: tegra: super: Switch to determine_rate
The Tegra super clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-65-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:06 +0000 (13:26 +0200)]
clk: tegra: periph: Switch to determine_rate
The Tegra periph clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-64-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:05 +0000 (13:26 +0200)]
clk: stm32: composite: Switch to determine_rate
The STM32 composite clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-63-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:04 +0000 (13:26 +0200)]
clk: st: flexgen: Switch to determine_rate
The ST Flexgen clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Maxime Ripard [Fri, 5 May 2023 11:26:03 +0000 (13:26 +0200)]
clk: sprd: composite: Switch to determine_rate
The Spreadtrum composite clocks implements a mux with a set_parent
hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Baolin Wang <baolin.wang@linux.alibaba.com> Cc: Chunyan Zhang <zhang.lyra@gmail.com> Cc: Orson Zhai <orsonzhai@gmail.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-61-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Fri, 5 May 2023 11:26:02 +0000 (13:26 +0200)]
clk: ingenic: tcu: Switch to determine_rate
The Ingenic TCU clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Maxime Ripard [Fri, 5 May 2023 11:26:01 +0000 (13:26 +0200)]
clk: ingenic: cgu: Switch to determine_rate
The Ingenic CGU clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Maxime Ripard [Fri, 5 May 2023 11:26:00 +0000 (13:26 +0200)]
clk: imx: scu: Switch to determine_rate
The iMX SCU clocks implements a mux with a set_parent hook, but doesn't
provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. The round_rate()
implementation being shared with other clocks, it's not removed.
And if it was an oversight, the clock behaviour can be adjusted later
on.
Cc: Abel Vesa <abelvesa@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-58-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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