Bjorn Andersson [Thu, 7 Jan 2021 23:25:26 +0000 (15:25 -0800)]
soc: qcom: mdt_loader: Detect truncated read of segments
Given that no validation of how much data the firmware loader read in
for a given segment truncated segment files would best case result in a
hash verification failure, without any indication of what went wrong.
Improve this by validating that the firmware loader did return the
amount of data requested.
Bjorn Andersson [Thu, 7 Jan 2021 23:31:19 +0000 (15:31 -0800)]
soc: qcom: mdt_loader: Validate that p_filesz < p_memsz
The code validates that segments of p_memsz bytes of a segment will fit
in the provided memory region, but does not validate that p_filesz bytes
will, which means that an incorrectly crafted ELF header might write
beyond the provided memory region.
The ARM Cortex-A53 CPU cores and QGIC2 interrupt controller
(an implementation of the ARM GIC 2.0 specification) used in MSM8916
support virtualization, e.g. for KVM on Linux. However, so far it was
not possible to make use of this functionality, because Qualcomm's
proprietary "hyp" firmware blocks the EL2 mode of the CPU and only
allows booting Linux in EL1.
However, on devices without (firmware) secure boot there is no need
to rely on all of Qualcomm's firmware. The "hyp" firmware on MSM8916
seems simple enough that it can be replaced with an open-source
alternative created only based on trial and error - with some similar
EL2/EL1 initialization code adapted from Linux and U-Boot.
qhypstub [1] is such an open-source firmware for MSM8916 that
can be used as drop-in replacement for Qualcomm's "hyp" firmware.
It does not implement any hypervisor functionality.
Instead, it allows booting Linux/KVM (or other hypervisors) in EL2.
With Linux booting in EL2, KVM seems to be working just fine on MSM8916.
However, so far it is not possible to make use of the virtualization
features in the GICv2. To use KVM's VGICv2 code, the QGIC2 device tree
node needs additional resources (according to binding documentation):
- The CPU interface region (second reg) must be at least 8 KiB large
to access the GICC_DIR register (mapped at 0x1000 offset)
- Virtual control/CPU interface register base and size
- Hypervisor maintenance interrupt
Fortunately, the public APQ8016E TRM [2] provides the required information:
- The CPU interface region (at 0x0B002000) actually has a size of 8 KiB
- Virtual control/CPU interface register is at 0x0B001000/0x0B004000
- Hypervisor maintenance interrupt is "PPI #0"
Note: This is a bit strange since almost all other ARM SoCs use
GIC_PPI 9 for this. However, I have verified that this is
indeed the interrupt that fires when bits are set in GICH_HCR.
Add the additional resources to the QGIC2 device tree node in msm8916.dtsi.
There is no functional difference when Linux is started in EL1 since the
additional resources are ignored in that case.
With these changes (and qhypstub), KVM seems to be fully working on
the DragonBoard 410c (apq8016-sbc) and BQ Aquaris X5 (longcheer-l8910).
Stephen Boyd [Tue, 23 Feb 2021 21:45:38 +0000 (13:45 -0800)]
firmware: qcom_scm: Fix kernel-doc function names to match
These functions were renamed but the kernel doc didn't follow along. Fix
it.
Cc: Elliot Berman <eberman@codeaurora.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Fixes: 9a434cee773a ("firmware: qcom_scm: Dynamically support SMCCC and legacy conventions") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210223214539.1336155-6-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
We don't want userspace ejecting this driver at runtime. Various other
drivers call into this code because it provides the mechanism to
communicate with the secure world on qcom SoCs. It should probe once and
be present forever after that.
Cc: Elliot Berman <eberman@codeaurora.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210223214539.1336155-5-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Stephen Boyd [Tue, 23 Feb 2021 21:45:36 +0000 (13:45 -0800)]
firmware: qcom_scm: Workaround lack of "is available" call on SC7180
Some SC7180 firmwares don't implement the QCOM_SCM_INFO_IS_CALL_AVAIL
API, so we can't probe the calling convention. We detect the legacy
calling convention on these firmwares, because the availability call
always fails and legacy is the fallback. This leads to problems where
the rmtfs driver fails to probe, because it tries to assign memory with
a bad calling convention, which then leads to modem failing to load and
all networking, even wifi, to fail. Ouch!
Let's force the calling convention to be what it always is on this SoC,
i.e. arm64. Of course, the calling convention is not the same thing as
implementing the QCOM_SCM_INFO_IS_CALL_AVAIL API. The absence of the "is
this call available" API from the firmware means that any call to
__qcom_scm_is_call_available() fails. This is OK for now though because
none of the calls that are checked for existence are implemented on
firmware running on sc7180. If such a call needs to be checked for
existence in the future, we presume that firmware will implement this
API and then things will "just work".
Cc: Elliot Berman <eberman@codeaurora.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Fixes: 9a434cee773a ("firmware: qcom_scm: Dynamically support SMCCC and legacy conventions") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210223214539.1336155-4-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Stephen Boyd [Tue, 23 Feb 2021 21:45:35 +0000 (13:45 -0800)]
firmware: qcom_scm: Reduce locking section for __get_convention()
We shouldn't need to hold this spinlock here around the entire SCM call
into the firmware and back. Instead, we should be able to query the
firmware, potentially in parallel with other CPUs making the same
convention detection firmware call, and then grab the lock to update the
calling convention detected. The convention doesn't change at runtime so
calling into firmware more than once is possibly wasteful but simpler.
Besides, this is the slow path, not the fast path where we've already
detected the convention used.
More importantly, this allows us to add more logic here to workaround
the case where the firmware call to check for availability isn't
implemented in the firmware at all. In that case we can check the
firmware node compatible string and force a calling convention.
Note that we remove the 'has_queried' logic that is repeated twice. That
could lead to the calling convention being printed multiple times to the
kernel logs if the bool is true but __query_convention() is running on
multiple CPUs. We also shorten the time where the lock is held, but we
keep the lock held around the printk because it doesn't seem hugely
important to drop it for that.
Cc: Elliot Berman <eberman@codeaurora.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Fixes: 9a434cee773a ("firmware: qcom_scm: Dynamically support SMCCC and legacy conventions") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210223214539.1336155-3-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Stephen Boyd [Tue, 23 Feb 2021 21:45:34 +0000 (13:45 -0800)]
firmware: qcom_scm: Make __qcom_scm_is_call_available() return bool
Make __qcom_scm_is_call_available() return bool instead of int. The
function has "is" in the name, so it should return a bool to indicate
the truth of the call being available. Unfortunately, it can return a
number < 0 which also looks "true", but not all callers expect that and
thus they think a call is available when really the check to see if the
call is available failed to figure it out.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Elliot Berman <eberman@codeaurora.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Fixes: 0f206514749b ("scsi: firmware: qcom_scm: Add support for programming inline crypto keys") Fixes: 0434a4061471 ("firmware: qcom: scm: add support to restore secure config to qcm_scm-32") Fixes: b0a1614fb1f5 ("firmware: qcom: scm: add OCMEM lock/unlock interface") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210223214539.1336155-2-swboyd@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Bjorn Andersson [Fri, 12 Mar 2021 00:33:17 +0000 (16:33 -0800)]
soc: qcom: wcnss_ctrl: Allow reading firmware-name from DT
The WLAN NV firmware blob differs between platforms, and possibly
devices, so add support in the wcnss_ctrl driver for reading the path of
this file from DT in order to allow these files to live in a generic
file system (or linux-firmware).
The new property is optional and the code falls back to the old filename
if the property isn't specified.
The WCNSS needs firmware which differs between platforms, and possibly
boards. Add a new property "firmware-name" to allow the DT to specify
the platform/board specific path to this firmware file.
arm64: dts: qcom: sdm845-xiaomi-beryllium: Add DSI and panel bits
Enabling the Display panel for beryllium requires DSI
labibb regulators and panel dts nodes to be added.
It is also required to keep some of the regulators as
always-on.
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210404194437.537011-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Jami Kettunen [Tue, 6 Apr 2021 01:07:07 +0000 (04:07 +0300)]
arm64: dts: qcom: Add support for OnePlus 5/5T
Add device trees for OnePlus 5 (cheeseburger) and 5T (dumpling)
MSM8998 SoC smartphones with initial support included for:
- UFS internal storage
- USB peripheral mode
- Display
- Touch
- Bluetooth
- Hall effect sensor
- Power and volume buttons
- Capacitive keypad button backlight (on cheeseburger)
Sujit Kautkar [Tue, 30 Mar 2021 01:46:10 +0000 (18:46 -0700)]
arm64: dts: qcom: Move rmtfs memory region
Move rmtfs memory region so that it does not overlap with system
RAM (kernel data) when KAsan is enabled. This puts rmtfs right
after mba_mem which is not supposed to increase beyond 0x94600000
arm64: dts: qcom: Add sound node for sc7180-trogdor-coachz
This is a trgodor variant, required to have sound node variable
for coachz specific platform.
Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210314061054.19451-3-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Ajit Pandey [Sun, 14 Mar 2021 06:10:53 +0000 (11:40 +0530)]
arm64: dts: qcom: sc7180-trogdor: Add lpass dai link for I2S driver
Add dai link for supporting lpass I2S driver, which is used
for audio capture and playback.
Add lpass-cpu node with pin controls and i2s primary
and secondary dai-links.
Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/20210314061054.19451-2-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Maxim fuel gauge datasheets describe the interrupt line as active
low with a requirement of acknowledge from the CPU. The falling edge
interrupt will mostly work but it's not correct.
The Maxim fuel gauge datasheets describe the interrupt line as active
low with a requirement of acknowledge from the CPU. The falling edge
interrupt will mostly work but it's not correct.
./include/linux/soc/qcom/qmi.h:26: warning: cannot understand function prototype: 'struct qmi_header '
./include/linux/soc/qcom/qmi.h:101: warning: cannot understand function prototype: 'struct qmi_response_type_v01 '
./include/linux/soc/qcom/irq.h:19: warning: expecting prototype for QCOM specific IRQ domain flags that distinguishes the handling of wakeup(). Prototype was for IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP() instead
./include/linux/soc/qcom/apr.h:126: warning: Function parameter or member '__apr_driver' not described in 'module_apr_driver'
./include/linux/soc/qcom/apr.h:126: warning: Excess function parameter '__aprbus_driver' description in 'module_apr_driver'
./include/linux/soc/qcom/llcc-qcom.h:43: warning: cannot understand function prototype: 'struct llcc_slice_desc '
./include/linux/soc/qcom/llcc-qcom.h:60: warning: cannot understand function prototype: 'struct llcc_edac_reg_data '
./include/linux/soc/qcom/llcc-qcom.h:86: warning: cannot understand function prototype: 'struct llcc_drv_data '
Address all those warnings by:
- prefixing kernel-doc descriptions for structs with the keyword 'struct',
- turning a kernel-doc comment that does not follow the kernel-doc syntax
into a normal comment, and
- correcting a parameter name in a kernel-doc comment.
Robert Foss [Wed, 24 Mar 2021 12:43:10 +0000 (13:43 +0100)]
arm64: dts: qcom: sm8350: Add thermal zones and throttling support
sm8350 has 29 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle their
frequencies on crossing passive temperature thresholds.
Jonathan Marek [Mon, 29 Mar 2021 12:00:48 +0000 (15:00 +0300)]
arm64: dts: qcom: sm8250: fix display nodes
Apply these fixes to the newly added sm8250 display ndoes
- Remove "notused" interconnect (which apparently was blindly copied from
my old patches)
- Use dispcc node example from dt-bindings, removing clocks which aren't
documented or used by the driver and fixing the region size.
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[DB: compatibility changes split into separate patch] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210329120051.3401567-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Pan Bian [Thu, 21 Jan 2021 11:49:07 +0000 (03:49 -0800)]
bus: qcom: Put child node before return
Put child node before return to fix potential reference count leak.
Generally, the reference count of child is incremented and decremented
automatically in the macro for_each_available_child_of_node() and should
be decremented manually if the loop is broken in loop body.
Dmitry Baryshkov [Wed, 10 Feb 2021 13:34:58 +0000 (16:34 +0300)]
arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS
On the GENI SPI controller is is not very efficient if the chip select
line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts:
qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the
details). Configure SPI0 CS pin as a GPIO.
Dmitry Baryshkov [Wed, 10 Feb 2021 13:34:57 +0000 (16:34 +0300)]
arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS
GENI SPI controller shows several issues if it manages the CS on its own
(see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to
use GPIO for CS")) for the details. Provide pinctrl entries for SPI
controllers using the same CS pin but in GPIO mode.
Dmitry Baryshkov [Wed, 10 Feb 2021 13:34:56 +0000 (16:34 +0300)]
arm64: dts: qcom: sm8250: further split of spi pinctrl config
Split "default" device tree nodes into common "data-clk" nodes and "cs"
nodes which might differ from board to board depending on how the slave
chips are wired.
As discussed on linux-arm-msm list, start splitting sm8250 pinctrl
settings into generic and board-specific parts. The first part to
receive such treatment is the spi, so split spi pinconf to the board
device tree.
Bjorn Andersson [Wed, 6 Jan 2021 00:10:04 +0000 (16:10 -0800)]
arm64: dts: qcom: pm8150: Enable RTC
The PM8150 comes with everything the RTC needs, so let's just leave it
enabled instead of having to explicitly enable it for all boards.
In effect this patch enables the RTC on the SM8150 MTP and the SM8250
HDK.
Srinivas Kandagatla [Tue, 9 Mar 2021 10:20:25 +0000 (10:20 +0000)]
arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881x
WSA881x powerdown pin is connected to GPIO1 not gpio2, so correct this.
This was working so far due to a shift bug in gpio driver, however
once that is fixed this will stop working, so fix this!
Stephen Boyd [Thu, 11 Mar 2021 21:12:41 +0000 (13:12 -0800)]
arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdor
This moved from being trogdor specific to being part of the general
sc7180.dtsi SoC file in commit 681a607ad21a ("arm64: dts: qcom:
sc7180: Add DisplayPort HPD pin dt node"). Then we dropped the pinconf
from the general sc7180.dtsi file in commit 8d079bf20410 ("arm64: dts:
qcom: sc7180: Drop pinconf on dp_hot_plug_det") and added it back to
the trogdor dts file in commit f772081f4883 ("arm64: dts: qcom:
sc7180: Add "dp_hot_plug_det" pinconf for trogdor").
As part of this we managed to forget to drop the old copy in the
trogdor dts. Let's do it now.
Shawn Guo [Wed, 3 Mar 2021 03:31:06 +0000 (11:31 +0800)]
arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'
The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.
This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.
Shawn Guo [Wed, 3 Mar 2021 03:31:05 +0000 (11:31 +0800)]
arm64: dts: qcom: sm8250: fix number of pins in 'gpio-ranges'
The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.
This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.
Shawn Guo [Wed, 3 Mar 2021 03:31:04 +0000 (11:31 +0800)]
arm64: dts: qcom: sm8150: fix number of pins in 'gpio-ranges'
The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.
This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.
Shawn Guo [Wed, 3 Mar 2021 03:31:03 +0000 (11:31 +0800)]
arm64: dts: qcom: sdm845: fix number of pins in 'gpio-ranges'
The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.
This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.
Maulik Shah [Thu, 11 Mar 2021 11:26:00 +0000 (16:56 +0530)]
arm64: dts: qcom: sc7280: Add cpuidle states
Add cpuidle states for little and big cpus.
The latency values are preliminary placeholders and will be updated
once testing provides the real numbers.
Sai Prakash Ranjan [Thu, 11 Mar 2021 11:25:55 +0000 (16:55 +0530)]
arm64: dts: qcom: sc7280: Add device node for APPS SMMU
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Bjorn Andersson [Mon, 8 Mar 2021 18:21:13 +0000 (10:21 -0800)]
arm64: dts: qcom: Introduce SM8350 HDK
Add initial DTS for the Snapdragon 888 Mobile Hardware Development Kit,
aka SM8350 HDK. This initial version describes debug UART, UFS storage,
the three USB connectors and remoteprocs.
Document the ipq6018-cp01 board. It was missing leading to warning:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed:
['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too short
['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too long
Additional items are not allowed ('qcom,ipq6018' was unexpected)
Vinod Koul [Mon, 8 Mar 2021 06:08:09 +0000 (11:38 +0530)]
arm64: dts: qcom: apq8016-sbc: drop qcom,sbc
apq8016-sbc is one of the compaitibles for this board, but is not
documented, so drop it. This fixes these two warns:
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc']
is not valid under any of the given schemas (Possible causes of the failure):
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is too long
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc'
is not one of ['qcom,apq8064-cm-qs600', 'qcom,apq8064-ifc6410']
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc'
is not one of ['qcom,apq8074-dragonboard']
Douglas Anderson [Thu, 18 Feb 2021 22:55:09 +0000 (14:55 -0800)]
arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor
At boot time the following happens:
1. Device core gets ready to probe our SPI driver.
2. Device core applies SPI controller's "default" pinctrl.
3. Device core calls the SPI driver's probe() function which will
eventually setup the chip select GPIO as "unasserted".
Thinking about the above, we can find:
a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would
have had them configured as "GENI" pins and not as "GPIO" pins.
b) It turns out that our BIOS also happens to init these pins as
"output" (even though it doesn't need to since they're not muxed as
GPIO) but leaves them at the default state of "low".
c) As soon as we apply the "default" chip select it'll switch the
function to GPIO and stop driving the chip select high (which is
how "GENI" was driving it) and start driving it low.
d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the
new method of gpio CS control"), when the SPI core inits things it
inits the GPIO to be "deasserted". Prior to that commit the GPIO
was left untouched until first use.
e) When the first transaction happens we'll assert the chip select and
then deassert it after done.
So before the commit to change us to use gpio descriptors we used to
have a _really long_ assertion of chip select before our first
transaction (because it got pulled down and then the first "assert"
was a no-op). That wasn't great but (apparently) didn't cause any
real harm.
After the commit to change us to use gpio descriptors we end up
glitching the chip select line during probe. It would go low and then
high with no data transferred. The other side ought to be robust
against this, but it certainly could cause some confusion. It's known
to at least cause an error message on the EC console and it's believed
that, under certain timing conditions, it could be getting the EC into
a confused state causing the EC driver to fail to probe.
Let's fix things to avoid the glitch. We'll add an extra pinctrl
entry that sets the value of the pin to output high (CS deasserted)
before doing anything else. We'll do this in its own pinctrl node
that comes before the normal pinctrl entries to ensure that the order
is correct and that this gets applied before the mux change.
This change is in the trogdor board file rather than in the SoC dtsi
file because chip select polarity can be different depending on what's
hooked up and it doesn't feel worth it to spam the SoC dtsi file with
both options. The board file would need to pick the right one anyway.
Douglas Anderson [Mon, 1 Mar 2021 21:34:37 +0000 (13:34 -0800)]
arm64: dts: qcom: Add sc7180-trogdor-coachz skus
This is a trogdor variant. This is mostly a grab from the downstream
tree with notable exceptions:
- I skip -rev0. This was a super early build and there's no advantage
of long term support.
- I remove sound node since sound hasn't landed upstream yet.
Cc: Gwendal Grignou <gwendal@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.13.I3d1f5f8a3bf31e8014229df0d4cfdff20e9cc90f@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Douglas Anderson [Mon, 1 Mar 2021 21:34:36 +0000 (13:34 -0800)]
arm64: dts: qcom: Add sc7180-trogdor-pompom skus
This is a trogdor variant. This is mostly a grab from the downstream
tree with notable exceptions:
- I skip -rev0. This was a super early build and there's no advantage
of long term support.
- In -rev1 I translate the handling of the USB hub like is done for
similar boards. See the difference between the downstream and
upstream 'sc7180-trogdor-lazor-r0.dts' for an example. This will
need to be resolved when proper support for the USB hub is figured
out upstream.
- I remove sound node since sound hasn't landed upstream yet.
- In incorporate the pending <https://crrev.com/c/2719075> for the
keyboard.
Cc: Philip Chen <philipchen@google.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.12.If93a01b30d20dccacbad4be8ddc519dc20a51a1e@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Douglas Anderson [Mon, 1 Mar 2021 21:34:35 +0000 (13:34 -0800)]
arm64: dts: qcom: Add sc7180-lazor-limozeen skus
This is a SKU variant of lazor. Add it. This squashes the downstream
patches to support this hardware.
NOTES:
- The non-touch SKU actually has "innolux,n116bca-ea1" but that driver
is still pending in simple-panel. The bindings have been Acked
though [1]. Things work well enough with the "innolux,n116bge"
timings for now, though.
- The wonky special dts just for "-rev4" arguably doesn't need to go
upstream since they weren't widely distributed, but since a few
people have them we might as well. If it ever causes problems we
can delete it.
Matthias Kaehlcke [Mon, 1 Mar 2021 21:34:34 +0000 (13:34 -0800)]
arm64: dts: qcom: sc7180: Set up lazor r3+ as sc7180-lite SKUs
Lazor rev3 and later use the 'lite' version of the SC7180 SoC.
Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
[dianders: Adjust commit message which referred to downstream history] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.10.Ia3795e192f5bbe17e6714e45fcb0bf5acdbd4c17@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Abhishek Kumar [Mon, 1 Mar 2021 21:34:33 +0000 (13:34 -0800)]
arm64: dts: qcom: sc7180: add GO_LAZOR variant property for lazor
For trogdor, in the latest board-2.bin file, new BDF with variant
name GO_LAZOR has been introduced, so we need this property set, for
GO_LAZOR BDF to be picked.
Cc: Philip Chen <philipchen@chromium.org> Signed-off-by: Abhishek Kumar <kuabhs@chromium.org>
[dianders: adjusted subject line and sort order] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.9.I4a38fe64dd79c54af80d7e4ef5940f8cf4f86e75@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Alexandru M Stan [Mon, 1 Mar 2021 21:34:31 +0000 (13:34 -0800)]
arm64: dts: qcom: sc7180-trogdor: Remove fp control pins in prep for coachz
Removed the pinctrl and pin{mux,conf} for the control pins because:
1. The only need for them is for userspace control via flash_fp_mcu
2. cros-ec doesn't know what to do with them, and even if it did,
it would interfere with flash_fp_mcu at the most inopportune times
Since we're not using hogs, we rely on AP firmware to set all the
control pins correctly.
Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Craig Hesling <hesling@chromium.org> Signed-off-by: Alexandru M Stan <amstan@chromium.org>
[dianders: adjusted since coachz isn't upstream yet]
Reviewed-by; Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.7.Ifd7b86f826b18410eada75758a7bca1eebfa336d@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Stephen Boyd [Mon, 1 Mar 2021 21:34:30 +0000 (13:34 -0800)]
arm64: dts: qcom: Disable camera clk on sc7180-trogdor devices by default
We only want to use this clk driver on CoachZ devices. Disable it for
all other Trogdor boards. NOTE: CoachZ devices aren't yet supported
upstream so until it is this is just disabled for all trogdor.
Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[dianders:adjusted since no coachz upstream yet] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.6.I22522b0c9db505ee43ed08e8d5d9e8fe632e7447@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Stephen Boyd [Mon, 1 Mar 2021 21:34:29 +0000 (13:34 -0800)]
arm64: dts: qcom: trogdor: Only wakeup from pen eject
Configure the pen to be a wakeup source only when the pen is ejected
instead of both when the pen is ejected and inserted. This corresponds
to wake source requirements.
Douglas Anderson [Mon, 1 Mar 2021 21:34:27 +0000 (13:34 -0800)]
arm64: dts: qcom: Prep sc7180-trogdor trackpad IRQ for new boards
The trackpad interrupt got renamed and also moved to a new GPIO on
newer boards. Let's do the move in the "trogdor.dtsi" file and then
undo it in the two old boards.
NOTE: since none of the new boards have device trees yet, this change
looks silly on its own but it will make sense after more boards are
supported.
Drop the old node and add the new one in its place.
Cc: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[dianders: Adjusted due to DP not itself not in upstream dts yet] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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