Rob Herring [Thu, 6 Dec 2018 19:11:42 +0000 (13:11 -0600)]
ARM: dts: sunxi: Fix PMU compatible strings
"arm,cortex-a15-pmu" is not a valid fallback compatible string for an
Cortex-A7 PMU, so drop it.
Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Chen-Yu Tsai [Mon, 3 Dec 2018 14:58:25 +0000 (22:58 +0800)]
arm64: dts: allwinner: a64: Fix up RTC device node and clock references
The RTC module on the A64 was claimed to be the same as on the A31, when
in fact it is not. It is actually compatible to the H3's RTC. The A64's
RTC has some extra crypto-related registers which the H3's does not, but
the exact function of these is not clear.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 3 Dec 2018 14:58:24 +0000 (22:58 +0800)]
ARM: dts: sun8i: r40: Add RTC device node
The R40 has an RTC hardware block, which has additional registers
that are not related to RTC or clock functions, and is otherwise
compatible with the H3's RTC.
Add a device node for it, and fix up any references to the LOSC.
Chen-Yu Tsai [Mon, 3 Dec 2018 14:58:22 +0000 (22:58 +0800)]
ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references
The RTC module on the H3 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The H5's RTC has some extra crypto-related registers compared to
the H3. Their exact functions are not clear. Also the RTC-VIO regulator
has different settings.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The device node for the internal oscillator is
removed, as it is internalized into the RTC device. Clock references to
the IOSC and LOSC are also fixed.
Chen-Yu Tsai [Mon, 3 Dec 2018 14:58:20 +0000 (22:58 +0800)]
ARM: dts: sun8i: a23/a33: Fix up RTC device node
The RTC module on the A23 was claimed to be the same as on the A31, when
in fact it is not. The A31 does not have an RTC external clock output,
and its internal RC oscillator's average clock rate is not in the same
range. The A33's RTC is the same as the A23.
This patch fixes the compatible string and clock properties to conform
to the updated bindings. The register range is also fixed.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 3 Dec 2018 14:58:21 +0000 (22:58 +0800)]
ARM: dts: sunxi: h3/h5: Add clock accuracy for external oscillators
The H3 datasheet specifies a tolerance range for the external
oscillators used. Add them to the device tree as the clock accuracy.
The internal oscillator is left unchanged, as it will be removed later.
Chen-Yu Tsai [Wed, 5 Dec 2018 10:11:52 +0000 (18:11 +0800)]
ARM: dts: sun8i: a33: Drop audio codec oversampling rate to 128 fs
The current oversampling rate of 512 means that for 48 kHz 16 bit
stereo, the MCLK is running at the same rate as the module clock,
so there is no head room to support higher sampling rates. The codec
however supports up to 192 kHz for playback.
This patch drops the oversampling rate from 512 to 128, so that 192 kHz
audio can be played back directly without downsampling. Ideally we
should be using different oversampling rates for different sampling
rates, but that's not possible without a platform-specific machine
driver.
Fixes: 870f1bd1f5e9 ("ARM: dts: sun8i: Add audio codec, dai and card for A33") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Chen-Yu Tsai [Wed, 5 Dec 2018 10:11:51 +0000 (18:11 +0800)]
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
All the audio interfaces on Allwinner SoCs need to change their module
clocks during operation, to switch between support for 44.1 kHz and 48
kHz family sample rates. The clock rate for the module clocks is
governed by their upstream audio PLL. The module clocks themselves only
have a gate, and sometimes a divider or mux. Thus any rate changes need
to be propagated upstream.
Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Chen-Yu Tsai [Wed, 5 Dec 2018 10:11:50 +0000 (18:11 +0800)]
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.
The vendor kernel gets around this (for newer SoCs) by using sigma-delta
modulation to generate a fractional-N factor. As the PLL hardware is
identical in most chips, we can back port the settings from the newer
SoC, in this case the H3, onto the A33.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Maxime Ripard [Wed, 5 Dec 2018 11:05:18 +0000 (12:05 +0100)]
Merge branches 'sunxi/core-for-4.21', 'sunxi/drivers-for-4.21', 'sunxi/dt-for-4.21', 'sunxi/dt64-for-4.21' and 'sunxi/h3-h5-for-4.21' into sunxi/for-next
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:44 +0000 (10:24 +0100)]
arm64: dts: allwinner: a64: Add Video Engine node
This adds the Video Engine node for the A64. Since it can map the whole
DRAM range, there is no particular need for a reserved memory node
(unlike platforms preceding the A33).
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Just like on the A33, the video engine on the H3 can map any address in
memory, so there is no particular need to have reserved memory at a fixed
address.
As a result, remove the reserved memory node and let the kernel allocate
the CMA pool wherever it sees fit.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
While we believed that the memory for the video engine had to be kept
in the first 256 MiBs of DRAM, this is no longer true starting with the
A33 and any address can be mapped.
As a result, remove the reserved memory node and let the kernel allocate
the CMA pool wherever it sees fit.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:34 +0000 (10:24 +0100)]
dt-bindings: sram: sunxi: Add bindings for the H5 with SRAM C1
This introduces new bindings for the H5 SoC in the SRAM controller.
Because the SRAM layout is different from other SoCs, no backward
compatibility is assumed with any of them.
However, the C1 SRAM section alone looks similar to previous SoCs,
so it is compatible with the initial A10 binding.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:43 +0000 (10:24 +0100)]
arm64: dts: allwinner: h5: Add Video Engine node
This adds the Video Engine node for the H5. Since it can map the whole
DRAM range, there is no particular need for a reserved memory node
(unlike platforms preceding the A33).
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:37 +0000 (10:24 +0100)]
ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes
The EMAC driver requires a syscon node to access the EMAC clock
configuration register (that is part of the system-control register
range and controlled). For this purpose, a dummy syscon node was
introduced to let the driver access the register freely.
Recently, the EMAC driver was tuned to get access to the register when
the SRAM driver is registered (as used on the A64). As a result, it is
no longer necessary to have a dummy syscon node for that purpose.
Now that we have a proper system-control node for both the H3 and H5,
we can get rid of that dummy syscon node and have the EMAC driver use
the node corresponding to the proper SRAM driver (by switching the
syscon label over to each dtsi). This way, we no longer have two
separate nodes for the same register space.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:36 +0000 (10:24 +0100)]
arm64: dts: allwinner: h5: Add system-control node with SRAM C1
Add the H5-specific system control node description to its device-tree
with support for the SRAM C1 section, that will be used by the video
codec node later on.
The CPU-side SRAM address was obtained empirically while the size was
taken from the documentation. They may not be entirely accurate.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:35 +0000 (10:24 +0100)]
soc: sunxi: sram: Add support for the H5 SoC system control
This adds the H5 SoC compatible to the list of device-tree matches for
the SRAM driver. Since the variant is the same as the A64 (that precedes
the H5), the same variant description is used.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:33 +0000 (10:24 +0100)]
soc: sunxi: sram: Enable EMAC clock access for H3 variant
Just like the A64 and H5, the H3 SoC uses the system control block
to enable the EMAC clock.
Add a variant structure definition for the H3 and use it over the A10
one. This will allow using the H3-specific binding for the syscon node
attached to the EMAC instead of the generic syscon binding.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Paul Kocialkowski [Wed, 5 Dec 2018 09:24:30 +0000 (10:24 +0100)]
ARM: dts: sun8i: h3: Fix the system-control register range
Unlike in previous generations, the system-control register range is not
limited to a size of 0x30 on the H3. In particular, the EMAC clock
configuration register (accessed through syscon) is at offset 0x30 in
that range.
Extend the register size to its full range (0x1000) as a result.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Mesih Kilinc [Sun, 2 Dec 2018 20:23:50 +0000 (23:23 +0300)]
ARM: dts: suniv: add initial DTSI file for F1C100s
F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Mesih Kilinc [Sun, 2 Dec 2018 20:23:47 +0000 (23:23 +0300)]
clk: sunxi-ng: add support for suniv F1C100s SoC
The suniv F1C100s SoC (the chip in some new F-series products of
Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after
sun6i.
Add support for the CCU.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Mesih Kilinc [Sun, 2 Dec 2018 20:23:37 +0000 (23:23 +0300)]
ARM: sunxi: add Allwinner ARMv5 SoCs
Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
used for many new F-series products, including F1C100A, F1C100s, F1C200s,
F1C500, F1C600).
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Oskari Lemmela [Tue, 20 Nov 2018 17:52:07 +0000 (19:52 +0200)]
arm64: dts: allwinner: a64: sopine-baseboard: enable power supplies
AXP803 ACIN pins are routed from SOM to the DC jack on the baseboard.
AXP803 charger pins BATSENSE, LOADSENSE, N_BATDRV, LX_CHG, VIN_CHG
and IPSOUT are connected via PMOS driver to SOM VBAT pins. VBAT and
AXP803 TS pins are routed to the baseboard 3-pin battery connector.
Chen-Yu Tsai [Wed, 28 Nov 2018 09:30:07 +0000 (17:30 +0800)]
clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
On the R40, in addition to a mux between the RTC's own RC oscillator and
an external 32768 Hz crystal, which are muxed inside the RTC module, the
CCU also has its own RC oscillator, which runs at around 2 MHz, and can
be muxed with the LOSC output from the RTC. This muxed output is called
"SYS 32K" in the module clock diagram, but otherwise referred to as the
LOSC throughout the CCU documentation.
The RC oscillator is not very accurate, even though it has an undocumented
calibration function. We really want a precise clock at 32768 Hz,
instead of something at around 32 KHz. This patch forces the SYS 32K
clock to use the RTC output as its parent, and doesn't bother
registering the internal oscillator nor a clock mux.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:39:24 +0000 (09:39 +0100)]
ARM: dts: sun8i: v3s: Remove skeleton and memory to avoid warnings
Our memory node will generate a warning in DTC since the unit address is
not matching the reg property. However, that node will be created by the
bootloader, so we can just remove it entirely in order to remove that
warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 09:58:01 +0000 (10:58 +0100)]
ARM: dts: sun8i: v3s: Change pinctrl nodes to avoid warning
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 10:57:49 +0000 (11:57 +0100)]
ARM: dts: sun8i: BPI-M2M: Remove i2c nodes
The i2c nodes were pre-populated to ease the use of overlays. However, now
that we provide default muxing options for those nodes, the one in the DTS
don't provide any content at all.
Remove them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Tue, 20 Nov 2018 21:03:28 +0000 (22:03 +0100)]
ARM: dts: sun8i: a23/a33: Provide default muxing for relevant controllers
The I2C's and MMC0 controllers have only one muxing option in the SoC. In
such a case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 11:05:00 +0000 (12:05 +0100)]
ARM: dts: sunxi: reference: Move the muxing back to the common DTSI
Now that all the SoCs using the tablet reference design DTSI are using the
same pinctrl naming scheme, we can move back the pinctrl phandles to the
main DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Tue, 20 Nov 2018 20:42:36 +0000 (21:42 +0100)]
ARM: dts: sun8i: a23/a33: Remove underscores from nodes names
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 09:58:01 +0000 (10:58 +0100)]
ARM: dts: sun8i: a23/a33: Change pinctrl nodes to avoid warning
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 10:14:15 +0000 (11:14 +0100)]
ARM: dts: sun8i: a23/a33: Remove all useless pinctrl nodes
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Some boards override the MMC pin muxing settings in order to enable the
pull-ups and change the drive strength to a value higher than the default.
While this was needed in the earlier days, this is now the default setting
for those pins, and therefore we don't need those board-specific settings
anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
The #address-cells and #size-cells are only relevant for nodes that have
childs with reg properties. Otherwise, DTC will emit a warning saying that
those properties are unnecessary.
Remove them when needed.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:51:04 +0000 (09:51 +0100)]
ARM: dts: sun8i: a23/a33: Fix OPP DTC warnings
DTC will emit a warning on our OPPs nodes for the common DTSI between the
A23 and A33 since those nodes use the frequency as unit addresses, but
don't have a matching reg property.
Fix this by moving the frequency to the node name instead.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:39:24 +0000 (09:39 +0100)]
ARM: dts: sun8i: a23/a33: Remove skeleton and memory to avoid warnings
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
The #address-cells and #size-cells are only relevant for nodes that have
childs with reg properties. Otherwise, DTC will emit a warning saying that
those properties are unnecessary.
Remove them when needed.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Some boards override the MMC pin muxing settings in order to enable the
pull-ups and change the drive strength to a value higher than the default.
While this was needed in the earlier days, this is now the default setting
for those pins, and therefore we don't need those board-specific settings
anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Tue, 20 Nov 2018 21:03:28 +0000 (22:03 +0100)]
ARM: dts: sun7i: Provide default muxing for relevant controllers
The I2C and MMC controllers have only one muxing option in the SoC. In such a
case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Fri, 7 Sep 2018 14:00:22 +0000 (16:00 +0200)]
ARM: dts: sun7i: Fix HDMI output DTC warning
Our HDMI output endpoint on the A10s DTSI has a warning under DTC: "graph
node has single child node 'endpoint', #address-cells/#size-cells are not
necessary". Fix this by removing those properties.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Tue, 20 Nov 2018 20:42:36 +0000 (21:42 +0100)]
ARM: dts: sun7i: Remove underscores from nodes names
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Thu, 22 Nov 2018 10:19:35 +0000 (11:19 +0100)]
ARM: dts: sun7i: som204: Use the UART3 TX and RX pin group
The SOM204-EVB doesn't use the CTS pin, and thus was defining its own
pinctrl node for the UART3 muxing. Since we split away the TX and RX pin,
we can use the global node now, and only have the RTS pin in our local
node.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Thu, 22 Nov 2018 10:18:09 +0000 (11:18 +0100)]
ARM: dts: sun7i: Split the RTS and CTS pins out of the UART nodes
Some UART nodes on the A20 DTSI do not share the same pattern that we use
everywhere else, with the RTS and CTS pins split away from the TX and RX
pins. Make those pin groups consistent with the rest of our DT.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 09:58:01 +0000 (10:58 +0100)]
ARM: dts: sun7i: Change pinctrl nodes to avoid warning
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 13:14:58 +0000 (14:14 +0100)]
ARM: dts: sun7i: Change LRADC node names to avoid warnings
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 10:14:15 +0000 (11:14 +0100)]
ARM: dts: sun7i: Remove all useless pinctrl nodes
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 13:03:42 +0000 (14:03 +0100)]
ARM: dts: sun7i: Change clock node names to avoid warnings
Our oscillators clock names have a unit address, but no reg property, which
generates a warning in DTC. Change these names to remove those unit
addresses.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:40:48 +0000 (09:40 +0100)]
ARM: dts: sun7i: Remove SoC node unit-name to avoid warnings
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:39:24 +0000 (09:39 +0100)]
ARM: dts: sun7i: Remove skeleton and memory to avoid warnings
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Tue, 20 Nov 2018 21:03:28 +0000 (22:03 +0100)]
ARM: dts: sun6i: Provide default muxing for relevant controllers
The I2C and MMC controllers have only one muxing option in the SoC. In such a
case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Tue, 20 Nov 2018 20:42:36 +0000 (21:42 +0100)]
ARM: dts: sun6i: Remove underscores from nodes names
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 09:58:01 +0000 (10:58 +0100)]
ARM: dts: sun6i: Change pinctrl nodes to avoid warning
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Some boards override the MMC pin muxing settings in order to enable the
pull-ups and change the drive strength to a value higher than the default.
While this was needed in the earlier days, this is now the default setting
for those pins, and therefore we don't need those board-specific settings
anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 7 Nov 2018 10:14:15 +0000 (11:14 +0100)]
ARM: dts: sun6i: Remove all useless pinctrl nodes
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 13:14:58 +0000 (14:14 +0100)]
ARM: dts: sun6i: Change LRADC node names to avoid warnings
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:40:48 +0000 (09:40 +0100)]
ARM: dts: sun6i: Remove SoC node unit-name to avoid warnings
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 13:03:42 +0000 (14:03 +0100)]
ARM: dts: sun6i: Change clock node names to avoid warnings
Our oscillators clock names have a unit address, but no reg property, which
generates a warning in DTC. Change these names to remove those unit
addresses.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Maxime Ripard [Wed, 21 Nov 2018 08:39:24 +0000 (09:39 +0100)]
ARM: dts: sun6i: Remove skeleton and memory to avoid warnings
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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