Bjorn Helgaas [Mon, 15 Jan 2024 18:10:41 +0000 (12:10 -0600)]
Merge branch 'pci/remove-old-api'
- In dw-xdata-pcie, pci_endpoint_test, and vmd, replace usage of deprecated
ida_simple_*() API with ida_alloc() and ida_free() (Christophe JAILLET)
* pci/remove-old-api:
dw-xdata: Remove usage of the deprecated ida_simple_*() API
misc: pci_endpoint_test: Remove usage of the deprecated ida_simple_*() API
PCI: vmd: Remove usage of the deprecated ida_simple_*() API
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:40 +0000 (12:10 -0600)]
Merge branch 'pci/irq-clean-up'
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec
terminology (Bjorn Helgaas)
- Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence,
designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape,
mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop
the redundant pci_epc_irq_type enum with the same values (Damien Le Moal)
- Use "intx" instead of "leg" or "legacy" when describing INTx interrupts
in endpoint core, endpoint tests, cadence, dra7xx, designware,
dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4,
rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal)
* pci/irq-clean-up:
PCI: xilinx-nwl: Use INTX instead of legacy
PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler()
PCI: rockchip-ep: Use INTX instead of legacy
PCI: uniphier: Use INTX instead of legacy
PCI: tegra194: Use INTX instead of legacy
PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler()
PCI: keystone: Use INTX instead of legacy
PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()
PCI: cadence: Use INTX instead of legacy
PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq()
misc: pci_endpoint_test: Use INTX instead of LEGACY
PCI: endpoint: Rename LEGACY to INTX in test function driver
PCI: endpoint: Use INTX instead of legacy
PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:38 +0000 (12:10 -0600)]
Merge branch 'pci/controller/layerscape'
- Add suspend/resume support for Layerscape LS1043a, including
software-managed PME_Turn_Off and transitions between L0, L2/L3_Ready
Link states (Frank Li)
* pci/controller/layerscape:
PCI: layerscape: Add suspend/resume for ls1043a
PCI: layerscape(ep): Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape: Add function pointer for exit_from_l2()
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:36 +0000 (12:10 -0600)]
Merge branch 'pci/controller/cadence'
- Add j721e DT and driver support for 'num-lanes' for devices that support
x1, x2, or x4 Links (Matt Ranostay)
- Add j721e DT compatible strings and driver support for j784s4 (Matt Ranostay)
- Make TI J721E Kconfig depend on ARCH_K3 since the hardware is specific to
those TI SoC parts (Peter Robinson)
* pci/controller/cadence:
PCI: j721e: Make TI J721E depend on ARCH_K3
PCI: j721e: Add TI J784S4 PCIe configuration
PCI: j721e: Add PCIe 4x lane selection support
PCI: j721e: Add per platform maximum lane settings
dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings
dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:35 +0000 (12:10 -0600)]
Merge branch 'pci/switchtec'
- Do dma_mrpc cleanup during switchtec_pci_remove() to match its devm
ioremapping in switchtec_pci_probe(). Previously the cleanup was done in
stdev_release(), which used stale pointers if stdev->cdev happened to be
open when the PCI device was removed (Daniel Stodden)
* pci/switchtec:
PCI: switchtec: Fix stdev_release() crash after surprise hot remove
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:35 +0000 (12:10 -0600)]
Merge branch 'pci/resource'
- Restructure pci_dev_for_each_resource() to avoid computing the address of
an out-of-bounds array element (the bounds check was performed later so
the element was never actually *read*, but it's nicer to avoid even
computing an out-of-bounds address) (Andy Shevchenko)
* pci/resource:
PCI: Avoid potential out-of-bounds read in pci_dev_for_each_resource()
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:34 +0000 (12:10 -0600)]
Merge branch 'pci/enumeration-logging'
- Log device type (Root Port, Switch Port, etc) during enumeration (Bjorn
Helgaas)
- Log resource names (BAR 0, VF BAR 0, bridge window, etc) consistently
instead of a mix of names and "reg 0x10" (Puranjay Mohan, Bjorn Helgaas)
- Log bridges before devices below the bridges (Bjorn Helgaas)
* pci/enumeration-logging:
PCI: Log bridge info when first enumerating bridge
PCI: Log bridge windows conditionally
PCI: Supply bridge device, not secondary bus, to read window details
PCI: Move pci_read_bridge_windows() below individual window accessors
PCI: Use resource names in PCI log messages
PCI: Update BAR # and window messages
PCI: Log device type during enumeration
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:34 +0000 (12:10 -0600)]
Merge branch 'pci/enumeration'
- Convert pci-host-common.c platform .remove() callback to .remove_new()
returning 'void' since it's not useful to return error codes here (Uwe
Kleine-König)
- Log a message about updating AMD USB controller class code (so dwc3, not
xhci, claims it) only when we actually change it (Guilherme G. Piccoli)
- Use PCI_HEADER_TYPE_* instead of literals in x86, powerpc, SCSI lpfc
(Ilpo Järvinen)
- Clean up open-coded PCIBIOS return code mangling (Ilpo Järvinen)
- Fix 64GT/s effective data rate calculation to use 1b/1b encoding rather
than the 8b/10b or 128b/130b used by lower rates (Ilpo Järvinen)
* pci/enumeration:
PCI: Fix 64GT/s effective data rate calculation
x86/pci: Clean up open-coded PCIBIOS return code mangling
scsi: lpfc: Use PCI_HEADER_TYPE_MFD instead of literal
powerpc/fsl-pci: Use PCI_HEADER_TYPE_MASK instead of literal
x86/pci: Use PCI_HEADER_TYPE_* instead of literals
PCI: Only override AMD USB controller if required
PCI: host-generic: Convert to platform remove callback returning void
Bjorn Helgaas [Mon, 15 Jan 2024 18:10:33 +0000 (12:10 -0600)]
Merge branch 'pci/aer'
- Log AER errors as "Correctable" (not "Corrected") or "Uncorrectable" to
match spec terminology (Bjorn Helgaas)
- Decode Requester ID when no error info found instead of printing the raw
hex value (Bjorn Helgaas)
* pci/aer:
PCI/AER: Use explicit register sizes for struct members
PCI/AER: Decode Requester ID when no error info found
PCI/AER: Use 'Correctable' and 'Uncorrectable' spec terms for errors
Jim Quinlan [Mon, 13 Nov 2023 18:56:06 +0000 (13:56 -0500)]
PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device
The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be
deliberately set by the PCIe RC HW into one of three mutually exclusive
modes:
"safe" -- No CLKREQ# expected or required, refclk is always provided. This
mode should work for all devices but is not be capable of any refclk
power savings.
"no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for
CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1,
but cannot provide L1 substate (L1SS) power savings. If the downstream
device connected to the RC is L1SS capable AND the OS enables L1SS, all
PCIe traffic may abruptly halt, potentially hanging the system.
"default" -- Bidirectional CLKREQ# between the RC and downstream device.
Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock
Power Management; specifically, may not be able to meet the T_CLRon max
timing of 400ns as specified in "Dynamic Clock Control", section
3.2.5.2.2 of the PCIe Express Mini CEM 2.1 specification. This
situation is atypical and should happen only with older devices.
Previously, this driver always set the mode to "no-l1ss", as almost all
STB/CM boards operate in this mode. But now there is interest in
activating L1SS power savings from STB/CM customers, which requires "aspm"
mode. In addition, a bug was filed for RPi4 CM platform because most
devices did not work in "no-l1ss" mode.
Note that the mode is specified by the DT property "brcm,clkreq-mode". If
this property is omitted, then "default" mode is chosen.
Note: Since L1 substates are now possible, a modification was made
regarding an internal bus timeout: During long periods of the PCIe RC HW
being in an L1SS sleep state, there may be a timeout on an internal bus
access, even though there may not be any PCIe access involved. Such a
timeout will cause a subsequent CPU abort.
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217276 Link: https://lore.kernel.org/linux-pci/20231113185607.1756-3-james.quinlan@broadcom.com Tested-by: Cyril Brulebois <cyril@debamax.com> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
requires the driver to deliberately place the RC HW one of three CLKREQ#
modes. The "brcm,clkreq-mode" property allows the user to override the
default setting. If this property is omitted, the default mode shall be
"default".
Link: https://lore.kernel.org/linux-pci/20231113185607.1756-2-james.quinlan@broadcom.com Tested-by: Cyril Brulebois <cyril@debamax.com> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com>
qizhong cheng [Mon, 11 Dec 2023 09:49:23 +0000 (17:49 +0800)]
PCI: mediatek: Clear interrupt status before dispatching handler
We found a failure when using the iperf tool during WiFi performance
testing, where some MSIs were received while clearing the interrupt
status, and these MSIs cannot be serviced.
The interrupt status can be cleared even if the MSI status remains pending.
As such, given the edge-triggered interrupt type, its status should be
cleared before being dispatched to the handler of the underling device.
[kwilczynski: commit log, code comment wording] Link: https://lore.kernel.org/linux-pci/20231211094923.31967-1-jianjun.wang@mediatek.com Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622") Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: rewrap comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: <stable@vger.kernel.org>
PCI: keystone: Fix race condition when initializing PHYs
The PCI driver invokes the PHY APIs using the ks_pcie_enable_phy()
function. The PHY in this case is the Serdes. It is possible that the
PCI instance is configured for two lane operation across two different
Serdes instances, using one lane of each Serdes.
In such a configuration, if the reference clock for one Serdes is
provided by the other Serdes, it results in a race condition. After the
Serdes providing the reference clock is initialized by the PCI driver by
invoking its PHY APIs, it is not guaranteed that this Serdes remains
powered on long enough for the PHY APIs based initialization of the
dependent Serdes. In such cases, the PLL of the dependent Serdes fails
to lock due to the absence of the reference clock from the former Serdes
which has been powered off by the PM Core.
Fix this by obtaining reference to the PHYs before invoking the PHY
initialization APIs and releasing reference after the initialization is
complete.
Harshit Mogalapalli [Mon, 30 Oct 2023 07:27:57 +0000 (00:27 -0700)]
PCI: xilinx-xdma: Fix error code in xilinx_pl_dma_pcie_init_irq_domain()
Currently, if the function irq_domain_add_linear() fails to allocate
a new IRQ domain and returns NULL, we would then still return a success
from the xilinx_pl_dma_pcie_init_irq_domain() function regardless, as
the PTR_ERR(NULL) would return a value of zero. This is not a desirable
outcome.
Thus, fix the incorrect error code and return the -ENOMEM error code if
the irq_domain_add_linear() fails to allocate a new IRQ domain.
Krzysztof Wilczyński [Sat, 6 Jan 2024 12:43:28 +0000 (12:43 +0000)]
PCI: xilinx-xdma: Fix uninitialized symbols in xilinx_pl_dma_pcie_setup_irq()
The error paths that follow calls to the devm_request_irq() functions
within the xilinx_pl_dma_pcie_setup_irq() reference an uninitialized
symbol each that also so happens to be incorrect.
Thus, fix this omission and reference the correct variable when invoking
a given dev_err() function following an error.
This problem was found using smatch via the 0-DAY CI Kernel Test service:
drivers/pci/controller/pcie-xilinx-dma-pl.c:638 xilinx_pl_dma_pcie_setup_irq() error: uninitialized symbol 'irq'.
drivers/pci/controller/pcie-xilinx-dma-pl.c:645 xilinx_pl_dma_pcie_setup_irq() error: uninitialized symbol 'irq'.
Fixes: 8d786149d78c ("PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver") Link: https://lore.kernel.org/oe-kbuild/202312120248.5DblxkBp-lkp@intel.com/ Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202312120248.5DblxkBp-lkp@intel.com/ Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
The current code calculated some dbi[2] registers' offset by calling
dw_pcie_ep_get_dbi[2]_offset() in each function. To improve the code
readability, add dw_pcie_ep_{read,write}_dbi[2} and some data-width
related helpers.
Yoshihiro Shimoda [Wed, 20 Dec 2023 05:38:26 +0000 (14:38 +0900)]
PCI: dwc: Rename .func_conf_select to .get_dbi_offset in struct dw_pcie_ep_ops
Since the struct member .func_conf_select makes the intentions behind it
difficult to ascertain from its name alone, rename it to .get_dbi_offset
to make the intended usage more obvious.
Peter Robinson [Thu, 4 Jan 2024 21:39:06 +0000 (21:39 +0000)]
PCI: j721e: Make TI J721E depend on ARCH_K3
The J721E PCIe is hardware specific to TI SoC parts so add a dependency
on that so it's available for those SoC parts and for compile testing but
not necessarily everyone who enables the Cadence PCIe controller.
Bjorn Helgaas [Wed, 6 Dec 2023 22:42:31 +0000 (16:42 -0600)]
PCI/AER: Use explicit register sizes for struct members
aer_irq() reads the AER Root Error Status and Error Source Identification
(PCI_ERR_ROOT_STATUS and PCI_ERR_ROOT_ERR_SRC) registers directly into
struct aer_err_source. Both registers are 32 bits, so declare the members
explicitly as "u32" instead of "unsigned int".
Similarly, aer_get_device_error_info() reads the AER Header Log
(PCI_ERR_HEADER_LOG) registers, which are also 32 bits, into struct
aer_header_log_regs. Declare those members as "u32" as well.
Bjorn Helgaas [Wed, 6 Dec 2023 22:42:30 +0000 (16:42 -0600)]
PCI/AER: Decode Requester ID when no error info found
When a device with AER detects an error, it logs error information in its
own AER Error Status registers. It may send an Error Message to the Root
Port (RCEC in the case of an RCiEP), which logs the fact that an Error
Message was received (Root Error Status) and the Requester ID of the
message source (Error Source Identification).
aer_print_port_info() prints the Requester ID from the Root Port Error
Source in the usual Linux "bb:dd.f" format, but when find_source_device()
finds no error details in the hierarchy below the Root Port, it printed the
raw Requester ID without decoding it.
Decode the Requester ID in the usual Linux format so it matches other
messages.
Sample message changes:
- pcieport 0000:00:1c.5: AER: Correctable error received: 0000:00:1c.5
- pcieport 0000:00:1c.5: AER: can't find device of ID00e5
+ pcieport 0000:00:1c.5: AER: Correctable error message received from 0000:00:1c.5
+ pcieport 0000:00:1c.5: AER: found no error details for 0000:00:1c.5
Bjorn Helgaas [Wed, 6 Dec 2023 22:42:29 +0000 (16:42 -0600)]
PCI/AER: Use 'Correctable' and 'Uncorrectable' spec terms for errors
The PCIe spec classifies errors as either "Correctable" or "Uncorrectable".
Previously we printed these as "Corrected" or "Uncorrected". To avoid
confusion, use the same terms as the spec.
One confusing situation is when one agent detects an error, but another
agent is responsible for recovery, e.g., by re-attempting the operation.
The first agent may log a "correctable" error but it has not yet been
corrected. The recovery agent must report an uncorrectable error if it is
unable to recover. If we print the first agent's error as "Corrected", it
gives the false impression that it has already been resolved.
Ilpo Järvinen [Tue, 2 Jan 2024 17:27:00 +0000 (19:27 +0200)]
PCI: Fix 64GT/s effective data rate calculation
Unlike the lower rates, the PCIe 64GT/s Data Rate uses 1b/1b encoding, not
128b/130b (PCIe r6.1 sec 1.2, Table 1-1). Correct the PCIE_SPEED2MBS_ENC()
calculation to reflect that.
Rename the function rockchip_pcie_legacy_int_handler() of the rockchip
host driver to rockchip_pcie_intx_handler() to match the PCI_IRQ_INTX
macro name used to control this function execution, and to match the
term used in the PCI specifications.
Damien Le Moal [Wed, 22 Nov 2023 06:04:04 +0000 (15:04 +0900)]
PCI: rockchip-ep: Use INTX instead of legacy
Rename the function rockchip_pcie_ep_send_legacy_irq() of the rockchip
endpoint driver to rockchip_pcie_ep_send_intx_irq(). Uses of the term
"legacy" are also replaced with "INTX" in comments.
Damien Le Moal [Wed, 22 Nov 2023 06:04:03 +0000 (15:04 +0900)]
PCI: uniphier: Use INTX instead of legacy
In the Designware uniphier controller driver, including the endpoint
driver, change all names using "legacy" to use "intx", to match the
term used in the PCI specifications.
Rename the function rockchip_pcie_legacy_int_handler() to
rockchip_pcie_intx_handler() to match the code managing INTX interrupts
(e.g. intx_domain_ops) and the term used in the PCI specifications.
Damien Le Moal [Wed, 22 Nov 2023 06:04:00 +0000 (15:04 +0900)]
PCI: keystone: Use INTX instead of legacy
In the Keystone controller driver, change all names using "legacy" to
use "intx" instead, to match the term used in the PCI specifications.
Given that the field legacy_intc_np of struct keystone_pcie is unused,
this field is removed instead of being renamed.
Damien Le Moal [Wed, 22 Nov 2023 06:03:59 +0000 (15:03 +0900)]
PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()
Rename the function dw_pcie_ep_raise_legacy_irq() of the Designware
endpoint controller driver to dw_pcie_ep_raise_intx_irq() to match the
name of the PCI_IRQ_INTX macro.
Link: https://lore.kernel.org/r/20231122060406.14695-10-dlemoal@kernel.org Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
Damien Le Moal [Wed, 22 Nov 2023 06:03:58 +0000 (15:03 +0900)]
PCI: cadence: Use INTX instead of legacy
In the Cadence endpoint controller driver, rename the function
cdns_pcie_ep_send_legacy_irq() to cdns_pcie_ep_send_intx_irq() to match
the macro PCI_IRQ_INTX name. Related comments and messages mentioning
"legacy" are also changed to refer to "intx".
Damien Le Moal [Wed, 22 Nov 2023 06:03:55 +0000 (15:03 +0900)]
misc: pci_endpoint_test: Use INTX instead of LEGACY
In the root complex pci endpoint test function driver, change macros and
functions names using the term "legacy" to use "intx" instead to
match the term used in the PCI specifications.
Damien Le Moal [Wed, 22 Nov 2023 06:03:54 +0000 (15:03 +0900)]
PCI: endpoint: Rename LEGACY to INTX in test function driver
In the endpoint test function driver, rename IRQ_TYPE_LEGACY to
IRQ_TYPE_INTX and COMMAND_RAISE_LEGACY_IRQ to COMMAND_RAISE_INTX_IRQ
to match the term used in the PCI specifications.
Damien Le Moal [Wed, 22 Nov 2023 06:03:52 +0000 (15:03 +0900)]
PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
linux/pci.h defines the IRQ flags PCI_IRQ_INTX, PCI_IRQ_MSI and
PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
definitions provided by enum pci_epc_irq_type. This removes the need
for defining this enum type completely.
Link: https://lore.kernel.org/r/20231122060406.14695-3-dlemoal@kernel.org Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Bjorn Helgaas [Wed, 22 Nov 2023 06:03:51 +0000 (15:03 +0900)]
PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit about the type
of IRQ being referenced as well as to match the PCI specifications
terms. Redefine PCI_IRQ_LEGACY as an alias to PCI_IRQ_INTX to avoid the
need for doing the renaming tree-wide. New drivers and new code should
now prefer using PCI_IRQ_INTX instead of PCI_IRQ_LEGACY.
Link: https://lore.kernel.org/r/20231122060406.14695-2-dlemoal@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Yang Li [Mon, 30 Oct 2023 06:12:42 +0000 (14:12 +0800)]
PCI: xilinx-xdma: Remove redundant dev_err()
There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.
./drivers/pci/controller/pcie-xilinx-dma-pl.c:688:2-9: line 688 is redundant because platform_get_irq() already prints an error
./drivers/pci/controller/pcie-xilinx-dma-pl.c:702:2-9: line 702 is redundant because platform_get_irq() already prints an error
Niklas Cassel [Tue, 28 Nov 2023 13:22:30 +0000 (14:22 +0100)]
PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support
Commit 6f5e193bfb55 ("PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get
correct MSI-X table address") modified dw_pcie_ep_raise_msix_irq() to
support iATUs which require a specific alignment.
However, this support cannot have been properly tested.
The whole point is for the iATU to map an address that is aligned,
using dw_pcie_ep_map_addr(), and then let the writel() write to
ep->msi_mem + aligned_offset.
Thus, modify the address that is mapped such that it is aligned.
With this change, dw_pcie_ep_raise_msix_irq() matches the logic in
dw_pcie_ep_raise_msi_irq().
Link: https://lore.kernel.org/linux-pci/20231128132231.2221614-1-nks@flawful.org Fixes: 6f5e193bfb55 ("PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address") Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: stable@vger.kernel.org # 5.7 Cc: Kishon Vijay Abraham I <kishon@kernel.org>
Uwe Kleine-König [Mon, 4 Dec 2023 09:47:42 +0000 (10:47 +0100)]
PCI: kirin: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
In the error path emit an error message replacing the (less useful)
message by the core. Apart from the improved error message there is no
change in behaviour.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Mon, 4 Dec 2023 09:47:41 +0000 (10:47 +0100)]
PCI: keystone: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
In the error path emit an error message replacing the (less useful)
message by the core. Apart from the improved error message there is no
change in behaviour.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Mon, 4 Dec 2023 09:47:40 +0000 (10:47 +0100)]
PCI: exynos: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
In the error path emit an error message replacing the (less useful)
message by the core. Apart from the improved error message there is no
change in behaviour.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert the SiFive PCI
drivers to use the newer symbol.
Bjorn Helgaas [Wed, 22 Nov 2023 16:34:07 +0000 (10:34 -0600)]
PCI: Log bridge info when first enumerating bridge
Log bridge secondary/subordinate bus and window information at the same
time we log the bridge BARs, just after discovering the bridge and before
scanning the bridge's secondary bus. This logs the bridge and downstream
devices in a more logical order:
- pci 0000:00:01.0: [8086:1901] type 01 class 0x060400
- pci 0000:01:00.0: [10de:13b6] type 00 class 0x030200
- pci 0000:01:00.0: reg 0x10: [mem 0xec000000-0xecffffff]
- pci 0000:00:01.0: PCI bridge to [bus 01]
- pci 0000:00:01.0: bridge window [io 0xe000-0xefff]
+ pci 0000:00:01.0: [8086:1901] type 01 class 0x060400
+ pci 0000:00:01.0: PCI bridge to [bus 01]
+ pci 0000:00:01.0: bridge window [io 0xe000-0xefff]
+ pci 0000:01:00.0: [10de:13b6] type 00 class 0x030200
+ pci 0000:01:00.0: reg 0x10: [mem 0xec000000-0xecffffff]
Note that we read the windows into a temporary struct resource that is
thrown away, not into the resources in the struct pci_bus.
The windows may be adjusted after we know what downstream devices require,
and those adjustments are logged as they are made.
Bjorn Helgaas [Mon, 4 Dec 2023 23:53:32 +0000 (17:53 -0600)]
PCI: Log bridge windows conditionally
Previously pci_read_bridge_io(), pci_read_bridge_mmio(), and
pci_read_bridge_mmio_pref() unconditionally logged the bridge window
resource. A future change will call these functions earlier and more
often. Add a "log" parameter so callers can control whether to generate
the log message. No functional change intended.
Remove the assumption that the secondary (child) pci_bus already exists by
passing in the bridge device (instead of the pci_bus) and a resource
pointer when reading bridge windows. A future change can use this to log
the bridge details before we enumerate the devices below the bridge.
Move pci_read_bridge_windows() below the functions that read the I/O,
memory, and prefetchable memory windows, so pci_read_bridge_windows() can
use them in the future. No functional change intended.
Puranjay Mohan [Sat, 6 Nov 2021 11:26:05 +0000 (16:56 +0530)]
PCI: Update BAR # and window messages
The PCI log messages print the register offsets at some places and BAR
numbers at other places. There is no uniformity in this logging mechanism.
It would be better to print names than register offsets.
Add a helper function that aids in printing more meaningful information
about the BAR numbers like "VF BAR", "ROM", "bridge window", etc. This
function can be called while printing PCI log messages.
Wolfram Sang [Sun, 5 Nov 2023 09:29:08 +0000 (10:29 +0100)]
PCI: rcar-host: Add support for optional regulators
The KingFisher board has regulators for miniPCIe, so enable these
optional regulators using devm. devm will automatically disable them
when the driver releases the device. Order variables in reverse-xmas
while we are here.
[kwilczynski: update style to match rest of the code] Link: https://lore.kernel.org/linux-pci/20231105092908.3792-3-wsa+renesas@sang-engineering.com Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Rob Herring [Thu, 7 Dec 2023 16:52:50 +0000 (10:52 -0600)]
PCI: rcar-gen4: Replace of_device.h with explicit of.h include
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it was merged into the regular platform
bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h.
As a result, there's a pretty much random mix of those include files
used throughout the tree. In order to detangle these headers and replace
the implicit includes with struct declarations, users need to explicitly
include the correct includes.
Matt Ranostay [Tue, 28 Nov 2023 05:44:00 +0000 (11:14 +0530)]
PCI: j721e: Add per platform maximum lane settings
Various platforms have different maximum amount of lanes that can be
selected. Add max_lanes to struct j721e_pcie to allow for detection of this
which is needed to calculate the needed bitmask size for the possible lane
count.
Link: https://lore.kernel.org/linux-pci/20231128054402.2155183-4-s-vadapalli@ti.com Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Achal Verma <a-verma1@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Frank Li [Mon, 4 Dec 2023 16:08:29 +0000 (11:08 -0500)]
PCI: layerscape: Add suspend/resume for ls1043a
Add suspend/resume support for Layerscape LS1043a.
In the suspend path, PME_Turn_Off message is sent to the endpoint to
transition the link to L2/L3_Ready state. In this SoC, there is no way to
check if the controller has received the PME_To_Ack from the endpoint or
not. So to be on the safer side, the driver just waits for
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3
state depending on the VAUX supply.
In the resume path, the link is brought back from L2 to L0 by doing a
software reset.
Link: https://lore.kernel.org/r/20231204160829.2498703-5-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Roy Zang <Roy.Zang@nxp.com>
Frank Li [Mon, 4 Dec 2023 16:08:28 +0000 (11:08 -0500)]
PCI: layerscape(ep): Rename pf_* as pf_lut_*
'pf' and 'lut' are two different acronyms describing the same
thing, basically it is a MMIO base address plus an offset.
Rename them to avoid duplicate pf_* and lut_* naming schemes in the
driver.
Link: https://lore.kernel.org/r/20231204160829.2498703-4-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Roy Zang <Roy.Zang@nxp.com>
Frank Li [Mon, 4 Dec 2023 16:08:27 +0000 (11:08 -0500)]
PCI: layerscape: Add suspend/resume for ls1021a
Add suspend/resume support for Layerscape LS1021a.
In the suspend path, PME_Turn_Off message is sent to the endpoint to
transition the link to L2/L3_Ready state. In this SoC, there is no way to
check if the controller has received the PME_To_Ack from the endpoint or
not. So to be on the safer side, the driver just waits for
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3
state depending on the VAUX supply.
In the resume path, the link is brought back from L2 to L0 by doing a
software reset.
Link: https://lore.kernel.org/r/20231204160829.2498703-3-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Roy Zang <Roy.Zang@nxp.com>
Frank Li [Mon, 4 Dec 2023 16:08:26 +0000 (11:08 -0500)]
PCI: layerscape: Add function pointer for exit_from_l2()
Since different SoCs require different sequences for exiting L2, let's add
a separate "exit_from_l2()" callback to handle SoC specific sequences.
Change ls_pcie_exit_from_l2() return value from void to int in order
to propagate errors. Return an error if the exit_from_l2() callback
fails in the resume flow.
Link: https://lore.kernel.org/r/20231204160829.2498703-2-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Roy Zang <Roy.Zang@nxp.com>
Bjorn Helgaas [Tue, 21 Nov 2023 18:36:43 +0000 (12:36 -0600)]
x86/pci: Reorder pci_mmcfg_arch_map() definition before calls
The typical style is to define functions before calling them. Move
pci_mmcfg_arch_map() and pci_mmcfg_arch_unmap() earlier so they're defined
before they're called. No functional change intended.
Bjorn Helgaas [Tue, 21 Nov 2023 18:36:42 +0000 (12:36 -0600)]
x86/pci: Return pci_mmconfig_add() failure early
If pci_mmconfig_alloc() fails, return the failure early so it's obvious
that the failure is the exception, and the success is the normal case. No
functional change intended.
In pci_mmconfig_insert(), there's no reference to "addr" between locking
pci_mmcfg_lock and testing "addr", so it *looks* like we should move the
test before the lock.
But 07f9b61c3915 ("x86/PCI: MMCONFIG: Check earlier for MMCONFIG region at
address zero") did that, which broke things by returning -EINVAL when
"addr" is zero instead of -EEXIST.
So 07f9b61c3915 was reverted by 67d470e0e171 ("Revert "x86/PCI: MMCONFIG:
Check earlier for MMCONFIG region at address zero"").
Add a comment about this issue to prevent it from happening again.
Bjorn Helgaas [Tue, 21 Nov 2023 18:36:40 +0000 (12:36 -0600)]
x86/pci: Rename pci_mmcfg_check_reserved() to pci_mmcfg_reserved()
"pci_mmcfg_check_reserved()" doesn't give a hint about what the boolean
return value means. Rename it to pci_mmcfg_reserved() so testing
"if (pci_mmcfg_reserved())" makes sense.
Update callers to treat the return value as boolean instead of comparing
with 0.
Bjorn Helgaas [Tue, 21 Nov 2023 18:36:39 +0000 (12:36 -0600)]
x86/pci: Rename acpi_mcfg_check_entry() to acpi_mcfg_valid_entry()
"acpi_mcfg_check_entry()" doesn't give a hint about what the return value
means. Rename it to "acpi_mcfg_valid_entry()", convert the return value to
bool, and update the return values and callers to match so testing
"if (acpi_mcfg_valid_entry())" makes sense.
Bjorn Helgaas [Tue, 21 Nov 2023 18:36:36 +0000 (12:36 -0600)]
x86/pci: Reword ECAM EfiMemoryMappedIO logging to avoid 'reserved'
fd3a8cff4d4a ("x86/pci: Treat EfiMemoryMappedIO as reservation of ECAM
space") added the concept of using the EFI memory map to help decide
whether ECAM space mentioned in the MCFG table is valid.
Unfortunately it described that EfiMemoryMappedIO space as "reserved", but
it is actually not *reserved* by the EFI memory map. EfiMemoryMappedIO
only means the firmware requested that the OS map this space for use by
firmware runtime services.
Change the dmesg logging to describe it as simply "EfiMemoryMappedIO", not
as "reserved as EfiMemoryMappedIO". A previous commit actually *does*
reserve the space if ACPI PNP0C01/02 devices haven't done so:
- PCI: ECAM at [mem 0xe0000000-0xefffffff] reserved as EfiMemoryMappedIO
+ PCI: ECAM at [mem 0xe0000000-0xefffffff] is EfiMemoryMappedIO; assuming valid
PCI: ECAM [mem 0xe0000000-0xefffffff] reserved to work around lack of ACPI motherboard _CRS
Bjorn Helgaas [Tue, 21 Nov 2023 18:36:35 +0000 (12:36 -0600)]
x86/pci: Reserve ECAM if BIOS didn't include it in PNP0C02 _CRS
Tomasz, Sebastian, and some Proxmox users reported problems initializing
ixgbe NICs.
I think the problem is that ECAM space described in the ACPI MCFG table is
not reserved via a PNP0C02 _CRS method as required by the PCI Firmware spec
(r3.3, sec 4.1.2), but it *is* included in the PNP0A03 host bridge _CRS as
part of the MMIO aperture.
If we allocate space for a PCI BAR, we're likely to allocate it from that
ECAM space, which obviously cannot work.
This could happen for any device, but in the ixgbe case it happens because
it's an SR-IOV device and the BIOS didn't allocate space for the VF BARs,
so Linux reallocated the bridge window leading to ixgbe and put it on top
of the ECAM space. From Tomasz' system:
PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0x80000000-0x8fffffff] (base 0x80000000)
PCI: MMCONFIG at [mem 0x80000000-0x8fffffff] not reserved in ACPI motherboard resources
pci_bus 0000:00: root bus resource [mem 0x80000000-0xfbffffff window]
pci 0000:00:01.1: PCI bridge to [bus 02-03]
pci 0000:00:01.1: bridge window [mem 0xfb900000-0xfbbfffff]
pci 0000:02:00.0: [8086:10fb] type 00 class 0x020000 # ixgbe
pci 0000:02:00.0: reg 0x10: [mem 0xfba80000-0xfbafffff 64bit]
pci 0000:02:00.0: VF(n) BAR0 space: [mem 0x00000000-0x000fffff 64bit] (contains BAR0 for 64 VFs)
pci 0000:02:00.0: BAR 7: no space for [mem size 0x00100000 64bit] # VF BAR 0
pci_bus 0000:00: No. 2 try to assign unassigned res
pci 0000:00:01.1: resource 14 [mem 0xfb900000-0xfbbfffff] released
pci 0000:00:01.1: BAR 14: assigned [mem 0x80000000-0x806fffff]
pci 0000:02:00.0: BAR 0: assigned [mem 0x80000000-0x8007ffff 64bit]
pci 0000:02:00.0: BAR 7: assigned [mem 0x80204000-0x80303fff 64bit] # VF BAR 0
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