Stephen Boyd [Wed, 27 Nov 2019 16:15:13 +0000 (08:15 -0800)]
Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' into clk-next
- Support CGU in Ingenix X1000
- Support Bitmain BM1880 clks
* clk-ingenic:
clk: ingenic: Allow drivers to be built with COMPILE_TEST
clk: Ingenic: Add CGU driver for X1000.
dt-bindings: clock: Add X1000 bindings.
* clk-init-leak:
clk: mark clk_disable_unused() as __init
clk: Fix memory leak in clk_unregister()
* clk-ux500:
MAINTAINERS: Update section for Ux500 clock drivers
* clk-bitmain:
MAINTAINERS: Add entry for BM1880 SoC clock driver
clk: Add common clock driver for BM1880 SoC
dt-bindings: clock: Add devicetree binding for BM1880 SoC
clk: Add clk_hw_unregister_composite helper function definition
clk: Zero init clk_init_data in helpers
Stephen Boyd [Wed, 27 Nov 2019 16:15:00 +0000 (08:15 -0800)]
Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and 'clk-pxa' into clk-next
- Make gpio gate clks propagate rate setting up to parent
* clk-gpio-flags:
clk: clk-gpio: propagate rate change to parent
* clk-tegra: (23 commits)
clk: tegra: Use match_string() helper to simplify the code
clk: tegra: Fix build error without CONFIG_PM_SLEEP
clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
clk: tegra: Optimize PLLX restore on Tegra20/30
clk: tegra: Add suspend and resume support on Tegra210
clk: tegra: Share clk and rst register defines with Tegra clock driver
clk: tegra: Use fence_udelay() during PLLU init
clk: tegra: clk-dfll: Add suspend and resume support
clk: tegra: clk-super: Add restore-context support
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
clk: tegra: periph: Add restore_context support
clk: tegra: Support for OSC context save and restore
clk: tegra: pll: Save and restore pll context
clk: tegra: pllout: Save and restore pllout context
clk: tegra: divider: Save and restore divider rate
clk: tegra: Reimplement SOR clocks on Tegra210
clk: tegra: Reimplement SOR clock on Tegra124
clk: tegra: Rename sor0_lvds to sor0_out
clk: tegra: Move SOR0 implementation to Tegra124
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
...
* clk-rockchip:
clk: rockchip: protect the pclk_usb_grf as critical on px30
clk: rockchip: add video-related niu clocks as critical on px30
clk: rockchip: move px30 critical clocks to correct clock controller
clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc
clk: rockchip: make clk_half_divider_ops static
* clk-sprd:
clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()
* clk-pxa:
clk: pxa: fix one of the pxa RTC clocks
Stephen Boyd [Wed, 27 Nov 2019 16:14:38 +0000 (08:14 -0800)]
Merge branches 'clk-ti', 'clk-allwinner', 'clk-qcom', 'clk-sa' and 'clk-aspeed' into clk-next
- Qualcomm MSM8998 GPU clk controllers
- Qualcomm SC7180 GCC and RPMH clk controllers
- Qualcomm QCS404 Q6SSTOP clk controllers
- Use struct_size() some more in various clk drivers
* clk-ti:
clk/ti/adpll: allocate room for terminating null
ARM: dts: omap3: fix DPLL4 M4 divider max value
clk: ti: divider: convert to use min,max,mask instead of width
clk: ti: divider: cleanup ti_clk_parse_divider_data API
clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table
clk: ti: am43xx: drop idlest polling from gfx clock
clk: ti: am33xx: drop idlest polling from gfx clock
clk: ti: am33xx: drop idlest polling from pruss clkctrl clock
clk: ti: am43xx: drop idlest polling from pruss clkctrl clock
clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks
clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocks
clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocks
clk: ti: omap5: add IVA subsystem clkctrl data
dt-bindings: clk: add omap5 iva clkctrl definitions
clk: ti: clkctrl: add new exported API for checking standby info
clk: ti: clkctrl: convert to use bit helper macros instead of bitops
clk: ti: clkctrl: fix setting up clkctrl clocks
* clk-allwinner:
clk: sunxi-ng: h3: Export MBUS clock
clk: sunxi-ng: h6: Allow GPU to change parent rate
clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
* clk-qcom:
clk: qcom: rpmh: Reuse sdm845 clks for sm8150
clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
clk: qcom: Allow constant ratio freq tables for rcg
clk: qcom: smd: Add missing pnoc clock
clk: qcom: Enumerate clocks and reset needed to boot the 8998 modem
clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180
dt-bindings: clock: Introduce RPMHCC bindings for SC7180
dt-bindings: clock: Add YAML schemas for the QCOM RPMHCC clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SC7180
dt-bindings: clock: Add sc7180 GCC clock binding
dt-bindings: clock: Add YAML schemas for the QCOM GCC clock bindings
clk: qcom: common: Return NULL from clk_hw OF provider
clk: qcom: rcg: update the DFS macro for RCG
clk: qcom: remove unneeded semicolon
clk: qcom: Add Q6SSTOP clock controller for QCS404
dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings
* clk-sa:
drivers/clk: convert VL struct to struct_size
* clk-aspeed:
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
clk: ast2600: Add RMII RCLK gates for all four MACs
dt-bindings: clock: Add AST2600 RMII RCLK gate definitions
dt-bindings: clock: Add AST2500 RMII RCLK definitions
Stephen Boyd [Wed, 27 Nov 2019 16:14:17 +0000 (08:14 -0800)]
Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'clk-imx' into clk-next
* clk-hisi:
clk: hi6220: use CLK_OF_DECLARE_DRIVER
* clk-amlogic:
clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
clk: meson: axg_audio: add sm1 support
clk: meson: axg-audio: provide clk top signal name
clk: meson: axg-audio: prepare sm1 addition
clk: meson: axg-audio: fix regmap last register
clk: meson: axg-audio: remove useless defines
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
dt-bindings: clk: axg-audio: add sm1 bindings
clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
clk: meson: g12a: fix cpu clock rate setting
clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
* clk-samsung:
clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
clk: samsung: exynos5420: Add VPLL rate table
clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
clk: samsung: exynos5433: Fix error paths
* clk-renesas: (23 commits)
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
clk: renesas: r8a77965: Remove superfluous semicolon
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
dt-bindings: power: Add r8a77961 SYSC power domain definitions
clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
clk: renesas: r8a774b1: Add TMU clock
clk: renesas: cpg-mssr: Add r8a774b1 support
dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
clk: renesas: rcar-gen3: Improve arithmetic divisions
clk: renesas: rcar-gen2: Improve arithmetic divisions
clk: renesas: Remove R-Car Gen2 legacy DT clock support
...
* clk-imx:
clk: imx: imx8mq: fix sys3_pll_out_sels
clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code
clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code
clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code
clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code
clk: imx7ulp: Correct DDR clock mux options
clk: imx7ulp: Correct system clock source option #7
clk: imx: imx8mq: mark sys1/2_pll as fixed clock
clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
clk: imx8mn: Define gates for pll1/2 fixed dividers
clk: imx8mm: Define gates for pll1/2 fixed dividers
clk: imx8mq: Define gates for pll1/2 fixed dividers
clk: imx: clk-pll14xx: Make two variables static
clk: imx8mq: Add VIDEO2_PLL clock
clk: imx8mn: Use common 1443X/1416X PLL clock structure
clk: imx8mm: Move 1443X/1416X PLL clock structure to common place
clk: imx: pll14xx: Fix quick switch of S/K parameter
Stephen Boyd [Wed, 27 Nov 2019 16:13:24 +0000 (08:13 -0800)]
Merge branches 'clk-rohm', 'clk-hisilicon', 'clk-marvell', 'clk-unused' and 'clk-devm-ioremap-resource' into clk-next
- Prepare Armada 3700 for suspend to RAM by moving suspend/resume priority for PCIe
- Drop unused variables, enums, etc. in various clk drivers
- Convert various drivers to use devm_platform_ioremap_resource()
* clk-rohm:
clk: bd718x7: Add MODULE_ALIAS()
* clk-hisilicon:
clk: hisilicon: fix sparse warnings in clk-hi3660.c
clk: hisilicon: fix sparse warnings in clk-hi3670.c
* clk-marvell:
dt-bindings: clk: armada3700: document the PCIe clock
dt-bindings: clk: armada3700: fix typo in SoC name
clk: mvebu: armada-37xx-periph: change suspend/resume time
clk: mvebu: armada-37xx-periph: add PCIe gated clock
* clk-devm-ioremap-resource:
clk: sprd: Change to use devm_platform_ioremap_resource()
clk: s3c2410: use devm_platform_ioremap_resource() to simplify code
clk: axs10x: use devm_platform_ioremap_resource() to simplify code
clk: mediatek: mt6797: use devm_platform_ioremap_resource() to simplify code
clk: mediatek: mt7629: use devm_platform_ioremap_resource() to simplify code
clk: mediatek: mt7622: use devm_platform_ioremap_resource() to simplify code
clk: mediatek: mt8183: use devm_platform_ioremap_resource() to simplify code
clk: mediatek: mt6779: use devm_platform_ioremap_resource() to simplify code
clk: mediatek: mt2712: use devm_platform_ioremap_resource() to simplify code
clk: davinci: use devm_platform_ioremap_resource() to simplify code
clk: hisilicon: use devm_platform_ioremap_resource() to simplify code
clk: bcm2835: use devm_platform_ioremap_resource() to simplify code
Manivannan Sadhasivam [Fri, 15 Nov 2019 16:29:00 +0000 (21:59 +0530)]
clk: Add common clock driver for BM1880 SoC
Add common clock driver for Bitmain BM1880 SoC. The clock controller on
BM1880 has supplies clocks to all peripherals in the form of gate clocks
and composite clocks (fixed factor + gate).
Manivannan Sadhasivam [Fri, 15 Nov 2019 16:28:55 +0000 (21:58 +0530)]
clk: Zero init clk_init_data in helpers
The clk_init_data struct needs to be initialized to zero for the new
parent_map implementation to work correctly. Otherwise, the member which
is available first will get processed.
Stephen Boyd [Thu, 14 Nov 2019 00:19:25 +0000 (16:19 -0800)]
clk: ingenic: Allow drivers to be built with COMPILE_TEST
We don't need the MIPS architecture or even a MIPS compiler to compile
test these drivers. Let's add a COMPILE_TEST possibility on the
menuconfig here so that we can build these drivers on more
configurations.
Ulf Hansson [Thu, 21 Nov 2019 10:07:26 +0000 (11:07 +0100)]
MAINTAINERS: Update section for Ux500 clock drivers
There's no longer any need host a tree solely to serve changes for the
Ux500 clock driver, thus drop this from the corresponding section and use
the common clk tree instead.
Moreover, let's also add the generic linux-clk mailing list and rename the
section header.
Rasmus Villemoes [Fri, 4 Oct 2019 09:48:25 +0000 (11:48 +0200)]
clk: mark clk_disable_unused() as __init
clk_disable_unused is only called once, as a late_initcall, so reclaim
a bit of memory by marking it (and the functions and data it is the
sole user of) as __init/__initdata. This moves ~1900 bytes from .text
to .init.text for a imx_v6_v7_defconfig.
Kishon Vijay Abraham I [Tue, 22 Oct 2019 07:11:53 +0000 (12:41 +0530)]
clk: Fix memory leak in clk_unregister()
Memory allocated in alloc_clk() for 'struct clk' and
'const char *con_id' while invoking clk_register() is never freed
in clk_unregister(), resulting in kmemleak showing the following
backtrace.
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lkml.kernel.org/r/20191022071153.21118-1-kishon@ti.com Fixes: 1df4046a93e0 ("clk: Combine __clk_get() and __clk_create_clk()") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
YueHaibing [Mon, 11 Nov 2019 14:04:20 +0000 (22:04 +0800)]
clk: armada-xp: remove unused code
drivers/clk/mvebu/armada-xp.c:171:38: warning:
mv98dx3236_coreclks defined but not used [-Wunused-const-variable=]
drivers/clk/mvebu/armada-xp.c:213:41: warning:
mv98dx3236_gating_desc defined but not used [-Wunused-const-variable=]
They are not used since commit 337072604224 ("clk: mvebu:
Expand mv98dx3236-core-clock support").
Stephen Boyd [Wed, 13 Nov 2019 19:27:45 +0000 (11:27 -0800)]
Merge tag 'v5.5-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
Adding a missing static declaration for clk_half_divider_ops
and a number of improvements for the px30 clock tree.
* tag 'v5.5-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: protect the pclk_usb_grf as critical on px30
clk: rockchip: add video-related niu clocks as critical on px30
clk: rockchip: move px30 critical clocks to correct clock controller
clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc
clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc
clk: rockchip: make clk_half_divider_ops static
Stephen Boyd [Wed, 13 Nov 2019 19:18:57 +0000 (11:18 -0800)]
Merge tag 'tegra-for-5.5-clk-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull Tegra clk driver updates from Thierry Reding:
The bulk of these changes implement suspend/resume support for Tegra210.
In addition, some of the SOR clocks on earlier Tegra generations are
reimplemented to more closely match the implementation on later chips,
which in turn makes it possible to handle HDMI and DP support in a more
unified way.
* tag 'tegra-for-5.5-clk-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (21 commits)
clk: tegra: Fix build error without CONFIG_PM_SLEEP
clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
clk: tegra: Optimize PLLX restore on Tegra20/30
clk: tegra: Add suspend and resume support on Tegra210
clk: tegra: Share clk and rst register defines with Tegra clock driver
clk: tegra: Use fence_udelay() during PLLU init
clk: tegra: clk-dfll: Add suspend and resume support
clk: tegra: clk-super: Add restore-context support
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
clk: tegra: periph: Add restore_context support
clk: tegra: Support for OSC context save and restore
clk: tegra: pll: Save and restore pll context
clk: tegra: pllout: Save and restore pllout context
clk: tegra: divider: Save and restore divider rate
clk: tegra: Reimplement SOR clocks on Tegra210
clk: tegra: Reimplement SOR clock on Tegra124
clk: tegra: Rename sor0_lvds to sor0_out
clk: tegra: Move SOR0 implementation to Tegra124
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
clk: tegra: Add Tegra20/30 EMC clock implementation
...
Stephen Boyd [Wed, 13 Nov 2019 19:16:58 +0000 (11:16 -0800)]
Merge tag 'tegra-for-5.5-clk-core-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-hw-parent-index
Pull clk framework change from Thierry Reding:
Contains a single core API addition that allows clock providers to query
the parent index for a given struct clk_hw. This is used to implement
suspend/resume support on Tegra SoCs.
* tag 'tegra-for-5.5-clk-core-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: Add API to get index of the clock parent
YueHaibing [Wed, 30 Oct 2019 12:56:50 +0000 (20:56 +0800)]
clk: tegra: Fix build error without CONFIG_PM_SLEEP
If CONFIG_PM_SLEEP is n, build fails:
drivers/clk/tegra/clk-tegra210.c:3426:13: error:
tegra210_clk_suspend undeclared here (not in a function); did you mean tegra_clk_ndspeed?
.suspend = tegra210_clk_suspend,
^~~~~~~~~~~~~~~~~~~~
tegra_clk_ndspeed
drivers/clk/tegra/clk-tegra210.c:3427:12: error:
tegra210_clk_resume undeclared here (not in a function); did you mean tegra210_clk_suspend?
.resume = tegra210_clk_resume,
Use ifdef to guard this.
Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 27d10d548c04 ("clk: tegra: Add suspend and resume support on Tegra210") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Tue, 15 Oct 2019 17:00:06 +0000 (20:00 +0300)]
clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
The new CPUIDLE driver uses the Tegra's CLK API and that driver won't
strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in
order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n.
There is no need to re-configure PLLX if its configuration in unchanged
on return from suspend / cpuidle, this saves 300us if PLLX is already
enabled (common case for cpuidle).
Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Fri, 16 Aug 2019 19:42:00 +0000 (12:42 -0700)]
clk: tegra: Add suspend and resume support on Tegra210
All the CAR controller settings are lost on suspend when core power goes
off. This implement saving and restoring context for all PLLs and clocks
during system suspend and resume to have the clocks back to same state
for normal operation.
Clock driver suspend and resume are registered as syscore_ops as clocks
restore need to happen before the other drivers resume to have all their
clocks back to the same state as before suspend.
Sowjanya Komatineni [Fri, 16 Aug 2019 19:41:58 +0000 (12:41 -0700)]
clk: tegra: Use fence_udelay() during PLLU init
This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.
Sowjanya Komatineni [Fri, 16 Aug 2019 19:41:54 +0000 (12:41 -0700)]
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
This patch has a fix to enable PLLP branches to CPU before changing
the CPU cluster clock source to PLLP for Gen5 Super clock and
disables PLLP branches to CPU when not in use.
During system suspend entry and exit, CPU source will be switched
to PLLP and this needs PLLP branches to be enabled to CPU prior to
the switch.
On system resume, warmboot code enables PLLP branches to CPU and
powers up the CPU with PLLP clock source.
Sowjanya Komatineni [Fri, 16 Aug 2019 19:41:51 +0000 (12:41 -0700)]
clk: tegra: Support for OSC context save and restore
This patch adds support for saving OSC clock frequency and the
drive-strength during OSC clock init and creates an API to restore
OSC control register value from the saved context.
This API is invoked by Tegra210 clock driver during system resume
to restore the OSC clock settings.
Thierry Reding [Mon, 24 Jun 2019 15:06:13 +0000 (17:06 +0200)]
clk: tegra: Reimplement SOR clocks on Tegra210
In order to allow the display driver to deal uniformly with all SOR
generations, implement the SOR clocks in a way that is compatible with
Tegra186 and later.
Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to allow the display driver to deal uniformly with all SOR
generations, implement the SOR clocks in a way that is compatible with
Tegra186 and later.
Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 28 Jun 2019 09:01:16 +0000 (11:01 +0200)]
clk: tegra: Move SOR0 implementation to Tegra124
The SOR0 clock on Tegra210 is very different from the SOR0 clock found
on Tegra124. Move the Tegra124 implementation to the Tegra124 driver so
that a custom implementation can be provided on Tegra210 without
clashing with the existing clock.
Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 28 Jun 2019 09:06:35 +0000 (11:06 +0200)]
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Later SoC generations implement this clock as SOR1_OUT. For consistency,
the Tegra210 implementation was adapted to match the same name in commit 4d1dc4018573 ("dt-bindings: clock: tegra: Add sor1_out clock").
Clean up the remaining pieces by adopting the new name for the internal
identifiers and remove the old alias. Note that since both SOR1_SRC and
SOR1_OUT were referring to the same device tree clock ID, this does not
break device tree ABI.
Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
the generic clock implementation because only the Memory Controller driver
is aware of what clock rates are actually available for a particular
device. EMC drivers will have to register a Tegra-specific CLK-API
callback which will perform rounding of a requested rate. EMC clock users
won't be able to request EMC clock by getting -EPROBE_DEFER until EMC
driver is probed and the callback is set up.
The functionality is somewhat similar to the clk-emc.c which serves
Tegra124+ SoCs. The later HW generations support more parent clock sources
and the HW configuration / integration with the EMC drivers differs a tad
from the older gens, hence it's not really worth to try to squash
everything into a single source file.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Fri, 16 Aug 2019 19:41:52 +0000 (12:41 -0700)]
clk: Add API to get index of the clock parent
This patch adds a new clk_hw_get_parent_index() function that can be
used to retrieve the index of a given clock's parent. This can be useful
for restoring a clock on system resume.
Michael Hennerich [Fri, 8 Nov 2019 07:17:18 +0000 (09:17 +0200)]
clk: clk-gpio: propagate rate change to parent
For an external clock source, which is gated via a GPIO, the
rate change should typically be propagated to the parent clock.
The situation where we are requiring this propagation, is when an
external clock is connected to override an internal clock (which typically
has a fixed rate). The external clock can have a different rate than the
internal one, and may also be variable, thus requiring the rate
propagation.
This rate change wasn't propagated until now, and it's unclear about cases
where this shouldn't be propagated. Thus, it's unclear whether this is
fixing a bug, or extending the current driver behavior. Also, it's unsure
about whether this may break any existing setups; in the case that it does,
a device-tree property may be added to disable this flag.
Stephen Boyd [Thu, 7 Nov 2019 21:40:18 +0000 (13:40 -0800)]
clk: qcom: rpmh: Reuse sdm845 clks for sm8150
The SM8150 list of clks is almost the same as the list for SDM845,
except there isn't an IPA clk. Just point to the SDM845 clks from the
SM8150 list for now so we can reduce the amount of struct bloat in this
driver.
Stephen Kitt [Fri, 27 Sep 2019 18:51:10 +0000 (20:51 +0200)]
drivers/clk: convert VL struct to struct_size
There are a few manually-calculated variable-length struct allocations
left, this converts them to use struct_size. Found with the following
git grep command
git grep -A1 'kzalloc.*sizeof[^_].*+'
Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
[sboyd@kernel.org: Add grep command] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jeffrey Hugo [Thu, 31 Oct 2019 18:57:15 +0000 (11:57 -0700)]
clk: qcom: Allow constant ratio freq tables for rcg
Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just
some constant ratio from the input across the entire frequency range. It
would be great if we could specify the frequency table as a single entry
constant ratio instead of a long list, ie:
{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
{ }
So, lets support that.
We need to fix a corner case in qcom_find_freq() where if the freq table
is non-null, but has no frequencies, we end up returning an "entry" before
the table array, which is bad. Then, we need ignore the freq from the
table, and instead base everything on the requested freq.
Jeffrey Hugo [Thu, 7 Nov 2019 19:06:15 +0000 (11:06 -0800)]
clk: qcom: smd: Add missing pnoc clock
When MSM8998 support was added, and analysis was done to determine what
clocks would be consumed. That analysis had a flaw, which caused the
pnoc to be skipped. The pnoc clock needs to be on to access the uart
for the console. The clock is on from boot, but has no consumer votes
in the RPM. When we attempt to boot the modem, it causes the RPM to
turn off pnoc, which kills our access to the console and causes CPU hangs.
We need pnoc to be defined, so that clk_smd_rpm_handoff() will put in
an implicit vote for linux and prevent issues when booting modem.
Hopefully pnoc can be consumed by the interconnect framework in future
so that Linux can rely on explicit votes.
Jeffrey Hugo [Thu, 7 Nov 2019 19:21:36 +0000 (11:21 -0800)]
clk: qcom: Enumerate clocks and reset needed to boot the 8998 modem
We need to control five additional clocks and a reset inorder to boot the
modem on msm8998. If we can boot the modem, we have a place to run the
wlan firmware and get wifi up and running.
Taniya Das [Mon, 14 Oct 2019 10:23:08 +0000 (15:53 +0530)]
clk: qcom: Add Global Clock controller (GCC) driver for SC7180
Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Taniya Das [Mon, 14 Oct 2019 10:23:07 +0000 (15:53 +0530)]
dt-bindings: clock: Add sc7180 GCC clock binding
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-5-tdas@codeaurora.org Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Reword subject to make sc7180 specific, sort
compatible] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Mon, 14 Oct 2019 10:23:04 +0000 (15:53 +0530)]
clk: qcom: rcg: update the DFS macro for RCG
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.
Govind Singh [Fri, 11 Oct 2019 13:29:28 +0000 (18:59 +0530)]
clk: qcom: Add Q6SSTOP clock controller for QCS404
Add support for the Q6SSTOP clock control used on qcs404
based devices. This would allow wcss remoteproc driver to
control the required WCSS Q6SSTOP clock/reset controls to
bring the subsystem out of reset and shutdown the WCSS Q6DSP.
Stephen Boyd [Wed, 6 Nov 2019 22:26:56 +0000 (14:26 -0800)]
Merge tag 'ti-clk-for-5.5-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti
Pull TI clk driver updates from Tero Kristo:
As the clock and reset handling is tightly coupled on the hardware level
on OMAP SoCs, we must ensure the events are sequenced properly. This
series makes sure that the clock side is behaving properly, and the
sequencing of the events is left for the bus driver (ti-sysc.)
The series also includes revamp of the TI divider clock implementation
to handle max divider values properly in cases where the max value is
not limited by the bitfield of the IO register but instead limited to
some arbitrary value. Previously this resulted in too high divider
values to be used in some cases causing HW malfunction.
Additionally, a couple of smaller changes needed by remoteproc support
are added; checking of the standby status and some missing clkctrl data
for omap5/dra7.
* tag 'ti-clk-for-5.5-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
ARM: dts: omap3: fix DPLL4 M4 divider max value
clk: ti: divider: convert to use min,max,mask instead of width
clk: ti: divider: cleanup ti_clk_parse_divider_data API
clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table
clk: ti: am43xx: drop idlest polling from gfx clock
clk: ti: am33xx: drop idlest polling from gfx clock
clk: ti: am33xx: drop idlest polling from pruss clkctrl clock
clk: ti: am43xx: drop idlest polling from pruss clkctrl clock
clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks
clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocks
clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocks
clk: ti: omap5: add IVA subsystem clkctrl data
dt-bindings: clk: add omap5 iva clkctrl definitions
clk: ti: clkctrl: add new exported API for checking standby info
clk: ti: clkctrl: convert to use bit helper macros instead of bitops
clk: ti: clkctrl: fix setting up clkctrl clocks
Stephen Boyd [Wed, 6 Nov 2019 21:04:28 +0000 (13:04 -0800)]
Merge tag 'imx-clk-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk updates from Shawn Guo:
- Make 1443X/1416X PLL clock structure common for reusing among i.MX8 SoCs
- A couple of imx7ulp clock multiplexer option corrections.
- Drop IMX7ULP_CLK_MIPI_PLL clock, as it's a MIPI DSI local clock and
shouldn't be used externally
- Add VIDEO2_PLL clock for imx8mq which is needed by DCSS when high
resolutions are used
- Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs
- Register SYS_PLL1 and SYS_PLL2 as fixed clock rather than pll14xx
type of clock
- Use imx_obtain_fixed_clk_hw() to simplify i.MX6/7/8 clock driver code
a little bit
- One cosmetic change on clk-pll14xx code to make variables static
* tag 'imx-clk-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: imx8mq: fix sys3_pll_out_sels
clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code
clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code
clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code
clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code
clk: imx7ulp: Correct DDR clock mux options
clk: imx7ulp: Correct system clock source option #7
clk: imx: imx8mq: mark sys1/2_pll as fixed clock
clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
clk: imx8mn: Define gates for pll1/2 fixed dividers
clk: imx8mm: Define gates for pll1/2 fixed dividers
clk: imx8mq: Define gates for pll1/2 fixed dividers
clk: imx: clk-pll14xx: Make two variables static
clk: imx8mq: Add VIDEO2_PLL clock
clk: imx8mn: Use common 1443X/1416X PLL clock structure
clk: imx8mm: Move 1443X/1416X PLL clock structure to common place
clk: imx: pll14xx: Fix quick switch of S/K parameter
Stephen Boyd [Wed, 6 Nov 2019 19:32:03 +0000 (11:32 -0800)]
Merge tag 'clk-renesas-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Switch some clocks on R-Car Gen2/3 to .determine_rate()
- Add support for the new R-Car M3-W+ (r8a77961) SoC
- Add support for the new RZ/G2N (r8a774b1) SoC
- Remove R-Car Gen2 legacy DT clock support
- Improve arithmetic divisions on R-Car Gen2 and Gen3
- Improve R-Car Gen3 SD clock handling
* tag 'clk-renesas-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (23 commits)
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
clk: renesas: r8a77965: Remove superfluous semicolon
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
dt-bindings: power: Add r8a77961 SYSC power domain definitions
clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
clk: renesas: r8a774b1: Add TMU clock
clk: renesas: cpg-mssr: Add r8a774b1 support
dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
clk: renesas: rcar-gen3: Improve arithmetic divisions
clk: renesas: rcar-gen2: Improve arithmetic divisions
clk: renesas: Remove R-Car Gen2 legacy DT clock support
...
Stephen Boyd [Wed, 6 Nov 2019 19:28:50 +0000 (11:28 -0800)]
Merge tag 'clk-v5.5-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Addition of rate table for the VPLL and GPU related clock
tree definition update to allow the GPU driver for setting
the GPU's clock without requiring detailed knowledge of
clock topology on each exynos542x SoC
- Fix for potential CPU performance degradation after system
suspend/resume cycle on exynos542x SoCs
* tag 'clk-v5.5-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
clk: samsung: exynos5420: Add VPLL rate table
clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
clk: samsung: exynos5433: Fix error paths
Stephen Boyd [Wed, 6 Nov 2019 19:20:14 +0000 (11:20 -0800)]
Merge tag 'clk-meson-v5.5-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk updates from Jerome Brunet:
- Add sm1 support in the Amlogic audio clock controller
* tag 'clk-meson-v5.5-1' of https://github.com/BayLibre/clk-meson:
clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
clk: meson: axg_audio: add sm1 support
clk: meson: axg-audio: provide clk top signal name
clk: meson: axg-audio: prepare sm1 addition
clk: meson: axg-audio: fix regmap last register
clk: meson: axg-audio: remove useless defines
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
dt-bindings: clk: axg-audio: add sm1 bindings
clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
clk: meson: g12a: fix cpu clock rate setting
clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
clk: rockchip: add video-related niu clocks as critical on px30
Video-In and -Out interconnect clocks need to stay on all the
time for the peripheral to work and we do not model the actual
interconnect at this point. So mark them as critical for now.
Peng Fan [Mon, 28 Oct 2019 03:08:34 +0000 (03:08 +0000)]
clk: imx: imx8mq: fix sys3_pll_out_sels
It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.
According to the current imx_clk_sccg_pll design, it uses both
bypass1/2, however set bypass2 as 1 is not correct, because it will
make sys[x]_pll_out use wrong parent and might access wrong registers.
So correct bypass2 to 0 and fix sys3_pll_out_sels.
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:41 +0000 (14:29 +0200)]
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
Add support for the R-Car M3-W+ (R8A77961) SoC to the Renesas Clock
Pulse Generator / Module Standby and Software Reset driver.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver. R-Car M3-W+ lacks a few modules, so their
clocks must be nullified.
Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:40 +0000 (14:29 +0200)]
clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.
Extend the dependency of CONFIG_CLK_R8A77960 from CONFIG_ARCH_R8A7796 to
CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the
SoC configuration symbol.
As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new
CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files
use the unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.
Hence remove the old R-Car Gen2 DT bindings describing a hierarchical
representation of the various CPG and MSTP clocks.
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.
The AST2600 has an explicit gate for the RMII RCLK for each of the four
MACs.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
The AST2500 has an explicit gate for the RMII RCLK for each of the two
MACs.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
Tero Kristo [Wed, 2 Oct 2019 12:06:11 +0000 (15:06 +0300)]
ARM: dts: omap3: fix DPLL4 M4 divider max value
The maximum divider value for DPLL4 M4 divider appears wrong. For most
OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe
only valid for omap36xx. To avoid any overflows in trying to write this
register, set the max to 16 for all omap3 family, except omap36xx. For
omap36xx the maximum is set to 31, as it appears value 32 is not working
properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 2 Oct 2019 12:06:10 +0000 (15:06 +0300)]
clk: ti: divider: convert to use min,max,mask instead of width
The existing width field used to check divider validity does not provide
enough protection against bad values. For example, if max divider value
is 4, the smallest all-1 bitmask that can hold this value is 7, which
allows values higher than 4 to be used. This typically causes
unpredictable results with hardware. So far this issue hasn't been
noticed as most of the dividers actually have maximum values which fit
the whole bitfield, but there are certain clocks for which this is a
problem, like dpll4_m4 divider on omap3 devices.
Thus, convert the whole validity logic to use min,max and mask values
for determining if a specific divider is valid or not. This prevents
the odd cases where bad value would otherwise be written to a divider
config register.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com>
Tero Kristo [Wed, 2 Oct 2019 12:06:09 +0000 (15:06 +0300)]
clk: ti: divider: cleanup ti_clk_parse_divider_data API
Cleanup the ti_clk_parse_divider_data to pass the divider data struct
directly instead of individual values of it. This makes it easier
to modify the implementation later on.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com>
Tero Kristo [Wed, 2 Oct 2019 12:06:08 +0000 (15:06 +0300)]
clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table
Cleanup couple of TI divider clock internal APIs. These currently pass
huge amount of parameters, which makes it difficult to track what is
going on. Abstract most of these under struct clk_omap_div which gets
passed over the APIs.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com>
Tero Kristo [Mon, 7 Oct 2019 12:26:04 +0000 (15:26 +0300)]
clk: ti: am43xx: drop idlest polling from gfx clock
Due to the way ti sysc and hardreset line control is now implemented,
it is not possible to poll the clock status for gfx clock independent
of hardreset line control. Thus, add a flag to prevent handling this
status bit from clock driver. Correct sequencing of events is guaranteed
by ti-sysc bus driver.
Tero Kristo [Mon, 7 Oct 2019 12:26:03 +0000 (15:26 +0300)]
clk: ti: am33xx: drop idlest polling from gfx clock
Due to the way ti sysc and hardreset line control is now implemented,
it is not possible to poll the clock status for gfx clock independent
of hardreset line control. Thus, add a flag to prevent handling this
status bit from clock driver. Correct sequencing of events is guaranteed
by ti-sysc bus driver.
Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tero Kristo [Thu, 12 Sep 2019 13:26:13 +0000 (16:26 +0300)]
clk: ti: am33xx: drop idlest polling from pruss clkctrl clock
The PRUSS module on AM33xx SoCs has a hardreset line and is controlled
by a PRCM reset line. Any clkctrl enable/disable operations cannot be
checked for module enabled/disabled status independent of the reset
operation, and this causes some unwanted timeouts in the kernel and
unbalanced states for the PRUSS clocks. These details should be handled
by the driver integration code itself.
Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these
module status checks are skipped.
Tero Kristo [Thu, 12 Sep 2019 13:26:12 +0000 (16:26 +0300)]
clk: ti: am43xx: drop idlest polling from pruss clkctrl clock
The PRUSS modules on AM43xx SoCs have a hardreset line and are controlled
by a PRCM reset line. Any clkctrl enable/disable operations cannot be
checked for module enabled/disabled status independent of the reset
operation, and this causes some unwanted timeouts in the kernel and
unbalanced states for the PRUSS clocks. These details should be handled
by the driver integration code itself.
Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these
module status checks are skipped.
Suman Anna [Thu, 12 Sep 2019 13:26:11 +0000 (16:26 +0300)]
clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks
The IPU and DSP remote processor cores and their corresponding MMUs on
OMAP5 SoCs have hardreset lines associated with them and are controlled
by a PRCM reset line each. Any clkctrl enable/disable operations cannot
be checked for module enabled/disabled status independent of the reset
operation, and this causes some unwanted timeouts in the kernel and
unbalanced states for these clocks. These details should be handled by
the driver integration code itself.
Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so
that these module status checks are skipped.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
projects / users / jedix / linux-maple.git / log