Ville Syrjälä [Wed, 5 Jun 2024 11:33:36 +0000 (14:33 +0300)]
drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG
No idea why the DDI clock gating print is done with drm_notice().
Just use drm_dbg_kms() since no one is going to be interested in
this under normal circumstances.
Jani Nikula [Wed, 29 May 2024 17:48:10 +0000 (20:48 +0300)]
drm/i915/display: include xe_bo.h, gem_object_types etc. where needed
Include what you use. The dependencies on the headers, and what they
include, is a bit convoluted. Add xe compat gem/gem_object_types.h. Fix
all the places needed.
Jani Nikula [Thu, 23 May 2024 13:37:05 +0000 (16:37 +0300)]
drm/i915: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Ville Syrjälä [Fri, 31 May 2024 11:53:42 +0000 (14:53 +0300)]
drm/i915: Protect CRC reg macro arguments for consistency
It's probably a good idea to start protecting all macro arguments
to avoid any cargo-cult mistakes when people go looking for examples
of how to define these things.
Ville Syrjälä [Fri, 31 May 2024 11:53:41 +0000 (14:53 +0300)]
drm/i915: Define the PIPE_CRC_EXP registers
I need a scratch register which fill the following requirements:
- can be accessed via DSB
- all the bits can be read/written
- no serious side effects
So far the only thing I could think of is the "expected CRC"
register. Add the definition so I can use it.
While I only need the hsw+ variant currently, let's define the
older variants as well for completeness.
Ville Syrjälä [Fri, 31 May 2024 11:53:39 +0000 (14:53 +0300)]
drm/i915: Add a separate definition for PIPE_CRC_RES_HSW
On hsw+ we only have one CRC result register, instead of the
five we have on ivb, and some of the others have been repurposed
to serve other CRC related purposes.
Since the hsw+ vs. pre-hsw register operate quite differently
let's add a separate definition for the hsw+ variant to make the
situation a bit more clear. Also since we only use this from a
hsw+ codepath there is no real benefit to be had with reusing
the ivb register definition.
Ville Syrjälä [Fri, 31 May 2024 11:53:38 +0000 (14:53 +0300)]
drm/i915: Regroup pipe CRC regs
Put all the definitions related to a single pipe CRC register
in one place, instead of the current approach where things are
spread all over the place.
Ville Syrjälä [Fri, 31 May 2024 11:53:37 +0000 (14:53 +0300)]
drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE()
PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid
for IVB+ where pipe register blocks are equally spaced, so we
can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for
these.
Ville Syrjälä [Fri, 31 May 2024 11:41:01 +0000 (14:41 +0300)]
drm/i915/dsb: Use intel_color_uses_dsb()
Use intel_color_uses_dsb() instead of open coding it in
intel_vblank_evade_init(). Make the logic around DSB a bit
more isolated from the rest of the code.
Ville Syrjälä [Fri, 31 May 2024 11:41:00 +0000 (14:41 +0300)]
drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()
Allow the caller of intel_dsb_prepare() to determine which DSB
engine (out of the three possible per pipe) to use. This will
let us utilize multiple DSB engines during the same commit.
Ville Syrjälä [Fri, 31 May 2024 11:40:59 +0000 (14:40 +0300)]
drm/i915/dsb: Move DSB ID definition to the header
We're going to need to make the DSB ID visible outside the DSB
code, so that we eg. can use multiple DSB engines in parallel.
to that end move the definition to intel_dsb.h.
Ville Syrjälä [Fri, 31 May 2024 11:40:58 +0000 (14:40 +0300)]
drm/i915/dsb: Polish the DSB ID enum
Namespace the DSB ID enum properly, and make the naming match
other such enums in general. Also make the names 0 based as
that's what Bspec uses for DSB (unlike eg. planes where it
uses 1 based indexing).
We'll throw out INVALID_DSB while at it since we have no use for
it at the moment.
warn next time around a power reference was put asynchronously, due to a
stale instance of the work still being pending. However the fix didn't
consider the case where multiple power reference was acquired and put,
requiring the work to requeue itself. Extend the fix for this case as
well canceling the pending instance of the work before it requeues
itself.
Jouni Högander [Wed, 29 May 2024 09:38:49 +0000 (12:38 +0300)]
drm/i915/psr: Add Early Transport into psr debugfs interface
We want to have sink Early Transport capability and usage in our psr
debugfs status interface.
v4: use su_region_et_enabled instead of psr2_su_region_et_valid
v3: remove extra space from "PSR mode: disabled"
v2: printout "Selective Update enabled (Early Transport)" instead of
"Selective Update Early Transport enabled"
Jouni Högander [Wed, 29 May 2024 09:38:48 +0000 (12:38 +0300)]
drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfs
Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug
debugfs interface is not allowed. This patch allows it.
v3:
- ensure psr is disabled/enabled if enable_psr2_su_region_et changes
- remove extra space
v2: ensure that fastset is performed when the bit changes
Jouni Högander [Wed, 29 May 2024 09:38:44 +0000 (12:38 +0300)]
drm/i915/psr: Add Early Transport status boolean into intel_psr
Currently we are purely relying on psr2_su_region_et_valid. Add new boolean
value into intel_psr struct indicating whether Early Transport is enabled
or not and use it instead of psr2_su_region_et_valid for getting Early
Transport status information.
Jani Nikula [Thu, 30 May 2024 13:19:11 +0000 (16:19 +0300)]
MAINTAINERS: update i915 and xe entries for include/drm/intel
With all the Intel specific drm files under include/drm/intel, update
the i915, xe, and the shared display entries. Do not discriminate based
on file name pattern, just add the entire directory for all three
entries.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Oded Gabbay <ogabbay@kernel.org> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Tvrtko Ursulin <tursulin@ursulin.net> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e0fdf28307bb3e457d8c67966c09c44cf7ff5783.1717075103.git.jani.nikula@intel.com
Jani Nikula [Thu, 30 May 2024 13:19:06 +0000 (16:19 +0300)]
drm: move i915_drm.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
v2: Also fix comment in intel_pci_config.h (Ilpo)
Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0e344a72e9be596ac2b8b55a26fd674a96f03cdc.1717075103.git.jani.nikula@intel.com
Jani Nikula [Thu, 30 May 2024 13:19:05 +0000 (16:19 +0300)]
drm: move intel_lpe_audio.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2d645970a65cfd13e01fd8195b35bf9483ae9c2f.1717075103.git.jani.nikula@intel.com
Jani Nikula [Thu, 30 May 2024 13:19:04 +0000 (16:19 +0300)]
drm: move i915_component.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
v2: Also change Documentation/gpu/i915.rst (Andi)
Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a8c07233a8234858eb6711140482ef8db4c91cf4.1717075103.git.jani.nikula@intel.com
Jani Nikula [Thu, 30 May 2024 13:19:03 +0000 (16:19 +0300)]
drm: move i915_gsc_proxy_mei_interface.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/461662d528c3f327c81b764b7c883cd4519d8729.1717075103.git.jani.nikula@intel.com
Ville Syrjälä [Tue, 28 May 2024 18:56:46 +0000 (21:56 +0300)]
drm/i915: Switch intel_usecs_to_scanlines() to 64bit maths
Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(),
with its 32bit maths, is currently limited to a few milliseconds.
I want bigger numbers in DSB selftests, so switch over to 64bit
maths.
Ville Syrjälä [Tue, 28 May 2024 18:56:44 +0000 (21:56 +0300)]
drm/i915: Simplify scanline_offset handling for gen2
Currently intel_crtc_scanline_offset() is careful to always
return a positive offset. That is not actually necessary
as long as we take care of negative values when applying the
offset in __intel_get_crtc_scanline().
This simplifies intel_crtc_scanline_offset(), and makes
the scanline_offfset arithmetic more symmetric between
the forward (__intel_get_crtc_scanline()) and reverse
(intel_crtc_scanline_to_hw()) directions.
Ville Syrjälä [Tue, 28 May 2024 18:56:42 +0000 (21:56 +0300)]
drm/i915: Extract intel_mode_vblank_end()
Extract intel_mode_vblank_end() in the same vein as
intel_mode_vblank_start(). While we have only one use
of this it seems nicer to unify the approach.
Ville Syrjälä [Tue, 28 May 2024 18:49:43 +0000 (21:49 +0300)]
drm/i915/cdclk: Plumb the full atomic state deeper
Various parts of the cdclk code need access the full atomic
state. Currently it's being dug out via the cdclk_state->base.state
pointer, which is not great as that pointer isn't always valid.
Instead plumb the full atomic state from the top so that it's
clear that it is in fact valid.
Jani Nikula [Wed, 22 May 2024 17:33:46 +0000 (20:33 +0300)]
drm/i915/display: add support for subplatforms
Add support for subplatforms. This is similar to what the xe driver is
doing. The subplatform is an enum and it's exclusive, i.e. only one
subplatform can match, and it completely identifies the platform and
subplatform. This is different from i915 core, and is notable in the
handling of ULT/ULX and RPL/RPL-U.
Jani Nikula [Wed, 22 May 2024 17:33:44 +0000 (20:33 +0300)]
drm/i915/display: change display probe to identify GMD ID based platforms
We'll need to identify all platforms, including the ones that have
display defined by GMD ID. Add MTL and LNL. Their display info will
still be probed via GMD ID.
Jani Nikula [Wed, 22 May 2024 17:33:42 +0000 (20:33 +0300)]
drm/i915/display: add platform descriptors
We'll need to start identifying the platforms independently in display
code in order to break free from the i915 and xe IS_<PLATFORM>()
macros. This is fairly straightforward, as we already identify most
platforms by PCI ID in display probe anyway.
As the first step, add platform descriptors with pointers to display
info. We'll have more platforms than display info, so minimize
duplication:
- Add separate skl/kbl/cfl/cml descriptors while they share the display
info.
- Add separate jsl/ehl descriptors while they share the display info.
Identify ADL-P (and derivatives) and DG2 descriptors by their names even
though their display info is Xe LPD or HPD.
Jani Nikula [Wed, 22 May 2024 17:33:40 +0000 (20:33 +0300)]
drm/i915/display: check platforms without display one level higher
The main change here is that the check for platforms without display is
now also done for GMD ID based platforms. However, without matches, the
end result is the same.
Animesh Manna [Wed, 29 May 2024 20:07:41 +0000 (01:37 +0530)]
drm/i915/alpm: Enable lobf from source in ALPM_CTL
Set the Link Off Between Frames Enable bit in ALPM_CTL register.
Note: Lobf need to be enabled adaptive sync fixed refresh mode
where vmin = vmax = flipline, which will arise after cmmr feature
enablement. Will add enabling sequence in a separate patch.
v1: Initial version.
v2: Condition check modified in alpm_configure(). [Jouni]
Animesh Manna [Wed, 29 May 2024 20:07:40 +0000 (01:37 +0530)]
drm/i915/alpm: Add compute config for lobf
Link Off Between Active Frames, is a new feature for eDP
that allows the panel to go to lower power state after
transmission of data. This is a feature on top of ALPM, AS SDP.
Add compute config during atomic-check phase.
v1: RFC version.
v2: Add separate flag for auxless-alpm. [Jani]
v3:
- intel_dp->lobf_supported replaced with crtc_state->has_lobf. [Jouni]
- Add DISPLAY_VER() check. [Jouni]
- Modify function name of get_aux_less_status. [Jani]
v4: Add enum alpm_mode to hold the aux-wake/less capability.
v5: Add alpm_dpcd to intel_dp and use aux_wake_supported()/
aux_less_wake_supported() instead of enum alpm_mode. [Jouni]
Luca Coelho [Tue, 28 May 2024 11:29:01 +0000 (14:29 +0300)]
drm/i915: move uapi.event outside spinlock in intel_crtc_vblank_work
In intel_crtc_vblank_work(), we access uapi.event before grabbing the
event_lock spinlock, but modify it inside the spinlock block. This
causes some static analyzers to get confused and issue a warning.
The uapi.event value is not protected by the event_lock, so we can
safely move it out of the protected block to prevent false positives.
Luca Coelho [Tue, 28 May 2024 11:29:00 +0000 (14:29 +0300)]
drm/i915/bios: double check array-boundary in parse_sdvo_lvds_data
During static analysis, a concern was raised that we may access the
dtd->dtd[] array out of bounds, because we are not checking whether
the index we use is larger than the array.
This should not be a problem as is, because the enumeration that is
used for this index comes from "panel_type", which uses an enumeration
with 4 items. But if this enumeration is ever changed, it can lead to
hard-to-detect bugs, so better double-check it before using it as an
index to the array.
Mika Kahola [Thu, 23 May 2024 13:46:49 +0000 (16:46 +0300)]
drm/i915/display: Add compare config for MTL+ platforms
Currently, we may bump into pll mismatch errors during the
state verification stage. This happens when we try to use
fastset instead of full modeset. Hence, we would need to add
a check for pipe configuration to ensure that the sw and the
hw configuration will match. In case of hw and sw mismatch,
we would need to disable fastset and use full modeset instead.
v2: Fix C10 error on PLL comparison (BAT)
Use memcmp instead of fixed loops for pll config
comparison (Jani)
Clean up and use intel_cx0pll_dump_hw_state() to dump
pll information (Jani)
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