Anisse Astier [Wed, 29 Dec 2021 22:21:59 +0000 (23:21 +0100)]
drm/i915/opregion: add support for mailbox #5 EDID
The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
used for the embedded display. Add support for using it via by adding
the EDID to the list of available modes on the connector, and use it for
eDP when available.
If a panel's EDID is broken, there may be an override EDID set in the
ACPI OpRegion mailbox #5. Use it if available.
Fixes the GPD Win Max display.
Based on original patch series by: Jani Nikula <jani.nikula@intel.com>
https://patchwork.kernel.org/project/intel-gfx/patch/20200828061941.17051-1-jani.nikula@intel.com/
Changes:
- EDID is copied and validated with drm_edid_is_valid
- EDID is now only used as a fallback.
- squashed the two patches
Cc: Jani Nikula <jani.nikula@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Anisse Astier <anisse@astier.eu> Link: https://patchwork.freedesktop.org/patch/msgid/20211229222200.53128-2-anisse@astier.eu
Andy Shevchenko [Wed, 22 Dec 2021 15:40:33 +0000 (17:40 +0200)]
drm/i915/dsi: Drop double check ACPI companion device for NULL
acpi_dev_get_resources() does perform the NULL pointer check against
ACPI companion device which is given as function parameter. Thus,
there is no need to duplicate this check in the caller.
Ville Syrjälä [Thu, 16 Dec 2021 11:08:22 +0000 (13:08 +0200)]
drm/i915/fbc: Remember to update FBC state even when not reallocating CFB
We mustn't forget to update our FBC state even if we don't have
to reallocate the CFB. Otherwise we won't refresh our notion
of what eg. the new fence or the new override CFB stride
should be. Using the wrong CFB stride in particular can cause
underruns and could even corrupt other stuff in stolen.
Jani Nikula [Wed, 22 Dec 2021 08:16:54 +0000 (10:16 +0200)]
drm/i915/bios: fix slab-out-of-bounds access
If VBT size is not a multiple of 4, the last 4-byte store will be out of
bounds of the allocated buffer. Spotted with KASAN. Round up the
allocation size.
v2: Use round_up() intead of roundup() as it's a power of 2 (Thomas)
Reported-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Fixes: a36e7dc0af1c ("drm/i915/dg1: Read OPROM via SPI controller") Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211222081654.1843211-1-jani.nikula@intel.com
Ville Syrjälä [Tue, 21 Dec 2021 19:37:53 +0000 (21:37 +0200)]
drm: Always include the debugfs dentry in drm_crtc
Remove the counterproductive CONFIG_DEBUG_FS ifdef and just include
the debugfs dentry in drm_crtc always. This way we don't need
annoying ifdefs in the actual code with DEBUGFS=n. Also we don't
have these ifdefs around any of the other debugfs dentries either
so can't see why drm_crtc should be special.
This fixes the i915 DEBUGFS=n build because I assumed the dentry
would always be there.
Cc: Jani Nikula <jani.nikula@intel.com> Reported-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Fixes: e74c6aa955ca ("drm/i915/fbc: Register per-crtc debugfs files") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211221193754.12287-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Daniel Vetter <daniel@ffwll.ch>
Clint Taylor [Thu, 16 Dec 2021 06:26:45 +0000 (22:26 -0800)]
drm/i915/dg1: Read OPROM via SPI controller
Read OPROM SPI through MMIO and find VBT entry since we can't use
OpRegion and PCI mapping may not work on some systems due to most BIOSes
not leaving the Option ROM mapped.
v2: Remove message with allocation failure
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211216062645.3477854-1-lucas.demarchi@intel.com
Hans de Goede [Sun, 21 Nov 2021 19:10:01 +0000 (20:10 +0100)]
drm/i915: Remove unused intel_gmbus_set_speed() function
The intel_gmbus_set_speed() function is not used anywhere, remove it.
Note drivers/gpu/drm/gma500 has its own copy called
gma_intel_gmbus_set_speed() which is used, the intel_gmbus_set_speed()
version in the i915 code is not used at all
Hans de Goede [Sun, 21 Nov 2021 11:00:32 +0000 (12:00 +0100)]
drm/i915/backlight: Make ext_pwm_disable_backlight() call intel_backlight_set_pwm_level()
At least the Bay Trail LPSS PWM controller used with DSI panels on many
Bay Trail tablets seems to leave the PWM pin in whatever state it was
(high or low) ATM that the PWM gets disabled. Combined with some panels
not having a separate backlight-enable pin this leads to the backlight
sometimes staying on while it should not (when the pin was high during
PWM-disabling).
First calling intel_backlight_set_pwm_level() will ensure that the pin
is always low (or high for inverted brightness panels) since the passed
in duty-cycle is 0% (or 100%) when the PWM gets disabled fixing the
backlight sometimes staying on.
With the exception of ext_pwm_disable_backlight() all other
foo_disable_backlight() functions call intel_backlight_set_pwm_level()
already before disabling the backlight, so this change also aligns
ext_pwm_disable_backlight() with all the other disable() functions.
Ville Syrjälä [Mon, 13 Dec 2021 13:44:49 +0000 (15:44 +0200)]
drm/i915/fbc: Introduce device info fbc_mask
Declare which FBC instances are present via a fbc_mask
in device info. For the moment there is just the one.
TODO: Need to figure out how to expose multiple FBC
instances in debugs. Just different file names, or move
the files under some subdirectory (per-crtc maybe), or
something else? This will need igt changes as well.
v2: Put the mask into device_info.display (Jani)
Put the magic pipe->fbc thing into skl_fbc_id_for_pipe() (Jani)
Ville Syrjälä [Mon, 13 Dec 2021 13:44:48 +0000 (15:44 +0200)]
drm/i915/fbc: Loop through FBC instances in various places
Convert i915->fbc into an array in preparation for
multiple FBC instances, and loop through all instances
in all places where the caller does not know which
instance(s) (if any) are relevant. This is the case
for eg. frontbuffer tracking and FIFO underrun hadling.
v2: More intel_ namespace (Jani)
Leave out debugfs for later
Jani Nikula [Mon, 13 Dec 2021 11:41:05 +0000 (13:41 +0200)]
drm/i915/cdclk: turn around i915_drv.h and intel_cdclk.h dependency
intel_cdclk.h only needs i915_drv.h for struct intel_cdclk_config. Move
the definition to intel_cdclk.h and turn the includes around to avoid
including i915_drv.h from other headers.
The intel cdclk state macros in intel_cdclk.h still reference struct
drm_i915_private, but as macros they don't strictly require the
definition until they are used.
v2: Expand on the commit message wrt cdclk state macros
Mark Brown [Mon, 13 Dec 2021 17:07:53 +0000 (17:07 +0000)]
drm/i915: Fix implicit use of struct pci_dev
intel_device_info.h references struct pci_dev but does not ensure that
the struct has been declared, causing build failures if something in
other headers changes so that the implicit dependency it is relying on
is no longer satisfied:
In file included from drivers/gpu/drm/i915/intel_device_info.h:32,
from drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:11,
from drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:11:
drivers/gpu/drm/i915/display/intel_display.h:643:39: error: 'struct pci_dev' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
643 | bool intel_modeset_probe_defer(struct pci_dev *pdev);
| ^~~~~~~
cc1: all warnings being treated as errors
Ville Syrjälä [Fri, 10 Dec 2021 12:27:26 +0000 (14:27 +0200)]
drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
Collect the dipslay related mask under the display sub-structure
in intel_device_info.
Note that there is a slight change in behaviour in that we zero
out .display entirely when !HAS_DISPLAY (aka. pipe_mask==0), so
now we also zero out the other masks (although cpu_transocder_mask
should already be zero of pipe_mask is zero). abox_mask is
only used by the display core init when HAS_DISPLAY is true, so
the actual behaviour of the system shouldn't change despite the
zeroing of these masks.
There is a lot more display stuff directly in device info that
could be moved over. Maybe someone else will be inspired to do it...
Hans de Goede [Tue, 5 Oct 2021 20:23:22 +0000 (22:23 +0200)]
drm/i915: Add privacy-screen support (v3)
Add support for eDP panels with a built-in privacy screen using the
new drm_privacy_screen class.
Changes in v3:
- Move drm_privacy_screen_get() call to intel_ddi_init_dp_connector()
Changes in v2:
- Call drm_connector_update_privacy_screen() from
intel_enable_ddi_dp() / intel_ddi_update_pipe_dp() instead of adding a
for_each_new_connector_in_state() loop to intel_atomic_commit_tail()
- Move the probe-deferral check to the intel_modeset_probe_defer() helper
Hans de Goede [Tue, 5 Oct 2021 20:23:21 +0000 (22:23 +0200)]
drm/i915: Add intel_modeset_probe_defer() helper
The upcoming privacy-screen support adds another check for
deferring probe till some other drivers have bound first.
Factor out the current vga_switcheroo_client_probe_defer() check
into an intel_modeset_probe_defer() helper, so that further
probe-deferral checks can be added there.
Jani Nikula [Wed, 8 Dec 2021 11:05:17 +0000 (13:05 +0200)]
drm/i915/trace: split out display trace to a separate file
Add display/intel_display_trace.[ch] for defining display
tracepoints. The main goal is to reduce cross-includes between gem and
display. It would be possible split up tracing even further, but that
would lead to more boilerplate.
We end up having to include intel_crtc.h in a few places because it was
pulled in implicitly via intel_de.h -> i915_trace.h -> intel_crtc.h, and
that's no longer the case.
Changes since v2.12:
- Release notes for v2.13:
1. Fix for simple flip queue with DC6v
- Release notes for v2.14:
1. Fix for flip queue roll over cases with DC6v
2. Enhancement for residency
3. Workaround for 3Dlut restore issue
Siva Mullati [Wed, 8 Dec 2021 04:12:15 +0000 (09:42 +0530)]
drm/i915: Skip remap_io_mapping() for non-x86 platforms
Only hw that supports mappable aperture would hit this path
vm_fault_gtt/vm_fault_tmm, So we never hit this function
remap_io_mapping() in discrete, So skip this code for non-x86
architectures.
v2: use IS_ENABLED () instead of #if defined
v3: move function prototypes from i915_drv.h to i915_mm.h
Mika Kahola [Fri, 19 Nov 2021 13:13:47 +0000 (15:13 +0200)]
drm/i915/display/dg2: Read CD clock from squasher table
To calculate CD clock with squasher unit, we set CD clock ratio to fixed value of 34.
The CD clock value is read from CD clock squasher table.
BSpec: 54034
v2: Read ratio from register (Ville)
Drop unnecessary local variable (Ville)
Get CD clock from the given table
v3: Calculate CD clock frequency based on waveform bit pattern (Ville)
[v4: vsyrjala: Actually do a proper blind readout from the hardware]
[v5: vsyrjala: Use has_cdclk_squasher()]
Mika Kahola [Fri, 19 Nov 2021 13:13:46 +0000 (15:13 +0200)]
drm/i915/display/dg2: Set CD clock squashing registers
Set CD clock squashing registers based on selected CD clock.
v2: use slk_cdclk_decimal() to compute decimal values instead of a
specific table (Ville)
Set waveform based on CD clock table (Ville)
Drop unnecessary local variable (Ville)
v3: Correct function naming (Ville)
Correct if-else structure (Ville)
[v4: vsyrjala: Fix spaces vs. tabs]
[v5: vsyrjala: Fix cd2x divider calculation (Uma),
Add warn to waveform lookup (Uma),
Handle bypass freq in waveform lookup,
Generalize waveform handling in bxt_set_cdclk()]
Mika Kahola [Fri, 19 Nov 2021 13:13:44 +0000 (15:13 +0200)]
drm/i915/display/dg2: Introduce CD clock squashing table
For CD clock squashing method, we need to define corresponding CD clock table for
reference clocks, dividers and ratios for all CD clock options.
BSpec: 54034
v2: Add CD squashing waveforms as part of CD clock table (Ville)
v3: Waveform is 16 bits wide (Ville)
[v4: vsyrjala: Nuke the non-squasher based table,
Set .divider=2 for consistency,
Pack intel_cdclk_vals a bit nicer]
v5: Fix error in waveform value (Swati)
v6 (Lucas): Rebase on upstream
v7 (MattR): Drop 40.8, 81.6, and 122.4 MHz frequencies to reflect new
bspec update.
Uma Shankar [Tue, 7 Dec 2021 07:11:35 +0000 (12:41 +0530)]
drm/i915/xelpd: Add Pipe Color Lut caps to platform config
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
v2: Updated lut size for 10bit gamma, added lut_tests (Ville)
Uma Shankar [Tue, 7 Dec 2021 07:11:33 +0000 (12:41 +0530)]
drm/i915/xelpd: Enable Pipe color support for D13 platform
Enable pipe color support for Display 13 platforms. Currently
limit to just 10bit gamma and later extend it for logarithmic
gamma, once the new UAPI is agreed by community and implemented
by a userspace consumer.
Remove force probe protection from ADL_P platform. Did not obsevre
warnings, errors, flickering or any visual defects while doing ordinary
tasks like browsing and editing documents in a two monitor setup.
For more info drm-tip idle run results :
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?
Tejas Upadhyay [Fri, 3 Dec 2021 07:37:20 +0000 (13:07 +0530)]
drm/i915/adl_p: Add ddc pin mapping
From VBT, ddc pin info suggests the following mapping:
VBT DRIVER
DDI TC1->ddc_pin=3 should translate to PORT_TC1->0x9
DDI TC2->ddc_pin=4 should translate to PORT_TC2->0xa
DDI TC3->ddc_pin=5 should translate to PORT_TC3->0xb
DDI TC4->ddc_pin=6 should translate to PORT_TC4->0xc
Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI C and DDI TC1 info.
Bspec:20124
v2:
- Changed Author to Tejas Upadhyay
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Acked-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203073720.3823371-1-ravitejax.goud.talla@intel.com
Ville Syrjälä [Wed, 24 Nov 2021 11:36:52 +0000 (13:36 +0200)]
drm/i915/fbc: Pimp the FBC debugfs output
Now that each plane tracks its own no_fbc_reason we can print that
out in debugfs, and we can also show which plane is currently
selected for FBC duty.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:49 +0000 (13:36 +0200)]
drm/i915/fbc: Move plane pointer into intel_fbc_state
Currently we track the FBC plane as a pointer under intel_fbc
and also as a i9xx_plane_id under intel_fbc_state. Just store
the pointer once in the fbc state.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:47 +0000 (13:36 +0200)]
drm/i915/fbc: Disable FBC fully on FIFO underrun
Currently a FIFO underrun just causes FBC to be deactivated,
and later checks then prevent it from being reactivated. We
can simpify our lives a bit by logically disabling FBC on
FIFO underruns. This avoids the funny intermediate state where
FBC is logically enabled but can't actually be activated.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:45 +0000 (13:36 +0200)]
drm/i915/fbc: Allocate intel_fbc dynamically
In the future we may have more than one FBC instance on some
platforms. So let's just allocate it dynamically. This also
lets us fully hide the implementation from prying eyes.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:42 +0000 (13:36 +0200)]
drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
The underrun code doesn't need to know any details about FBC, so
just pass in the whole device rather than a specific FBC instance.
We could make this a bit more fine grained by also passing in the
pipe to intel_fbc_handle_fifo_underrun_irq() and letting the FBC
code figure which FBC instance (if any) is active on said pipe.
But that seems a bit overkill for this so don't bother.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:40 +0000 (13:36 +0200)]
drm/i915/fbc: Track FBC usage per-plane
In the future we may have multiple planes on the same pipe
capable of using FBC. Prepare for that by tracking FBC usage
per-plane rather than per-crtc.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:39 +0000 (13:36 +0200)]
drm/i915/fbc: Pass around FBC instance instead of crtc
Pass the FBC instance instead of the crtc to a bunch of places.
We also adjust intel_fbc_post_update() to do the
intel_fbc_get_reg_params() things instead of doing it from the lower
level function (which also gets called for front buffer tracking).
Nothing in there will change during front buffer updates.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:37 +0000 (13:36 +0200)]
drm/i915/fbc: Nuke more FBC state
There isn't a good reason why we'd have to cache all this
plane state stuff in the FBC state. Instead we can just
pre-calculate what FBC will really need.
Ville Syrjälä [Wed, 24 Nov 2021 11:36:35 +0000 (13:36 +0200)]
drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
There's no need to store all this stuff in intel_fbc_state_cache.
Just check it all against the plane/crtc states and store only
what we need. Probably more should get nuked still, but this
is a start.
So what we'll do is:
- each plane will check its own state and update its local
no_fbc_reason
- the per-plane no_fbc_reason (if any) then gets propagated
to the cache->no_fbc_reason while doing the actual update
- fbc->no_fbc_reason gets updated in the end with either
the value from the cache or directly from frontbuffer
tracking
It's still a bit messy, but should hopefuly get cleaned up
more in the future. At least now we can observe each plane's
reasons for rejecting FBC now more consistently, and we don't
have so mcuh redundant state store all over the place.
v2: store no_fbc_reason per-plane instead of per-pipe
Ville Syrjälä [Wed, 24 Nov 2021 11:36:34 +0000 (13:36 +0200)]
drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
No reason to burden the caller with the details on how the minimum
compression limit is calculated, so just pass in the whole plane
state instead of just the cpp value.
The ilk fbc watermark computation uses intel_fbc_is_active() which
is racy since we don't know whether FBC will be enabled or not at
some point. So let's just assume it will be if both HAS_FBC()
and the modparam agree.
Ville Syrjälä [Wed, 1 Dec 2021 15:25:39 +0000 (17:25 +0200)]
drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
Let's just stick to 32bit mmio accesses so we can get rid
of the bare "uncore" reg access in display code. The register
are defined as 32bit in the spec anyway.
We could define a 64bit "de" variant I suppose, but doesn't
really make much sense just for this one case, and when we
start to use the DSB for this stuff we'd also need another
64bit variant for that. Just easier to do 32bit always.
While at it we can reorder stuff a bit so that we write the
registers in order of increasing offset (more or less).
Jani Nikula [Wed, 1 Dec 2021 13:57:11 +0000 (15:57 +0200)]
drm/i915/display: convert dp_to_i915() to a macro
Avoid looking into the guts of struct drm_i915_private in
headers. Again, converting an inline function to a macro is less than
ideal, but avoids having to pull in i915_drv.h just for the to_i915()
part.
Anshuman Gupta [Tue, 30 Nov 2021 13:20:05 +0000 (18:50 +0530)]
drm/i915/selftest: Disable IRQ for timestamp calculation
gt_pm selftest calculates engine ticks cycles and wall time
cycles by delta of respective engine elapsed TIMESTAMP and ktime
for period of 1000us.
It compares the engine ticks cycles with wall time cycles.
Disable local cpu interrupt so that interrupt handler does not
switch out the thread during measure_clocks() and prevent
miscalculation of engine tick cycles.
v2:
- nuke preempt_{disable,enable}, as disable_local_irq()
disable the preemption. (Chris)
Matt Roper [Tue, 16 Nov 2021 17:48:15 +0000 (09:48 -0800)]
drm/i915/dg2: Add Wa_14010547955
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.
Matt Roper [Tue, 16 Nov 2021 17:48:14 +0000 (09:48 -0800)]
drm/i915/dg2: s/DISP_STEPPING/DISPLAY_STEPPING/
Commit cd0fcf5af791 ("drm/i915: rename DISP_STEPPING->DISPLAY_STEP and
GT_STEPPING->GT_STEP") renamed all platforms' display stepping tests,
but the DG2 patches were still in-flight at that time and did not
incorporate the new naming scheme. Rename DG2's macro now for
consistency with other platforms.
Vidya Srinivas [Thu, 2 Dec 2021 11:08:36 +0000 (16:38 +0530)]
drm/i915: Add PLANE_CUS_CTL restriction in max_width
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Take care of this restriction in max_width.
Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out.
v2: Addressed review comments from Ville. Added separate
functions for max_width - for HDR and SDR
v3: Addressed review comments from Ville. Changed names of
HDR and SDR max_width functions to icl_hdr_plane_max_width
and icl_sdr_plane_max_width
Jani Nikula [Wed, 1 Dec 2021 13:57:03 +0000 (15:57 +0200)]
drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it
intel_wait_for_vblank() goes through a pipe to crtc lookup, while in
most cases we already have the crtc available. Avoid the extra lookups
by adding an intel_crtc based helper.
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