drm/msm/dpu: re-introduce dpu core revision to the catalog
Introduce the dpu core revision back as an entry to the catalog so that
we can just use dpu revision checks and enable those bits which
should be enabled unconditionally and not controlled by a catalog
and also simplify the changes to do something like:
if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx)
enable the bit;
changes in v5:
- fix the commit text to remove instances of DPU_HW_VER
Jessica Zhang [Tue, 27 Jun 2023 20:31:45 +0000 (13:31 -0700)]
drm/msm/dsi: Enable BURST_MODE for command mode for DSI 6G v1.3+
During a frame transfer in command mode, there could be frequent
LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or
if the DSI controller is running on slow clock and is throttled. To
minimize frame latency due to these transitions, it is recommended to
send the frame in a single burst.
This feature is supported for DSI 6G 1.3 and above, thus enable burst
mode if supported.
Ryan McCann [Sat, 8 Jul 2023 01:24:45 +0000 (18:24 -0700)]
drm/msm/dpu: Update dev core dump to dump registers of sub-blocks
Currently, the device core dump mechanism does not dump registers of
sub-blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Edit
dpu_kms_mdp_snapshot function to account for sub-blocks.
Ryan McCann [Sat, 8 Jul 2023 01:24:44 +0000 (18:24 -0700)]
drm/msm/dpu: Refactor printing of main blocks in device core dump
Currently, the names of main blocks are hardcoded into the
msm_disp_snapshot_add_block function rather than using the name that
already exists in the catalog. Change this to take the name directly from
the catalog instead of hardcoding it.
Ryan McCann [Sat, 8 Jul 2023 01:24:43 +0000 (18:24 -0700)]
drm/msm/dpu: Remove redundant prefix/suffix in name of sub-blocks
For a device core dump, the registers of sub-blocks are printed under a
title formatted as <mainBlkName_sblkName>. For example, the csc sub-block
for an SSPP main block "sspp_0" would be printed "sspp_0_sspp_csc0". The
title is clearly redundant due to the duplicate "sspp" and "0" that exist
in both the mainBlkName and sblkName. To eliminate this redundancy, remove
the secondary "sspp" and "0" that exist in the sub-block name by
elimanting the "sspp_" prefix and the concatenation of "num" that results
in the redundant "0" suffix. Remove num parameter altogether from relevant
macros as a consequence of it no longer being used.
Ryan McCann [Sat, 8 Jul 2023 01:24:42 +0000 (18:24 -0700)]
drm/msm/dpu: Define names for unnamed sblks
Some sub-blocks in the hw catalog have not been given a name, so when the
registers from that block are dumped, there is no name to reference.
Define names for relevant sub-blocks to fix this.
Ryan McCann [Sat, 8 Jul 2023 01:24:40 +0000 (18:24 -0700)]
drm/msm: Update dev core dump to not print backwards
Device core dump add block method adds hardware blocks to dumping queue
with stack behavior which causes the hardware blocks to be printed in
reverse order. Change the addition to dumping queue data structure
from "list_add" to "list_add_tail" for FIFO queue behavior.
Fixes: 98659487b845 ("drm/msm: add support to take dpu snapshot") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/546200/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-1-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
drm/msm/dpu: correct indentation for CTL definitions
Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
This is done in preparation to expanding the rest of hardware block
defines, so that all blocks have similar indentation.
In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
for DSI interfaces.
Kuogee Hsieh [Thu, 22 Jun 2023 17:24:46 +0000 (10:24 -0700)]
drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info
Since struct drm_dsc_config is stored at atomic_enable() instead
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct msm_display_info.
Kuogee Hsieh [Thu, 22 Jun 2023 17:24:45 +0000 (10:24 -0700)]
drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0]
Currently struct drm_dsc_config for DSI is populated at display
setup during system boot up. This mechanism works fine with
embedded display but not for pluggable displays as the
struct drm_dsc_config will become stale once external display
is unplugged.
In preparation of adding support for DP DSC support
move storing of DSI DSC struct to atomic_enable() so that same
mechanism will work for both embedded display and pluggable
displays.
Changes in v4:
-- fix checkpatch.pl warning
Changes in v5:
-- delete dpu_encoder_get_dsc_config() from atomic_mode_set
Konrad Dybcio [Thu, 20 Apr 2023 01:14:54 +0000 (03:14 +0200)]
drm/msm/dpu1: Rename sm8150_dspp_blk to sdm845_dspp_blk
SDM845 was the first SoC to include both PCC v4 and GC v1.8.
We don't currently support any other blocks but the common config
for these two can be reused for a large amount of SoCs.
Rename it to indicate the origin of that combo.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/533003/ Link: https://lore.kernel.org/r/20230420-topic-dpu_gc-v1-1-d9d1a5e40917@linaro.org
[DB: also applied to new catalog files] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:21:01 +0000 (01:21 +0200)]
drm/msm/a6xx: Add A610 speedbin support
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542780/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:21:00 +0000 (01:21 +0200)]
drm/msm/a6xx: Add A619_holi speedbin support
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542772/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:59 +0000 (01:20 +0200)]
drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542777/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:58 +0000 (01:20 +0200)]
drm/msm/a6xx: Use "else if" in GPU speedbin rev matching
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542770/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:56 +0000 (01:20 +0200)]
drm/msm/a6xx: Add A610 support
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset line broken - after a couple of assert/
deassert cycles, it will hang for good and will not wake up again.
This GPU requires mesa changes for proper rendering, and lots of them
at that. The command streams are quite far away from any other A6XX
GPU and hence it needs special care. This patch was validated both
by running an (incomplete) downstream mesa with some hacks (frames
rendered correctly, though some instructions made the GPU hangcheck
which is expected - garbage in, garbage out) and by replaying RD
traces captured with the downstream KGSL driver - no crashes there,
ever.
Add support for this GPU on the kernel side, which comes down to
pretty simply adding A612 HWCG tables, altering a few values and
adding a special case for handling the reset line.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542779/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:55 +0000 (01:20 +0200)]
drm/msm/a6xx: Add support for A619_holi
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542775/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:54 +0000 (01:20 +0200)]
drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations
A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
as none of the GMU wrapper Adrenos that don't support yet seem to feature it.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542774/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:53 +0000 (01:20 +0200)]
drm/msm/a6xx: Introduce GMU wrapper support
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno-common code and modify the deeply-GMU-infused
A6XX code to facilitate these GPUs. This involves if-ing out lots
of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's
the actual name that Qualcomm uses in their downstream kernels).
This is essentially a register region which is convenient to model
as a device. We'll use it for managing the GDSCs. The register
layout matches the actual GMU_CX/GX regions on the "real GMU" devices
and lets us reuse quite a bit of gmu_read/write/rmw calls.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542766/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:52 +0000 (01:20 +0200)]
drm/msm/a6xx: Move CX GMU power counter enablement to hw_init
Since the introduction of A6xx support, we've been enabling the CX GMU
power counter 0 in a bit of a weird spot. Move it to hw_init so that
GMU wrapper GPUs can reuse the same code paths. As a bonus, this order
makes it easier to compare mainline and downstream register access traces.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542765/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:51 +0000 (01:20 +0200)]
drm/msm/a6xx: Extend and explain UBWC config
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542764/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:50 +0000 (01:20 +0200)]
drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0.
This is typically done automatically on successful GX collapse, but in
case that fails, we should take care of it.
Also, add a memory barrier to ensure it's gone through before jumping
to further initialization.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542760/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:49 +0000 (01:20 +0200)]
drm/msm/a6xx: Add a helper for software-resetting the GPU
Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
GPUs and reuse it in a6xx_gmu_force_off().
This helper, contrary to the original usage in GMU code paths, adds
a readback+delay sequence to ensure that the reset is never deasserted
too quickly due to e.g. OoO execution going crazy.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542758/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Unify the indentation and explain the cryptic 0xF value.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542756/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:47 +0000 (01:20 +0200)]
drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu
This function is responsible for telling the GPU to halt transactions
on all of its relevant buses, drain them and leave them in a predictable
state, so that the GPU can be e.g. reset cleanly.
Move the function to a6xx_gpu.c, remove the static keyword and add a
prototype in a6xx_gpu.h to accomodate for the move.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542762/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:46 +0000 (01:20 +0200)]
drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off()
As pointed out by Akhil during the review process of GMU wrapper
introduction [1], it makes sense to move this write into the function
that's responsible for forcibly shutting the GMU off.
It is also very convenient to move this to GMU-specific code, so that
it does not have to be guarded by an if-condition to avoid calling it
on GMU wrapper targets.
Move the write to the aforementioned a6xx_gmu_force_off() to achieve
that. No effective functional change.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542752/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:45 +0000 (01:20 +0200)]
drm/msm/a6xx: Remove static keyword from sptprac en/disable functions
These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542751/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:44 +0000 (01:20 +0200)]
drm/msm/adreno: Use adreno_is_revn for A690
The adreno_is_revn rework came at the same time as A690 introduction
and that resulted in it not covering all cases. Fix it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542754/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Thu, 15 Jun 2023 23:20:43 +0000 (01:20 +0200)]
dt-bindings: display/msm/gmu: Add GMU wrapper
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.
The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.
To sum it all up, the GMU wrapper is essentially a register space within
the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks,
interrupts, multiple reg spaces, iommus and OPP. Document it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542750/ Signed-off-by: Rob Clark <robdclark@chromium.org>
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.
The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.
GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be
specified under the GPU node, just like their older cousins. Account
for that.
Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542748/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Dmitry Baryshkov [Wed, 14 Jun 2023 22:44:02 +0000 (01:44 +0300)]
drm/msm/dsi: split dsi_ctrl_config() function
It makes no sense to pass NULL parameters to dsi_ctrl_config() in the
disable case. Split dsi_ctrl_config() into enable and disable parts and
drop unused params.
Dmitry Baryshkov [Tue, 13 Jun 2023 00:09:40 +0000 (03:09 +0300)]
drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts
During IRQ conversion we have lost the PP_DONE interrupts for sc7280
platform. This was left unnoticed, because this interrupt is only used
for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels.
Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw catalog") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/542175/ Link: https://lore.kernel.org/r/20230613001004.3426676-2-dmitry.baryshkov@linaro.org
Bjorn Andersson [Mon, 12 Jun 2023 22:02:59 +0000 (15:02 -0700)]
drm/msm/dp: Free resources after unregistering them
The DP component's unbind operation walks through the submodules to
unregister and clean things up. But if the unbind happens because the DP
controller itself is being removed, all the memory for those submodules
has just been freed.
Change the order of these operations to avoid the many use-after-free
that otherwise happens in this code path.
Bjorn Andersson [Mon, 12 Jun 2023 22:01:06 +0000 (15:01 -0700)]
drm/msm/dp: Drop aux devices together with DP controller
Using devres to depopulate the aux bus made sure that upon a probe
deferral the EDP panel device would be destroyed and recreated upon next
attempt.
But the struct device which the devres is tied to is the DPUs
(drm_dev->dev), which may be happen after the DP controller is torn
down.
Indications of this can be seen in the commonly seen EDID-hexdump full
of zeros in the log, or the occasional/rare KASAN fault where the
panel's attempt to read the EDID information causes a use after free on
DP resources.
It's tempting to move the devres to the DP controller's struct device,
but the resources used by the device(s) on the aux bus are explicitly
torn down in the error path. The KASAN-reported use-after-free also
remains, as the DP aux "module" explicitly frees its devres-allocated
memory in this code path.
As such, explicitly depopulate the aux bus in the error path, and in the
component unbind path, to avoid these issues.
Fixes: 2b57f726611e ("drm/msm/dp: fix aux-bus EP lifetime") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/542163/ Link: https://lore.kernel.org/r/20230612220106.1884039-1-quic_bjorande@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Baryshkov [Mon, 12 Jun 2023 03:16:15 +0000 (06:16 +0300)]
drm/msm: provide fb_dirty implemenation
Since commit 93e81e38e197 ("drm/fb_helper: Minimize damage-helper
overhead") the drm_fb_helper_funcs::fb_dirty helper is required for
proper dirty/damage processing. The drm/msm driver requires that to
function to let CMD panels to work. Use simplified version of
drm_fbdev_generic_helper_fb_dirty() to fix support for CMD mode panels.
Jessica Zhang [Fri, 9 Jun 2023 22:57:17 +0000 (15:57 -0700)]
drm/msm/dsi: Remove incorrect references to slice_count
Currently, slice_count is being used to calculate word count and
pkt_per_line. Instead, these values should be calculated using slice per
packet, which is not the same as slice_count.
Slice count represents the number of slices per interface, and its value
will not always match that of slice per packet. For example, it is possible
to have cases where there are multiple slices per interface but the panel
specifies only one slice per packet.
Thus, use the default value of one slice per packet and remove slice_count
from the aforementioned calculations.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Fixes: bc6b6ff8135c ("drm/msm/dsi: Use DSC slice(s) packet size to compute word count") Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/541965/ Link: https://lore.kernel.org/r/20230405-add-dsc-support-v6-5-95eab864d1b6@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Jessica Zhang [Fri, 9 Jun 2023 22:57:16 +0000 (15:57 -0700)]
drm/msm/dpu: Set DATA_COMPRESS on command mode for DCE/DSC 1.2
Add a DPU INTF op to set the DCE_DATA_COMPRESS bit to enable the
DCE/DSC 1.2 datapath
Note: For now, this op is called for command mode encoders only. Changes to
set DATA_COMPRESS for video mode encoders will be posted along with DSC
v1.2 support for DP.
Jessica Zhang [Fri, 9 Jun 2023 22:57:15 +0000 (15:57 -0700)]
drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag for DPU >= 7.0
In DPU 7.x and later, DSC/DCE enablement registers have been moved from
PINGPONG to INTF. Thus, add a DPU_INTF_DATA_COMPRESS feature flag that will
be set if the DATA_COMPRESS register is in the INTF block.
Jessica Zhang [Fri, 9 Jun 2023 22:57:13 +0000 (15:57 -0700)]
msm/drm/dsi: Round up DSC hdisplay calculation
Currently, when compression is enabled, hdisplay is reduced via integer
division. This causes issues for modes where the original hdisplay is
not a multiple of 3.
Abhinav Kumar [Thu, 25 May 2023 17:40:57 +0000 (10:40 -0700)]
drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.
changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- re arrange sc8280xp_dsc[]
changes in v4:
-- fix checkpatch warning
changes in v10:
-- remove hard slice from commit text
-- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN
-- change DSC_BLK_1_2 .len from 0x100 to 0x29c
changes in v11:
-- remove comment at DSC_BLK_1_2 marco
Kuogee Hsieh [Thu, 25 May 2023 17:40:54 +0000 (10:40 -0700)]
drm/msm/dpu: add support for DSC encoder v1.2 engine
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete off and used real register name directly
Changes in v7:
-- replace offset with sblk->enc.base
-- replace ss with slice
Changes in v8:
-- fixed checkpatch warning
Changes in v9:
-- replaced __dsc_calc_ob_max_addr() with __dsc_calc_output_buf_max_addr()
-- replaced variable num_ss with num_softslice
-- remove inline from function declaration
changes in v10:
-- rewording text of changes in v9
-- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN
-- replace drm_dsc_calculate_flatness_det_thresh() with drm_dsc_flatness_det_thresh()
Dmitry Baryshkov [Wed, 24 May 2023 17:45:17 +0000 (10:45 -0700)]
drm/msm/dsi: use DRM DSC helpers for DSC setup
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Dmitry Baryshkov [Wed, 24 May 2023 17:45:15 +0000 (10:45 -0700)]
drm/display/dsc: add helper to set semi-const parameters
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Dmitry Baryshkov [Mon, 12 Jun 2023 18:25:27 +0000 (21:25 +0300)]
drm/msm/adreno: make adreno_is_a690()'s argument const
Change adreno_is_a690() prototype to accept the const struct adreno_gpu
pointer instead of a non-const one. This fixes the following warning:
In file included from drivers/gpu/drm/msm/msm_drv.c:33:
drivers/gpu/drm/msm/adreno/adreno_gpu.h: In function ‘adreno_is_a660_family’:
drivers/gpu/drm/msm/adreno/adreno_gpu.h:303:54: warning: passing argument 1 of ‘adreno_is_a690’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
303 | return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
Fixes: 1b90e8f8879c ("drm/msm/adreno: change adreno_is_* functions to accept const argument") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/542138/ Link: https://lore.kernel.org/r/20230612182527.3345786-1-dmitry.baryshkov@linaro.org
drm/msm/adreno: change adreno_is_* functions to accept const argument
All adreno_is_*() functions do not modify their argument in any way, so
they can be changed to accept const struct adreno_gpu pointer.
Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/531706/ Signed-off-by: Rob Clark <robdclark@chromium.org>
drm/msm/adreno: warn if chip revn is verified before being set
The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno
510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE
to prevent such bugs from happening again. A separate helper is
necessary so that the warning is displayed really just once instead of
being displayed for each of comparisons.
Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/531705/ Signed-off-by: Rob Clark <robdclark@chromium.org>
drm/msm/a5xx: really check for A510 in a5xx_gpu_init
The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno
510") added special handling for a510 (this SKU doesn't seem to support
preemption, so the driver should clamp nr_rings to 1). However the
gpu->revn is not yet set (it is set later, in adreno_gpu_init()) and
thus the condition is always false. Check config->rev instead.
Fixes: 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno 510") Reported-by: Adam Skladowski <a39.skl@gmail.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Adam Skladowski <a39.skl@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/531511/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Mon, 17 Apr 2023 22:55:10 +0000 (15:55 -0700)]
drm/msm: Move cmdstream dumping out of sched kthread
This is something that can block for arbitrary amounts of time as
userspace consumes from the FIFO. So we don't really want this to
be in the fence signaling path.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/532617/
drm/msm/a6xx: don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU
If the Adreno SMMU is dma-coherent, allocation will fail unless we
disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
coherent SMMUs (like we have on sm8350 platform).
Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes") Reported-by: David Heidelberg <david@ixit.cz> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM8450 HDK
Patchwork: https://patchwork.freedesktop.org/patch/531562/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Dmitry Baryshkov [Wed, 29 Mar 2023 00:55:29 +0000 (03:55 +0300)]
drm/msm: drop unused ring variable in msm_ioctl_gem_submit()
The variable ring is not used by msm_parse_deps() and
msm_ioctl_gem_submit() and thus can be dropped.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/529340/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Sparse reports plenty of warnings against the a6xx code because of
a6xx_gmu::mmio and a6xx_gmu::rscc members. For some reason they were
defined as __iomem pointers rather than pointers to __iomem memory.
Correct the __iomem attribute.
Fixes: 02ef80c54e7c ("drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650") Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304070550.NrbhJCvP-lkp@intel.com/ Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/531583/ Signed-off-by: Rob Clark <robdclark@chromium.org>
DPU:
- Added support for DPU on sm6350 and sm6375 platforms
- Implemented tearcheck support to support vsync on SM150 and newer platforms
- Enabled missing features (DSPP, DSC, split display) on sc8180x, sc8280xp, sm8450
- Enabled writeback on sc7280
- Enabled DSC on msm8998
- Native HDMI output support
- Dropped unused features: regdma, GC, IGC
- Fixed the DSC flush operations
- Simplified QoS handling, removing obsolete and unused features and merging
SSPP and WB code paths
- Reworked dpu_encoder initialisation path
DSI:
- Added support for DSI and 28nm DSI PHY on MSM8226 platform
- Added support for DSI on sm6350 and sm6375 platforms
- Dropped powerup quirks in favour of using pre_enable_prev_first for
downstream bridges
- Fixed 14nm DSI PHY programming
MDP5:
- Added support for display controller on MSM8226 platform
Dave Airlie [Fri, 9 Jun 2023 06:43:35 +0000 (16:43 +1000)]
Merge tag 'drm-intel-gt-next-2023-06-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
UAPI Changes:
- I915_GEM_CREATE_EXT_SET_PAT for Mesa on Meteorlake.
Driver Changes:
Fixes/improvements/new stuff:
- Use large rings for compute contexts (Chris Wilson)
- Better logging/debug of unexpected GuC communication issues (Michal Wajdeczko)
- Clear out entire reports after reading if not power of 2 size (Ashutosh Dixit)
- Limit lmem allocation size to succeed on SmallBars (Andrzej Hajda)
- perf/OA capture robustness improvements on DG2 (Umesh Nerlige Ramappa)
- Fix error code in intel_gsc_uc_heci_cmd_submit_nonpriv() (Dan Carpenter)
Future platform enablement:
- Add workaround 14016712196 (Tejas Upadhyay)
- HuC loading for MTL (Daniele Ceraolo Spurio)
- Allow user to set cache at BO creation (Fei Yang)
Miscellaneous:
- Use system include style for drm headers (Jani Nikula)
- Drop legacy CTB definitions (Michal Wajdeczko)
- Turn off the timer to sample frequencies when GT is parked (Ashutosh Dixit)
- Make PMU sample array two-dimensional (Ashutosh Dixit)
- Use the correct error value when kernel_context() fails (Andi Shyti)
- Fix second parameter type of pre-gen8 pte_encode callbacks (Nathan Chancellor)
- Fix parameter in gmch_ggtt_insert_{entries, page}() (Nathan Chancellor)
- Fix size_t format specifier in gsccs_send_message() (Nathan Chancellor)
- Use the fdinfo helper (Tvrtko Ursulin)
- Add some missing error propagation (Tvrtko Ursulin)
- Reduce I915_MAX_GT to 2 (Matt Atwood)
- Rename I915_PMU_MAX_GTS to I915_PMU_MAX_GT (Matt Atwood)
- Remove some obsolete definitions (John Harrison)
Merges:
- Merge drm/drm-next into drm-intel-gt-next (Tvrtko Ursulin)
Dave Airlie [Fri, 9 Jun 2023 01:46:10 +0000 (11:46 +1000)]
Merge tag 'drm-intel-next-2023-06-05' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 features for v6.5:
Features and functionality:
- Meteorlake (MTL) display enabling (Mika, Radhakrishna, José, Ankit, Clint,
Gustavo, Imre, Anusha, Juha-Pekka, Matt)
- Allow VRR to be toggled during fastsets (Ville)
- Allow arbitrary refresh rates with VRR eDP panels (Ville)
- Support async flips on linear buffers on display ver 12+ (Arun)
- New debugfs for display clock frequencies (Bhanuprakash)
- Taint kernel when force probing unsupported devices (Jani)
- Expose CRTC CTM property on ILK/SNB/VLV (Ville)
DRM subsystem changes:
- EDID changes to support further conversion to struct drm_edid (Jani)
- Move i915 DSC parameter code to common DRM helpers (Dmitry Baryshkov)
Refactoring and cleanups:
- CSC color refactoring (Ville)
- VRR cleanups (Ville)
- Finish i915 conversion to struct drm_edid (Jani)
- Start high level display driver file (Jani)
- Hotplug refactoring (Ville)
- Misc display refactoring and cleanups (Jani, Ville)
- Use device based logging for state checker warnings (Jani)
- Split out hotplug and display irq handling (Jani)
- Move display device info and probe under display/ (Matt)
- HDCP cleanups (Suraj)
- Use localized warning ignores instead of per file (Jani)
- Remove superfluous enum i915_drm_suspend_mode (Maarten)
- PSR, pfit, scaler and chicken register definition cleanups (Ville)
- Constify pointers to hwmon_channel_info (Krzysztof Kozlowski)
- Replace all non-returning strlcpy with strscpy (Azeem Shaikh)
- Refactor VBT aux channel and DDC pin mapping (Ville)
- Include cleanups (Jani)
Fixes:
- Fix modeset locking issue in DP MST HDCP (Suraj)
- Fix disconnected Type-C/DP-alt disable at probe (Imre)
- Fix HDMI PCON DSC usage and color conversions (Ankit)
- Fix g4x HDMI infoframe/audio transmission port usage (Ville)
- Avoid use-after-free when DP connector init fails (Maarten)
- Fix voltage level for 480 MHz CDCLK (Chaitanya)
- Check HPD live state during eDP probe (Ville)
- Fix active port PLL selection for secondary MST streams (Imre)
- Check pipe source size when using SKL+ scalers (Ville)
- Fix MIPI DSI sleep sequences (Hans de Goede)
- Fix DPCD register write order to match 128b/132b requirement (Arun)
- Increase AUX timeout for Type-C (Suraj)
- Communicate display power demands to pcode (Stan)
- Fix potential division by zero in DSC compute config (Nikita Zhandarovich)
- Fix fast wake AUX sync length (Jouni)
- Fix potential oops on intel_get_crtc_new_encoder() (Ville)
* meson
* Add support for MIPI DSI displays; plus fixes and DT bindings
* panel
* Add Support for Rocktech RK043FN48H; plus DT bindings
* Add support for Starry himax83102-j02; plus DT bindings
* Add support for Starry ili9882t; plus DT bindings
Dave Airlie [Fri, 9 Jun 2023 01:30:37 +0000 (11:30 +1000)]
Merge tag 'drm-habanalabs-next-2023-06-08' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into drm-next
This tag contains additional habanalabs driver changes for v6.5:
- uAPI changes:
- Return 0 when user queries if there was a h/w or f/w error and no such error happened.
Previously we returned an error in such case.
- New features and improvements:
- Add pci health check when we lose connection with the firmware. This can be used to
distinguish between pci link down and firmware getting stuck.
- Add more info to the error print when TPC interrupt occur.
- Reduce amount of code under mutex in the command submission of signal event.
- Firmware related fixes:
- Fixes to the handshake protocol during f/w initialization.
- Display information that the f/w sends us when encountering a DMA error.
- Do soft-reset using a message sent to firmware instead of writing to MMIO.
- Prepare generic code to extract f/w version numbers.
- Bug fixes and code cleanups. Notable fixes are:
- Unsecure certain TPC registers that the user should access.
- Fix handling of QMAN errors
- Fix memory leak when recording errors (to later pass them to the user)
- Multiple fixes to razwi interrupt handling code
projects / users / jedix / linux-maple.git / log