Nicolas Pitre [Sat, 3 Sep 2011 02:26:55 +0000 (22:26 -0400)]
ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
Given that we want the default to not have any <mach/memory.h> and given
that there are now fewer cases where it is still provided than the cases
where it is not at this point, this makes sense to invert the logic and
just identify the exception cases.
The word "need" instead of "have" was chosen to construct the config
symbol so not to suggest that having a mach/memory.h file is actually
a feature that one should aim for.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
This is later used to construct the search path for:
The compiler would be looking into mach-s3c2410 and picking up this
version first. Any config that was actually expecting the mach-s3c2400
version was therefore producing a broken kernel binary. Not relying on
any of them anymore would fix that issue.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Will Deacon [Fri, 7 Oct 2011 14:57:55 +0000 (15:57 +0100)]
ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores
ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.
Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Nicolas Pitre [Wed, 6 Jul 2011 02:52:51 +0000 (22:52 -0400)]
ARM: prepare for removal of a bunch of <mach/memory.h> files
When the CONFIG_NO_MACH_MEMORY_H symbol is selected by a particular
machine class, the machine specific memory.h include file is no longer
used and can be removed. In that case the equivalent information can
be obtained dynamically at runtime by enabling CONFIG_ARM_PATCH_PHYS_VIRT
or by specifying the physical memory address at kernel configuration time.
If/when all instances of mach/memory.h are removed then this symbol could
be removed.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Nicolas Pitre [Thu, 1 Sep 2011 04:48:04 +0000 (00:48 -0400)]
ARM: mach-omap2: clean up debug-macro.S
This achieves two goals:
1) Get rid of omap_uart_v2p() and omap_uart_p2v() which were the last users
of PLAT_PHYS_OFFSET.
2) Remove the probing of the M bit in the CP15 control reg and make
the access to the .data variables completely position independent.
There is a catch though: the busyuart macro needs to know where the LSR
register is which might be at a different offset depending on the hardware.
Given that this macro is given only two registers and that one of them
must be preserved, the trick is to always pass the LSR register address
around, and deduce the base address for the THR register by masking out
the LSR offset in senduart instead.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
Nicolas Pitre [Thu, 1 Sep 2011 02:55:46 +0000 (22:55 -0400)]
ARM: add an extra temp register to the low level debugging addruart macro
Some platforms (like OMAP not to name it) are doing rather complicated
hacks just to determine the base UART address to use. Let's give their
addruart macro some slack by providing an extra work register which will
allow for much needed cleanups.
This is basically a no-op as this commit is only adding the extra argument
to the macro but no one is using it yet.
Signed-off-by: nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Kevin Hilman <khilman@ti.com>
Santosh Shilimkar [Tue, 28 Jun 2011 19:42:56 +0000 (12:42 -0700)]
ARM: mm: Add strongly ordered descriptor support.
On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.
On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.
Colin Cross [Thu, 10 Feb 2011 20:54:10 +0000 (12:54 -0800)]
ARM: gic: Use cpu pm notifiers to save gic state
When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.
Original-author: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Colin Cross [Fri, 22 Jul 2011 21:57:09 +0000 (14:57 -0700)]
cpu_pm: call notifiers during suspend
Implements syscore_ops in cpu_pm to call the cpu and
cpu cluster notifiers during suspend and resume,
allowing drivers receiving the notifications to
avoid implementing syscore_ops.
Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Colin Cross [Thu, 10 Feb 2011 10:04:45 +0000 (02:04 -0800)]
cpu_pm: Add cpu power management notifiers
During some CPU power modes entered during idle, hotplug and
suspend, peripherals located in the CPU power domain, such as
the GIC, localtimers, and VFP, may be powered down. Add a
notifier chain that allows drivers for those peripherals to
be notified before and after they may be reset.
Notified drivers can include VFP co-processor, interrupt controller
and it's PM extensions, local CPU timers context save/restore which
shouldn't be interrupted. Hence CPU PM event APIs must be called
with interrupts disabled.
Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Russell King [Thu, 1 Sep 2011 10:57:59 +0000 (11:57 +0100)]
ARM: pm: add L2 cache cleaning for suspend
We need to ensure that state is pushed out from the L2 cache when
suspending so that the resume paths can access their data before the
MMU and caches have been re-initialized. Add the necessary calls to
__cpu_suspend_save().
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 1 Sep 2011 10:52:33 +0000 (11:52 +0100)]
ARM: pm: convert some assembly to C
Convert some of the sleep.S guts to C code, which makes it easier to
use our macros and to add L2 cache handling. We provide a helper
function, __cpu_suspend_save(), which deals with saving the common
state, setting up for resume, and flushing caches.
The remainder left as assembly code is the saving of the CPU general
purpose registers, and allocating space on the stack to save the CPU
specific registers and resume state.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 31 Aug 2011 22:26:18 +0000 (23:26 +0100)]
ARM: pm: get rid of cpu_resume_turn_mmu_on
We don't require cpu_resume_turn_mmu_on as we can combine the ldr
instruction with the following code provided we ensure that
cpu_resume_mmu is aligned for older CPUs. Note that we also align
to a 32-byte boundary to ensure that the code can't cross a section
boundary.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 28 Aug 2011 09:30:34 +0000 (10:30 +0100)]
ARM: pm: no need to save/restore context ID register
There is no need to save and restore the context ID register on ARMv6
and ARMv7 with a temporary page table as we write the context ID
register when we switch back to the real page tables for the thread.
Moreover, the temporary page tables do not contain any non-global
mappings, so the context ID value should not be used. To be safe,
initialize the register to a reserved context ID value.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 27 Aug 2011 21:39:09 +0000 (22:39 +0100)]
ARM: pm: only use preallocated page table during resume
Only use the preallocated page table during the resume, not while
suspending. This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 26 Aug 2011 19:28:52 +0000 (20:28 +0100)]
ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU
enable code. This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Jon Medhurst [Sun, 28 Aug 2011 15:44:30 +0000 (16:44 +0100)]
ARM: kprobes: Add some benchmarking to test module
These benchmarks show the basic speed of kprobes and verify the success
of optimisations done to the emulation of typical function entry
instructions (i.e. push/stmdb).
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Jon Medhurst [Sun, 28 Aug 2011 15:18:43 +0000 (16:18 +0100)]
ARM: kprobes: Framework for instruction set test cases
On ARM we have to simulate/emulate CPU instructions in order to
singlestep them. This patch adds a framework which can be used to
construct test cases for different instruction forms. It is described in
detail in the in-source comments of kprobes-test.c
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Jon Medhurst [Sun, 28 Aug 2011 15:02:38 +0000 (16:02 +0100)]
ARM: kprobes: Add basic API tests
These test that the different kinds of probes can be successfully placed
into ARM and Thumb code and that the handlers are called correctly when
this code is executed.
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Nicolas Pitre [Wed, 14 Sep 2011 04:16:21 +0000 (00:16 -0400)]
ARM: zImage: prevent constant copy+rebuild of lib1funcs.S
The rule to copy this file doesn't have to be forced. However
lib1funcs.[So] have to be listed amongst the targets.
This prevents zImage from being recreated needlessly.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Nicolas Pitre [Wed, 14 Sep 2011 02:37:07 +0000 (22:37 -0400)]
ARM: zImage: allow supplementing appended DTB with traditional ATAG data
Some old bootloaders can't be updated to a device tree capable one,
yet they provide ATAGs with memory configuration, the ramdisk address,
the kernel cmdline string, etc. To allow a device tree enabled
kernel to be used with such bootloaders, it is necessary to convert those
ATAGs into FDT properties and fold them into the DTB appended to zImage.
Currently the following ATAGs are converted:
ATAG_CMDLINE
ATAG_MEM
ATAG_INITRD2
If the corresponding information already exists in the appended DTB, it
is replaced, otherwise the required node is created to hold it.
The code looks for ATAGs at the location pointed by the value of r2 upon
entry into the zImage code. If no ATAGs are found there, an attempt at
finding ATAGs at the typical 0x100 offset from start of RAM is made.
Otherwise the DTB is left unchanged.
Thisstarted from an older patch from John Bonesio <bones@secretlab.ca>,
with contributions from David Brown <davidb@codeaurora.org>.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Nicolas Pitre [Wed, 14 Sep 2011 01:42:55 +0000 (21:42 -0400)]
ARM: zImage: gather some string functions into string.c
This is a small subset of string functions needed by commits to come.
Except for memcpy() which is unchanged from its original location, their
implementation is meant to be small, and -Os is enforced to prevent gcc
from doing pointless loop unrolling.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Nicolas Pitre [Sun, 12 Jun 2011 05:07:33 +0000 (01:07 -0400)]
ARM: zImage: make sure appended DTB doesn't get overwritten by kernel .bss
The appended DTB gets relocated with the decompressor code to get out
of the way of the decompressed kernel. However the kernel's .bss section
may be larger than the relocated code and data, and then the DTB gets
overwritten. Let's make sure the relocation takes care of moving zImage
far enough so no such conflict with .bss occurs.
Thanks to Tony Lindgren <tony@atomide.com> for figuring out this issue.
While at it, let's clean up the code a bit so that the wont_overwrite
symbol is used while determining if a conflict exists, making the above
change more precise as well as eliminating some ARM/THUMB alternates.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
John Bonesio [Fri, 27 May 2011 22:45:50 +0000 (18:45 -0400)]
ARM: zImage: Allow the appending of a device tree binary
This patch provides the ability to boot using a device tree that is appended
to the raw binary zImage (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
Signed-off-by: John Bonesio <bones@secretlab.ca>
[nico: ported to latest zImage changes plus additional cleanups/improvements] Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Nicolas Pitre [Sat, 28 May 2011 02:25:26 +0000 (22:25 -0400)]
ARM: zImage: ensure it is always a multiple of 64 bits in size
This is needed for proper alignment when the DTB appending feature
is used.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm: Remove duplicate "return" statement
drm/nv04/crtc: Bail out if FB is not bound to crtc
drm/nouveau: fix nv04_sgdma_bind on non-"4kB pages" archs
drm/nouveau: properly handle allocation failure in nouveau_sgdma_populate
drm/nouveau: fix oops on pre-semaphore hardware
drm/nv50/crtc: Bail out if FB is not bound to crtc
drm/radeon/kms: fix DP detect and EDID fetch for DP bridges
Merge branch 'fixes' of git://git.linaro.org/people/arnd/arm-soc
* 'fixes' of git://git.linaro.org/people/arnd/arm-soc:
ARM: CSR: add missing sentinels to of_device_id tables
ARM: cns3xxx: Fix newly introduced warnings in the PCIe code
ARM: cns3xxx: Fix compile error caused by hardware.h removed
ARM: davinci: fix cache flush build error
ARM: davinci: correct MDSTAT_STATE_MASK
ARM: davinci: da850 EVM: read mac address from SPI flash
OMAP: omap_device: fix !CONFIG_SUSPEND case in _noirq handlers
OMAP2430: hwmod: musb: add missing terminator to omap2430_usbhsotg_addrs[]
OMAP3: clock: indicate that gpt12_fck and wdt1_fck are in the WKUP clockdomain
OMAP4: clock: fix compile warning
OMAP4: clock: re-enable previous clockdomain enable/disable sequence
OMAP: clockdomain: Wait for powerdomain to be ON when using clockdomain force wakeup
OMAP: powerdomains: Make all powerdomain target states as ON at init
The LTTng 2.0 kernel tracer (stand-alone module package, available at
http://lttng.org) uses the 0xF6 ioctl range for tracer control and
transport operations.
Merge branch 'for-linus' of git://github.com/chrismason/linux
* 'for-linus' of git://github.com/chrismason/linux:
Btrfs: add dummy extent if dst offset excceeds file end in
Btrfs: calc file extent num_bytes correctly in file clone
btrfs: xattr: fix attribute removal
Btrfs: fix wrong nbytes information of the inode
Btrfs: fix the file extent gap when doing direct IO
Btrfs: fix unclosed transaction handle in btrfs_cont_expand
Btrfs: fix misuse of trans block rsv
Btrfs: reset to appropriate block rsv after orphan operations
Btrfs: skip locking if searching the commit root in csum lookup
btrfs: fix warning in iput for bad-inode
Btrfs: fix an oops when deleting snapshots
If we write some data into the data hole of the file(no preallocation for this
hole), Btrfs will allocate some disk space, and update nbytes of the inode, but
the other element--disk_i_size needn't be updated. At this condition, we must
update inode metadata though disk_i_size is not changed(btrfs_ordered_update_i_size()
return 1).
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