Olof Johansson [Sun, 13 Mar 2016 01:05:27 +0000 (17:05 -0800)]
Merge tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.6 (part 2)
Add support for the Armada 7K and 8K SoCs and the Armada 8040 DB board
* tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
arm64: dts: marvell: update Armada AP806 clock description
arm64: dts: marvell: add Device Tree files for Armada 7K/8K
Arnd Bergmann [Wed, 2 Mar 2016 21:28:30 +0000 (22:28 +0100)]
Merge tag 'qcom-arm64-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64
Merge "Qualcomm ARM64 Updates for v4.6" from Andy Gross:
* Add MSM8996 support
* Cleanups for MSM8916
* Updates for APQ8016 SBC
* Fixup pmic reg properties
* Add RPMCC node for 8916
* Add LPASS audio nodes
* Add USB support on MSM8916
* tag 'qcom-arm64-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (24 commits)
arm64: dts: qcom: Fix MPP's function used for LED control
arm64: dts: qcom: fix usb digital voltage levels
arm64: dts: qcom: apq8016-sbc: enable lpass on DB410c
arm64: dts: qcom: add lpass node
arm64: dts: qcom: add audio pinctrls
arm64: dts: qcom: apq8016-sbc: add usb support
arm64: dts: qcom: add manual pullup setting to otg.
arm64: dts: qcom: msm8916: Add RPMCC DT node
ARM64: dts: qcom: Remove size elements from pmic reg properties
arm64: dts: msm8996: Add #power-domain-cells property
arm64: dts: apq8016-sbc: Add real regulators and pinctrl for sdhc
arm64: dts: apq8016-sbc: move sdhci node under soc node
arm64: dts: apq8016-sbc: make 1.8v available on LS expansion
arm64: dts: apq8016-sbc: add regulators support
arm64: dts: qcom: add lable for smd rpm regulators
arm64: dts: remove s2 regulator from smd regulators.
arm64: dts: qcom: add correct drive strenght on cs pins
arm64: dts: qcom: remove redundant spi cs pins from pinconf
arm64: dts: apq8016-sbc: Add aliases to spi device.
arm64: dts: Add L2 cache node to msm8916
...
Arnd Bergmann [Mon, 29 Feb 2016 23:36:51 +0000 (00:36 +0100)]
Merge tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64
Merge "First part of X-Gene DT changes queued for v4.6" from Duc Dang:
This patch set includes:
+ A change in compatible string of X-Gene v2 SoC
PLL DT node to reflect the v2 hardware
+ Update DT fields for X-Gene v1 and v2 standby
GPIO controllers
+ Update declaration of power button GPIO for
X-Gene v1 and X-Gene v2 platforms
* tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next:
arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
arm64: dts: apm: Update X-Gene standby GPIO controller DTS entries
arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardware
Arnd Bergmann [Mon, 29 Feb 2016 23:22:23 +0000 (00:22 +0100)]
Merge tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi into next/dt64
Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu:
- Add L2 cache topology
- Use Cortex specific device node for pmu
- Append all gicv3 ITS entries
- Append gpio nodes
- Append power button node for D02 board
* tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hip05: Append power button node for D02 board
arm64: dts: hip05: Append gpio nodes
arm64: dts: hip05: Append all gicv3 ITS entries
arm64: dts: hip05: Use Cortex specific device node for pmu
arm64: dts: hip05: Add L2 cache topology
Arnd Bergmann [Fri, 26 Feb 2016 21:51:16 +0000 (22:51 +0100)]
Merge tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/dt64
Merge "ARM: Xilinx ZynqMP dt patches for v4.6" from Michal Simek:
- Extract clock information from EP108
- Sort GPIO node
* tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx:
ARM64: zynqmp: Extract clock information from EP108
ARM64: zynqmp: Keep gpio node alphabetically sorted
Thomas Petazzoni [Wed, 24 Feb 2016 15:16:47 +0000 (16:16 +0100)]
arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
The DT nodes representing the XOR engines were not placed at the
proper location to comply with the requirement of ordering DT nodes by
their unit address. This commit fixes this mistake.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thomas Petazzoni [Wed, 24 Feb 2016 15:16:46 +0000 (16:16 +0100)]
arm64: dts: marvell: update Armada AP806 clock description
Following the review from the DT maintainers, the DT binding for the
clocks has changed, and we now use a DFX server node exposing a
syscon, with the clock nodes being subnodes of the DFX server
node. This commit therefore updates the AP806 Device Tree file to use
this new DT binding.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thomas Petazzoni [Thu, 18 Feb 2016 16:20:30 +0000 (17:20 +0100)]
arm64: dts: marvell: add Device Tree files for Armada 7K/8K
This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.
The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:
- An AP806 block that contains the CPU core and a few basic
peripherals. The AP806 is available in dual core configurations
(used in 7020 and 8020) and quad core configurations (used in 8020
and 8040).
- One or two CP110 blocks that contain all the high-speed interfaces
(SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
and the 8K family chips have two CP110, giving them twice the
number of HW interfaces.
In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:
* armada-ap806.dtsi - definitions common to dual/quad ap806
* armada-ap806-dual.dtsi - description of the two CPUs
* armada-7020.dtsi - description of the 7020 SoC
* armada-8020.dtsi - description of the 8020 SoC
* armada-ap806-quad.dtsi - description of the four CPUs
* armada-7040.dtsi - description of the 7040 SoC
* armada-7040-db.dts - description of the 7040 board
* armada-8040.dtsi - description of the 8040 SoC
The CP110 blocks are not described yet, and will be part of future
patch series.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Duc Dang [Thu, 25 Feb 2016 21:52:52 +0000 (13:52 -0800)]
arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
This patch updates gpio-keys node that supports power-off for
X-Gene v2 Merlin board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: Quan Nguyen <qnguyen@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com>
xgene-gpio-sb driver now supports configuring some GPIO pins
as interrupt pins. This patch adds the required fields for GPIO
standby controller DT node of X-Gene v2 platform to work with
this new driver change.
Signed-off-by: Quan Nguyen <qnguyen@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com>
Duc Dang [Thu, 25 Feb 2016 15:56:27 +0000 (07:56 -0800)]
arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
This patch updates gpio-keys node that supports power-off for
X-Gene v1 Mustang board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Yoshihiro Shimoda [Tue, 23 Feb 2016 12:28:34 +0000 (21:28 +0900)]
arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
This board has a MAX3355 chip. However, we cannot use the extcon/max3355
driver because the ID pin doesn't connect to a gpio pin (in other words,
it connects to the SoC specific pin).
And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now.
So, this patch enables usb2_phy of channel 1 and 2.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ai Kyuse [Mon, 15 Feb 2016 15:01:50 +0000 (16:01 +0100)]
arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3
Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support.
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ai Kyuse [Mon, 15 Feb 2016 15:01:49 +0000 (16:01 +0100)]
arm64: dts: r8a7795: Add SDHI support to dtsi
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: squashed some fixes and added mmc-caps] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Srinivas Kandagatla [Tue, 23 Feb 2016 16:50:36 +0000 (16:50 +0000)]
arm64: dts: qcom: fix usb digital voltage levels
This patch updates the digital voltage levels from corner values to
microvolts as we are going to use s1 regulator directly for vddcx
instead of s1_corner.
Srinivas Kandagatla [Tue, 23 Feb 2016 16:49:46 +0000 (16:49 +0000)]
arm64: dts: qcom: add manual pullup setting to otg.
This patch adds manual pull up setting for usb otg indicating that the
vbus is vbus is not routed to USB controller/phy therefore enables
pull-up explicitly before starting controller.
Kefeng Wang [Fri, 29 Jan 2016 08:39:01 +0000 (16:39 +0800)]
arm64: dts: hip05: Add L2 cache topology
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Olof Johansson [Thu, 25 Feb 2016 00:49:05 +0000 (16:49 -0800)]
Merge tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.6 (part 1)
Device tree part of the Armada 3700 support:
- binding for the Armada 3700 SoCs
- device tree files for the SoCs and a board
- tidy up the Marvell related files
* tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: add the Marvell Armada 3700 family and a development board
devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family
Documentation: dt: Tidy up the Marvell related files
Documentation: dt-bindings: Add a new compatible for the Armada 3700
Olof Johansson [Wed, 24 Feb 2016 21:51:45 +0000 (13:51 -0800)]
Merge tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Define the tuning-related mmc clocks and move from
gpio-key,wakeup to the more generic wakeup-source property.
* tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc
Stephen Boyd [Wed, 25 Nov 2015 22:27:37 +0000 (14:27 -0800)]
ARM64: dts: qcom: Remove size elements from pmic reg properties
The #size-cells for the pmics are 0, but we specify a size in the
reg property so that MPP and GPIO modules can figure out how many
pins there are. Now that we've done that by counting irqs, we can
remove the size elements in the reg properties and be DT
compliant.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Thu, 28 Jan 2016 17:43:54 +0000 (17:43 +0000)]
arm64: dts: qcom: add lable for smd rpm regulators
This patch adds label to smd rpm regulators so that the board level file
can use the label directly to populate the regulators, rather than
having deep nesting.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Thu, 28 Jan 2016 17:43:30 +0000 (17:43 +0000)]
arm64: dts: qcom: add correct drive strenght on cs pins
2mA drive strenght is not enough to drive chipselect low on hardware
configurations with level shifters, 16mA should give good range to
allow such configurations to work.
This issue was noticed while testing spi on db410c with sensor board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Stephen Boyd [Fri, 8 Jan 2016 23:57:09 +0000 (15:57 -0800)]
arm64: dts: Add L2 cache node to msm8916
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.
Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
MT8173 E1 chip has one bug that if turn off USB power domain, vcore
power will also be off, thus cause modules using vcore power domain
fail, like MMC. The E1 chip only found on MT8173-evb board and this
board only has E1 chip, so implement this as a board specific
workaround.
Pwrapper use vcore power, so add pwrapper using USB power domain to
keep USB power domain not to zero and disabled.
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
For the at GICH Virtual interface control blocks at 0xf1040000 cover the
whole 128kB (0x20000) range. This is done based on the advice from Marc
Zyngier http://www.spinics.net/lists/arm-kernel/msg483139.html
Gregory CLEMENT [Tue, 2 Feb 2016 17:14:06 +0000 (18:14 +0100)]
arm64: dts: add the Marvell Armada 3700 family and a development board
Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).
It also adds a dts file for the Marvell Armada 3720 DB board.
Gregory CLEMENT [Tue, 2 Feb 2016 17:13:56 +0000 (18:13 +0100)]
devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family
The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit
introduces the Device Tree binding that documents the top-level
compatible strings for Armada 3700 based platforms.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
Gregory CLEMENT [Tue, 2 Feb 2016 17:13:41 +0000 (18:13 +0100)]
Documentation: dt: Tidy up the Marvell related files
Over the last releases we have added more and more Marvell related binding
directly in the arm directory. It's time to have our proper directory
inside it, and move all the files in it.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
Rajesh Bhagat [Wed, 10 Feb 2016 05:09:47 +0000 (10:39 +0530)]
arm64: dts: ls1043a: Add quirk for Erratum A009116
Add "snps,quirk-frame-length-adjustment" property to USB3 node for
erratum A009116. This property provides value of GFLADJ_30MHZ for post
silicon frame length adjustment.
Lijun Pan [Tue, 9 Feb 2016 23:08:07 +0000 (17:08 -0600)]
arm64: dts: ls2080a: Add quirk for Erratum A009116
Add "snps,quirk-frame-length-adjustment" property to
USB3 node for erratum A009116. This property provides
value of GFLADJ_30MHZ for post silicon frame length
adjustment.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Sudeep Holla [Mon, 8 Feb 2016 21:55:12 +0000 (21:55 +0000)]
arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.
Few dts files assign value "1" to gpio-key,wakeup and in one instance a
value "0" is assigned probably assuming it won't be enabled as a wakeup
source. Since the presence of the boolean property indicates it is
enabled, value of "0" have no value.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Suravee Suthikulpanit [Mon, 8 Feb 2016 17:59:17 +0000 (11:59 -0600)]
dtb: amd: Add support for AMD/Linaro 96Boards Enterprise Edition Server board
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server
(Husky) Board. This is based on the AMD Seattle Rev.B0 system
Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
projects / users / jedix / linux-maple.git / log