Arnd Bergmann [Tue, 8 Mar 2022 16:06:44 +0000 (17:06 +0100)]
Merge tag 'amlogic-drivers-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/drivers
Amlogic Drivers updates for v5.18:
- Add support for Amlogic S4 in meson-secure-pwrc power domain driver
* tag 'amlogic-drivers-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
soc: s4: Add support for power domains controller
dt-bindings: power: add Amlogic s4 power domains bindings
Arnd Bergmann [Tue, 8 Mar 2022 15:50:17 +0000 (16:50 +0100)]
Merge tag 'memory-controller-drv-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.18, part two
1. TI: Two fixes for TI EMIF driver for quite old error path issues (so
for unlikely scenarios).
2. Renesas: Document RZ/V2L SoC in bindings.
* tag 'memory-controller-drv-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC
memory: emif: check the pointer temp in get_device_details()
memory: emif: Add check for setup_interrupts
Arnd Bergmann [Tue, 8 Mar 2022 15:49:19 +0000 (16:49 +0100)]
Merge tag 'at91-soc-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers
AT91 SoC #2 for 5.18:
- SAMA5D29 variant to the SAMA5D2 family in SoC driver.
* tag 'at91-soc-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: add support in soc driver for new SAMA5D29
soc: add microchip polarfire soc system controller
ARM: at91: Kconfig: select PM_OPP
ARM: at91: PM: add cpu idle support for sama7g5
ARM: at91: ddr: fix typo to align with datasheet naming
ARM: at91: ddr: align macro definitions
ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency
Arnd Bergmann [Mon, 7 Mar 2022 22:47:47 +0000 (23:47 +0100)]
Merge tag 'v5.17-next-soc.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
mmsys: fix compilation by adding SW reset infrastructure
* tag 'v5.17-next-soc.2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
Document RZ/V2L RPC-IF bindings. RZ/V2L RPC-IF is identical to one found
on the RZ/G2L SoC. No driver changes are required as generic compatible
string "renesas,rzg2l-rpc-if" will be used as a fallback.
While at it, drop the comment "# RZ/G2L family" for "renesas,rzg2l-rpc-if"
compatible string as this will avoid changing the line for every new SoC
addition.
Jiasheng Jiang [Thu, 24 Feb 2022 02:54:44 +0000 (10:54 +0800)]
memory: emif: Add check for setup_interrupts
As the potential failure of the devm_request_threaded_irq(),
it should be better to check the return value of the
setup_interrupts() and return error if fails.
Arnd Bergmann [Tue, 1 Mar 2022 18:24:20 +0000 (19:24 +0100)]
Merge tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.18
This refactors the Qualcomm mdt file loader, to partially decouple it
from the SCM peripheral-authentication-service. This is needed as newer
platforms, such as the Qualcomm SM8450, require the metadata to remain
accessible to TrustZone during a longer time. This is followed by the
introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).
It changes the way hardware version differences are handled in the LLCC
driver and introduces support for Qualcomm SM8450. While updating the dt
binding for LLCC it also introduces the missing SM8350 compatible.
The ocmem and aoss drivers gains missing put_device() calls and rpmpd
gains a missing check for kcalloc() failure.
The SPM driver is updated to avoid instantiating the SPM cpuidle devices
if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
operates in 32-bit mode without PSCI.
The RPM power-domain driver gains MSM8226 support.
Lastly the socinfo driver gains knowledge about a few new SoCs and
PMICs.
* tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (37 commits)
soc: qcom: rpmpd: Add MSM8226 support
dt-bindings: power: rpmpd: Add MSM8226 to rpmpd binding
soc: qcom: mdt_loader: Fix split-firmware condition
dt-bindings: arm: msm: Add LLCC compatible for SM8450
dt-bindings: arm: msm: Add LLCC compatible for SM8350
soc: qcom: llcc: Add configuration data for SM8450 SoC
soc: qcom: llcc: Update register offsets for newer LLCC HW
soc: qcom: llcc: Add missing llcc configuration data
soc: qcom: llcc: Add write-cache cacheable support
soc: qcom: llcc: Update the logic for version info extraction
soc: qcom: llcc: Add support for 16 ways of allocation
soc: qcom: socinfo: Add some more PMICs and SoCs
firmware: qcom: scm: Add support for MC boot address API
firmware: qcom: scm: Drop cpumask parameter from set_boot_addr()
firmware: qcom: scm: Simplify set_cold/warm_boot_addr()
cpuidle: qcom-spm: Check if any CPU is managed by SPM
remoteproc: qcom: pas: Add SM8450 remoteproc support
dt-bindings: remoteproc: qcom: pas: Add SM8450 PAS compatibles
remoteproc: qcom: pas: Carry PAS metadata context
soc: qcom: mdt_loader: Extract PAS operations
...
Arnd Bergmann [Tue, 1 Mar 2022 10:09:41 +0000 (11:09 +0100)]
Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
- add power domains support for mt8195
- disable ACP on mt8192
mt8186:
- add support for power domains
- add mmsys and mutex support needed for DRM
- add reset control based on mmsys subsystem
- add pmic wrapper
* tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
dt-bindings: arm: mediatek: mmsys: add support for MT8186
dt-bindings: mediatek: add compatible for MT8186 pwrap
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
soc: mediatek: mmsys: add mmsys reset control for MT8186
soc: mediatek: mtk-infracfg: Disable ACP on MT8192
soc: mediatek: add MTK mutex support for MT8186
soc: mediatek: mmsys: add mt8186 mmsys routing table
soc: mediatek: pm-domains: Add support for mt8186
dt-bindings: power: Add MT8186 power domains
soc: mediatek: pm-domains: Add support for mt8195
soc: mediatek: pm-domains: Move power status offset to power domain data
soc: mediatek: pm-domains: Remove unused macro
soc: mediatek: pm-domains: Add wakeup capacity support in power domain
dt-bindings: power: Add MT8195 power domains
Arnd Bergmann [Tue, 1 Mar 2022 09:52:27 +0000 (10:52 +0100)]
Merge tag 'memory-controller-drv-mediatek-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.18 - Mediatek SoC
1. Several updates in the MTK SMI bindings.
2. Add support for MT8186 MTK SMI and improvements in support for MT8195.
* tag 'memory-controller-drv-mediatek-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: mtk-smi: Enable sleep ctrl safety function for MT8195
memory: mtk-smi: mt8186: Add smi support
memory: mtk-smi: Add sleep ctrl function
memory: mtk-smi: handle positive return value for clk_bulk_prepare_enable
dt-bindings: memory: mediatek: Add mt8186 support
dt-bindings: memory: mtk-smi: Correct minItems to 2 for the gals clocks
dt-bindings: memory: mtk-smi: No need mediatek,larb-id for mt8167
dt-bindings: memory: mtk-smi: Rename clock to clocks
Arnd Bergmann [Tue, 1 Mar 2022 09:47:13 +0000 (10:47 +0100)]
Merge tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.18
1. Minor improvements: Mediatek SMI, Freescale/NXP IFC, Tegra20 and
Tegra30.
2. Convert Freescale/NXP IFC bindings to dtschema.
3. Convert LPDDR bindings to dtschema.
4. Adjust revision ID property in LPDDR2 bindings to match LPDDR3
bindings.
* tag 'memory-controller-drv-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: Update of_memory lpddr2 revision-id binding
dt-bindings: memory: lpddr2: Adjust revision ID property to match lpddr3
memory: of: parse max-freq property
dt-bindings: memory: lpddr3: deprecate passing timings frequency as unit address
dt-bindings: memory: lpddr3: deprecate manufacturer ID
dt-bindings: memory: lpddr3: adjust IO width to spec
dt-bindings: memory: lpddr3: convert to dtschema
dt-bindings: memory: lpddr3-timings: convert to dtschema
dt-bindings: memory: lpddr2-timings: convert to dtschema
memory: brcmstb_dpfe: fix typo in a comment
memory: fsl_ifc: populate child devices without relying on simple-bus
dt-bindings: memory: fsl: convert ifc binding to yaml schema
memory: mtk-smi: Use ARRAY_SIZE to define MTK_SMI_CLK_NR_MAX
Johnson Wang [Mon, 7 Feb 2022 08:30:34 +0000 (16:30 +0800)]
dt-bindings: mediatek: add compatible for MT8186 pwrap
This adds dt-binding documentation of pwrap for Mediatek MT8186
SoCs Platform.
Acked-by: Rob Herring <robh@kernel.org> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-3-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Alyssa Rosenzweig [Tue, 15 Feb 2022 18:46:51 +0000 (13:46 -0500)]
soc: mediatek: mtk-infracfg: Disable ACP on MT8192
MT8192 contains an experimental Accelerator Coherency Port
implementation, which does not work correctly but was unintentionally
enabled by default. For correct operation of the GPU, we must set a
chicken bit disabling ACP on MT8192.
Adapted from the following downstream change to the out-of-tree, legacy
Mali GPU driver:
Note this change is required for both Panfrost and the legacy kernel
driver.
Co-developed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Cc: Nick Fan <Nick.Fan@mediatek.com> Cc: Nicolas Boichat <drinkcat@chromium.org> Cc: Chen-Yu Tsai <wenst@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Arnd Bergmann [Mon, 28 Feb 2022 12:38:51 +0000 (13:38 +0100)]
Merge tag 'ti-driver-soc-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers
TI Driver updates for v5.18
* Fixups for k3-ringacc, smartreflex, tisci, wkup_m3_ipc
* Device detection for am62x.
* tag 'ti-driver-soc-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
soc: ti: k3-socinfo: Add AM62x JTAG ID
soc: ti: wkup_m3_ipc: Fix IRQ check in wkup_m3_ipc_probe
firmware: ti_sci: inproper error handling of ti_sci_probe
firmware: ti_sci: Fix compilation failure when CONFIG_TI_SCI_PROTOCOL is not defined
soc: ti: smartreflex: Use platform_get_irq_optional() to get the interrupt
soc: ti: k3-ringacc: Use devm_bitmap_zalloc() when applicable
Arnd Bergmann [Mon, 28 Feb 2022 12:37:06 +0000 (13:37 +0100)]
Merge tag 'tegra-for-5.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.18-rc1
This contains the final bit to enable advanced power management on
Tegra20 and Tegra30. It also contains some cleanups and wake event
support on Tegra234.
* tag 'tegra-for-5.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: bpmp: cleanup double word in comment
soc/tegra: pmc: Add Tegra234 wake events
soc/tegra: fuse: Explicitly cast to/from __iomem
soc/tegra: fuse: Update nvmem cell list
soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30
Yongqiang Niu [Tue, 22 Feb 2022 05:28:02 +0000 (13:28 +0800)]
soc: mediatek: add MTK mutex support for MT8186
Add MTK mutex support for MT8186 SoC.
We need MTK mutex to control timing of display modules and there
are two display pipelines for MT8186 including internal and external
display.
MTK mutex for internal display:
- Timing source: DSI
- Control modules: OVL0/RDMA0/COLOR0/CCORR/AAL0/GAMMA/POSTMASK0/DITHER
MTK mutex for external display:
- Timing source : DPI
- Control modules: OVL_2L0/RDMA1
Chun-Jie Chen [Sun, 30 Jan 2022 01:21:03 +0000 (09:21 +0800)]
soc: mediatek: pm-domains: Move power status offset to power domain data
MT8195 has more than 32 power domains so it needs
two set of pwr_sta and pwr_sta2nd registers,
so move the register offset from soc data into power domain data.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Chun-Jie Chen [Sun, 30 Jan 2022 01:21:02 +0000 (09:21 +0800)]
soc: mediatek: pm-domains: Remove unused macro
Due to clk resource data will be allocated dynamically by
searching parent count of clk in power domain node, so remove
the unused marco MAX_SUBSYS_CLKS for static allocation.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-4-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Arnd Bergmann [Fri, 25 Feb 2022 16:14:15 +0000 (17:14 +0100)]
Merge tag 'samsung-clk-fsd-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung clock controller changes for v5.18
Add support for Tesla FSD SoC clock controller within Samsung Exynos SoC
clock controller drivers. The Tesla FSD's clock controller is similar
to Samsung Exynos one, so entire driver structure can be re-used.
* tag 'samsung-clk-fsd-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: fix missing Tesla FSD dependency on Exynos
clk: samsung: fsd: Add cam_csi block clock information
clk: samsung: fsd: Add cmu_mfc block clock information
clk: samsung: fsd: Add cmu_imem block clock information
clk: samsung: fsd: Add cmu_fsys1 clock information
clk: samsung: fsd: Add cmu_fsys0 clock information
clk: samsung: fsd: Add cmu_peric block clock information
clk: samsung: fsd: Add initial clock support
dt-bindings: clock: Document FSD CMU bindings
dt-bindings: clock: Add bindings definitions for FSD CMU blocks
Arnd Bergmann [Fri, 25 Feb 2022 16:05:31 +0000 (17:05 +0100)]
Merge tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
Arm SCMI firmware interface updates for v5.18
Few main additions include:
- Support for OPTEE based SCMI transport to enable using SCMI service
provided by OPTEE on some platforms
- Support for atomic SCMI transports which enables few SCMI transactions
to be completed in atomic context. This involves other refactoring work
associated with it. It also marks SMC and OPTEE as atomic transport as
the commands are completed once the return.
- Support for polling mode in SCMI VirtIO transport in order to support
atomic operations
- Support for atomic clock operations based on availability of atomic
capability in the underlying SCMI transport
Other changes involves some trace and log enhancements and miscellaneous
bug fixes.
* tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (28 commits)
clk: scmi: Support atomic clock enable/disable API
firmware: arm_scmi: Add support for clock_enable_latency
firmware: arm_scmi: Add atomic support to clock protocol
firmware: arm_scmi: Support optional system wide atomic-threshold-us
dt-bindings: firmware: arm,scmi: Add atomic-threshold-us optional property
firmware: arm_scmi: Add atomic mode support to virtio transport
firmware: arm_scmi: Review virtio free_list handling
firmware: arm_scmi: Add a virtio channel refcount
firmware: arm_scmi: Disable ftrace for Clang Thumb2 builds
firmware: arm_scmi: Add new parameter to mark_txdone
firmware: arm_scmi: Add atomic mode support to smc transport
firmware: arm_scmi: Add support for atomic transports
firmware: arm_scmi: Make optee support sync_cmds_completed_on_ret
firmware: arm_scmi: Make smc support sync_cmds_completed_on_ret
firmware: arm_scmi: Add sync_cmds_completed_on_ret transport flag
firmware: arm_scmi: Make smc transport use common completions
firmware: arm_scmi: Add configurable polling mode for transports
firmware: arm_scmi: Use new trace event scmi_xfer_response_wait
include: trace: Add new scmi_xfer_response_wait event
firmware: arm_scmi: Refactor message response path
...
Arnd Bergmann [Fri, 25 Feb 2022 16:05:20 +0000 (17:05 +0100)]
Merge tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.18:
- Drop LS1021A device check from soc-imx driver as it's unneeded since
commit commit 4ebd29f91629 ("soc: imx: Register SoC device only on
i.MX boards").
- Add support for power domains provided by the VPU blk-ctrl on the
i.MX8MQ.
- Add resource owner management API which will be used to check whether
M4 is under control of Linux.
- Add VPU MU resources support into SCU power domain driver.
- Support DT overlay for WEIM bus driver with OF reconfiguration
notifier handler.
* tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
bus: imx-weim: add DT overlay support for WEIM bus
firmware: imx: scu-pd: imx8q: add vpu mu resources
firmware: imx: add get resource owner api
soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
soc: imx: Remove Layerscape check
Arnd Bergmann [Fri, 25 Feb 2022 16:05:11 +0000 (17:05 +0100)]
Merge tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers
TEE shared memory cleanup for v5.18
- The TEE shared memory pool based on two pools is replaced with a single
somewhat more capable pool.
- Replaces tee_shm_alloc() and tee_shm_register() with new functions
easier to use and maintain. The TEE subsystem and the TEE drivers are
updated to use the new functions instead.
- The TEE based Trusted keys routines are updated to use the new
simplified functions above.
- The OP-TEE based rng driver is updated to use the new simplified
functions above.
- The TEE_SHM-flags are refactored to better match their usage
* tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
tee: refactor TEE_SHM_* flags
tee: replace tee_shm_register()
KEYS: trusted: tee: use tee_shm_register_kernel_buf()
tee: add tee_shm_register_{user,kernel}_buf()
optee: add optee_pool_op_free_helper()
tee: replace tee_shm_alloc()
tee: simplify shm pool handling
tee: add tee_shm_alloc_user_buf()
tee: remove unused tee_shm_pool_alloc_res_mem()
hwrng: optee-rng: use tee_shm_alloc_kernel_buf()
optee: use driver internal tee_context for some rpc
Arnd Bergmann [Fri, 25 Feb 2022 16:04:24 +0000 (17:04 +0100)]
Merge tag 'renesas-drivers-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.18
- Initial support for the new RZ/V2L SoC,
- RZ/G2L product revision support.
* tag 'renesas-drivers-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Add support for reading product revision for RZ/G2L family
soc: renesas: Identify RZ/V2L SoC
This patch updates the code parsing the "jedec,lpddr2" device tree
binding to use the new `revision-id` property instead of the deprecated
`revision-id1` and `revision-id2` properties if available.
Julius Werner [Thu, 24 Feb 2022 00:34:19 +0000 (16:34 -0800)]
dt-bindings: memory: lpddr2: Adjust revision ID property to match lpddr3
Commit 3539a2c6c689 ("dt-bindings: memory: lpddr2: Add revision-id
properties") added the properties `revision-id1` and `revision-id2` to
the "jedec,lpddr2" binding. The "jedec,lpddr3" binding already had a
single array property `revision-id` for the same purpose. For
consistency between related memory types, this patch deprecates the
LPDDR2 properties and instead adds a property in the same style as for
LPDDR3 to that binding.
Claudiu Beznea [Thu, 13 Jan 2022 14:48:54 +0000 (16:48 +0200)]
ARM: at91: PM: add cpu idle support for sama7g5
Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
register to divide the CPU clock by 16 before switching it to idle and
use automatic self-refresh option of DDR controller.
Remove CONFIG_SOC_SAMA7 dependency to avoid having #ifdef preprocessor
directives in driver code (arch/arm/mach-at91/pm.c). This prepares the
code for next commits.
Thierry Reding [Thu, 24 Feb 2022 12:27:28 +0000 (13:27 +0100)]
soc/tegra: fuse: Explicitly cast to/from __iomem
sparse is picky about casts between different address spaces. A cast to
plain void * needs to be accompanied by a __force modifier and casting
back to void __iomem * needs to be explicit to avoid warnings.
kartik [Mon, 6 Dec 2021 11:52:45 +0000 (17:22 +0530)]
soc/tegra: fuse: Update nvmem cell list
Update tegra_fuse_cells with below entries:
- gcplex-config-fuse:
Configuration bits for GPU, used to enable/disable write protected
region used for storing GPU firmware.
- pdi0:
Unique per chip public identifier.
- pdi1:
Unique per chip public identifier.
The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP
blocks for which drivers are common. To avoid updating the Kconfig
files for drivers in common to each SoC, introduce the ARCH_RZG2L config
option.
The ARCH_RZG2L config option will be selected by the above mentioned
SoCs, and the ARCH_RZG2L config option will be used as a dependency for
the drivers in common.
While at it, move PM and PM_GENERIC_DOMAINS under the ARCH_RZG2L config
option instead of keeping it for individual SoCs.
The updated condition checking if a segment can be found in the loaded
firmware blob, or need to be loaded from a separate file, incorrectly
classifies segments that ends at the end of the loaded blob. The result
is that the mdt loader attempts to load the segment from a separate
file.
Correct the conditional to use the loaded segment instead.
Lad Prabhakar [Mon, 21 Feb 2022 22:24:50 +0000 (22:24 +0000)]
soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs
Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044
and ARCH_R9A07G054 configs. PM and PM_GENERIC_DOMAINS configs are
required for RZ/{G2L,V2L} SoC without these configs the SMARC EVK's
won't boot.
Ivan Bornyakov [Tue, 22 Feb 2022 05:20:59 +0000 (08:20 +0300)]
bus: imx-weim: add DT overlay support for WEIM bus
Add OF reconfiguration notifier handler for WEIM bus to setup Chip
Select timings on runtime creation of child devices.
However, it is not possible to load another DT overlay with conflicting
CS timings with previously loaded overlay, even if the first one is
unloaded. The reason is that there is no acces to CS timing property of
a device node being removed, thus we can't track which of configured CS
are available for re-configuration.
Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Cristian Marussi [Thu, 17 Feb 2022 13:12:34 +0000 (13:12 +0000)]
clk: scmi: Support atomic clock enable/disable API
Support also atomic enable/disable clk_ops beside the bare non-atomic one
(prepare/unprepare) when the underlying SCMI transport is configured to
support atomic transactions for synchronous commands.
Compare the SCMI system-wide configured atomic threshold latency time and
the per-clock advertised enable latency (if any) to choose whether to
provide sleeping prepare/unprepare vs atomic enable/disable.
Link: https://lore.kernel.org/r/20220217131234.50328-9-cristian.marussi@arm.com Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cristian Marussi [Thu, 17 Feb 2022 13:12:33 +0000 (13:12 +0000)]
firmware: arm_scmi: Add support for clock_enable_latency
An SCMI platform can optionally advertise an enable latency typically
associated with a specific clock resource: add support for parsing such
optional message field and export such information in the usual publicly
accessible clock descriptor.
Cristian Marussi [Thu, 17 Feb 2022 13:12:32 +0000 (13:12 +0000)]
firmware: arm_scmi: Add atomic support to clock protocol
Introduce new _atomic variant for SCMI clock protocol operations related
to enable disable operations: when an atomic operation is required the xfer
poll_completion flag is set for that transaction.
Cristian Marussi [Thu, 17 Feb 2022 13:12:31 +0000 (13:12 +0000)]
firmware: arm_scmi: Support optional system wide atomic-threshold-us
An SCMI agent can be configured system-wide with a well-defined atomic
threshold: only SCMI synchronous command whose latency has been advertised
by the SCMI platform to be lower or equal to this configured threshold will
be considered for atomic operations, when requested and if supported by the
underlying transport at all.
SCMI protocols in the platform can optionally signal to the OSPM agent
the expected execution latency for a specific resource/operation pair.
Introduce an SCMI system wide optional property to describe a global time
threshold which can be configured on a per-platform base to determine the
opportunity, or not, for an SCMI command advertised to have a higher
latency than the threshold, to be considered for atomic operations:
high-latency SCMI synchronous commands should be preferably issued in the
usual non-atomic mode.
Link: https://lore.kernel.org/r/20220217131234.50328-5-cristian.marussi@arm.com Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cristian Marussi [Thu, 17 Feb 2022 13:12:29 +0000 (13:12 +0000)]
firmware: arm_scmi: Add atomic mode support to virtio transport
Add support for .mark_txdone and .poll_done transport operations to SCMI
VirtIO transport as pre-requisites to enable atomic operations.
Add a Kernel configuration option to enable SCMI VirtIO transport polling
and atomic mode for selected SCMI transactions while leaving it default
disabled.
Link: https://lore.kernel.org/r/20220217131234.50328-4-cristian.marussi@arm.com Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Skalkin <igor.skalkin@opensynergy.com> Cc: Peter Hilber <peter.hilber@opensynergy.com> Cc: virtualization@lists.linux-foundation.org Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cristian Marussi [Thu, 17 Feb 2022 13:12:27 +0000 (13:12 +0000)]
firmware: arm_scmi: Add a virtio channel refcount
Currently SCMI VirtIO channels are marked with a ready flag and related
lock to track channel lifetime and support proper synchronization at
shutdown when virtqueues have to be stopped.
This leads to some extended spinlocked sections with IRQs off on the RX
path to keep hold of the ready flag and does not scale well especially when
SCMI VirtIO polling mode will be introduced.
Add an SCMI VirtIO channel dedicated refcount to track active users on both
the TX and the RX path and properly enforce synchronization and cleanup at
shutdown, inhibiting further usage of the channel once freed.
Link: https://lore.kernel.org/r/20220217131234.50328-2-cristian.marussi@arm.com Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Igor Skalkin <igor.skalkin@opensynergy.com> Cc: Peter Hilber <peter.hilber@opensynergy.com> Cc: virtualization@lists.linux-foundation.org Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Jens Wiklander [Fri, 4 Feb 2022 09:33:53 +0000 (10:33 +0100)]
tee: simplify shm pool handling
Replaces the shared memory pool based on two pools with a single pool.
The alloc() function pointer in struct tee_shm_pool_ops gets another
parameter, align. This makes it possible to make less than page aligned
allocations from the optional reserved shared memory pool while still
making user space allocations page aligned. With in practice unchanged
behaviour using only a single pool for bookkeeping.
The allocation algorithm in the static OP-TEE shared memory pool is
changed from best-fit to first-fit since only the latter supports an
alignment parameter. The best-fit algorithm was previously the default
choice and not a conscious one.
The optee and amdtee drivers are updated as needed to work with this
changed pool handling.
This also removes OPTEE_SHM_NUM_PRIV_PAGES which becomes obsolete with
this change as the private pages can be mixed with the payload pages.
The OP-TEE driver changes minimum alignment for argument struct from 8
bytes to 512 bytes. A typical OP-TEE private shm allocation is 224 bytes
(argument struct with 6 parameters, needed for open session). So with an
alignment of 512 well waste a bit more than 50%. Before this we had a
single page reserved for this so worst case usage compared to that would
be 3 pages instead of 1 page. However, this worst case only occurs if
there is a high pressure from multiple threads on secure world. All in
all this should scale up and down better than fixed boundaries.
Jens Wiklander [Fri, 4 Feb 2022 09:33:52 +0000 (10:33 +0100)]
tee: add tee_shm_alloc_user_buf()
Adds a new function tee_shm_alloc_user_buf() for user mode allocations,
replacing passing the flags TEE_SHM_MAPPED | TEE_SHM_DMA_BUF to
tee_shm_alloc().
Jens Wiklander [Fri, 4 Feb 2022 09:33:50 +0000 (10:33 +0100)]
hwrng: optee-rng: use tee_shm_alloc_kernel_buf()
Uses the new simplified tee_shm_alloc_kernel_buf() function instead of
the old deprecated tee_shm_alloc() function which required specific
TEE_SHM-flags.
Lucas Stach [Tue, 25 Jan 2022 17:11:19 +0000 (11:11 -0600)]
dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
This adds the defines for the power domains provided by the VPU
blk-ctrl on the i.MX8MQ.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Sai Prakash Ranjan [Fri, 28 Jan 2022 07:47:12 +0000 (13:17 +0530)]
soc: qcom: llcc: Update register offsets for newer LLCC HW
Newer LLCC HW have different register offsets for several registers,
currently of which LLCC hardware info and status are used to identify
the LLCC version information and other data. So use separate table to
keep track of these register offsets which vary by different LLCC HW
versions and eases any future addition in variations of register offsets
for newer hardware.
Sai Prakash Ranjan [Fri, 28 Jan 2022 07:47:10 +0000 (13:17 +0530)]
soc: qcom: llcc: Add write-cache cacheable support
Newer SoCs with LLCC IP version 2.1.0.0 and later support write
sub-cache cacheable feature. Use a separate llcc_slice_config member
"write_scid_cacheable_en" to identify this feature and program
LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it.
Sai Prakash Ranjan [Fri, 28 Jan 2022 07:47:09 +0000 (13:17 +0530)]
soc: qcom: llcc: Update the logic for version info extraction
LLCC HW version info is made up of major, branch, minor and echo
version bits each of which are 8bits. Several features in newer
LLCC HW are based on the full version rather than just major or
minor versions such as write-subcache enable which is applicable
for versions v2.0.0.0 and later, also upcoming write-subcache
cacheable for SM8450 SoC which is only present in versions v2.1.0.0
and later, so it makes it easier and cleaner to just directly
compare with the full version than adding additional major/branch/
minor/echo version checks. So remove the earlier major version check
and add full version check for those features.
Krzysztof Kozlowski [Sun, 6 Feb 2022 13:58:06 +0000 (14:58 +0100)]
memory: of: parse max-freq property
Passing the memory timings maximum frequency as an unit address was
a workaround and instead 'max-freq' is preferred. Look for 'max-freq'
first and then fallback to 'reg'.
Krzysztof Kozlowski [Sun, 6 Feb 2022 13:58:05 +0000 (14:58 +0100)]
dt-bindings: memory: lpddr3: deprecate passing timings frequency as unit address
The timings node maximum frequency was passed as an unit address, which
is actually a workaround. Such workaround and unit address are not
needed at all, because the device memory node (parent) can contain
multiple timing nodes without unit addresses but with suffix used for
nodenames, e.g. timings-1.
LPDDR2 bindings already use such version, so unify the LPDDR3 with them.
Krzysztof Kozlowski [Sun, 6 Feb 2022 13:58:04 +0000 (14:58 +0100)]
dt-bindings: memory: lpddr3: deprecate manufacturer ID
The memory manufacturer should be described in vendor part of
compatible, so there is no need to duplicate it in a separate property.
Similarly is done in LPDDR2 bindings.
Krzysztof Kozlowski [Sun, 6 Feb 2022 13:58:03 +0000 (14:58 +0100)]
dt-bindings: memory: lpddr3: adjust IO width to spec
According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register
Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only
16- and 32-bit IO width. Drop the unsupported others.
Ard Biesheuvel [Thu, 3 Feb 2022 08:22:01 +0000 (09:22 +0100)]
firmware: arm_scmi: Disable ftrace for Clang Thumb2 builds
The SMC calling convention designates R0-R7 as input registers in
AArch32 mode, and this conflicts with the compiler's use of R7 as a
frame pointer when building in Thumb2 mode. Generally, we don't enable
the frame pointer, and GCC happily enables the -pg profiling hooks
without them. However, Clang refuses, and errors out with the message
below:
drivers/firmware/arm_scmi/smc.c:152:2: error: write to reserved register 'R7'
arm_smccc_1_1_invoke(scmi_info->func_id, 0, 0, 0, 0, 0, 0, 0, &res);
^
include/linux/arm-smccc.h:550:4: note: expanded from macro 'arm_smccc_1_1_invoke'
arm_smccc_1_1_smc(__VA_ARGS__); \
^
Let's just disable ftrace for the compilation unit when building this
configuration.
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