Stephen Boyd [Tue, 25 Apr 2023 18:52:25 +0000 (11:52 -0700)]
Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-of:
clk: add missing of_node_put() in "assigned-clocks" property parsing
* clk-samsung:
clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
clk: samsung: Convert to platform remove callback returning void
clk: samsung: exynos5433: Extract PM support to common ARM64 layer
clk: samsung: Extract parent clock enabling to common function
clk: samsung: Extract clocks registration to common function
clk: samsung: exynos850: Add AUD and HSI main gate clocks
clk: samsung: exynos850: Implement CMU_G3D domain
clk: samsung: clk-pll: Implement pll0818x PLL type
clk: samsung: Set dev in samsung_clk_init()
clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
clk: samsung: Remove np argument from samsung_clk_init()
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
* clk-rockchip:
clk: rockchip: rk3588: make gate linked clocks critical
clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
* clk-qcom: (57 commits)
clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
clk: qcom: add the GPUCC driver for sa8775p
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
clk: qcom: Add Global Clock Controller driver for IPQ9574
dt-bindings: clock: Add ipq9574 clock and reset definitions
clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
clk: qcom: apss-ipq-pll: add support for IPQ5332
dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
...
Stephen Boyd [Tue, 25 Apr 2023 18:50:49 +0000 (11:50 -0700)]
Merge branches 'clk-starfive', 'clk-fractional' and 'clk-devmof' into clk-next
- Shrink size of clk_fractional_divider a little
- Convert various clk drivers to devm_of_clk_add_hw_provider()
* clk-starfive:
clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
clk: starfive: Avoid casting iomem pointers
MAINTAINERS: generalise StarFive clk/reset entries
reset: starfive: Add StarFive JH7110 reset driver
clk: starfive: Add StarFive JH7110 always-on clock driver
clk: starfive: Add StarFive JH7110 system clock driver
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: starfive: Extract the common JH71X0 reset code
reset: starfive: Factor out common JH71X0 reset code
reset: Create subdirectory for StarFive drivers
reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
clk: starfive: Factor out common JH7100 and JH7110 code
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
* clk-fractional:
clk: Remove mmask and nmask fields in struct clk_fractional_divider
clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider
clk: imx: Remove values for mmask and nmask in struct clk_fractional_divider
clk: Compute masks for fractional_divider clk when needed.
* clk-devmof:
clk: uniphier: Use managed `of_clk_add_hw_provider()`
clk: si5351: Use managed `of_clk_add_hw_provider()`
clk: si570: Use managed `of_clk_add_hw_provider()`
clk: si514: Use managed `of_clk_add_hw_provider()`
clk: lmk04832: Use managed `of_clk_add_hw_provider()`
clk: hsdk-pll: Use managed `of_clk_add_hw_provider()`
clk: cdce706: Use managed `of_clk_add_hw_provider()`
clk: axs10x: Use managed `of_clk_add_hw_provider()`
clk: axm5516: Use managed `of_clk_add_hw_provider()`
clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`
Stephen Boyd [Tue, 25 Apr 2023 18:50:08 +0000 (11:50 -0700)]
Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Converted most Mediatek clock drivers to struct platform_driver
- MediaTek clock drivers can be built as modules
- Mediatek MT8188 SoC clk drivers
- Clock driver for Sunplus SP7021 SoC
- Reimplement Loongson-1 clk driver with DT support
- Clk driver support for Loongson-2 SoCs
- Migrate socfpga clk driver to of_clk_add_hw_provider()
* clk-mediatek: (84 commits)
clk: mediatek: fhctl: Mark local variables static
clk: mediatek: Use right match table, include mod_devicetable
clk: mediatek: Add MT8188 adsp clock support
clk: mediatek: Add MT8188 imp i2c wrapper clock support
clk: mediatek: Add MT8188 wpesys clock support
clk: mediatek: Add MT8188 vppsys1 clock support
clk: mediatek: Add MT8188 vppsys0 clock support
clk: mediatek: Add MT8188 vencsys clock support
clk: mediatek: Add MT8188 vdosys1 clock support
clk: mediatek: Add MT8188 vdosys0 clock support
clk: mediatek: Add MT8188 vdecsys clock support
clk: mediatek: Add MT8188 mfgcfg clock support
clk: mediatek: Add MT8188 ipesys clock support
clk: mediatek: Add MT8188 imgsys clock support
clk: mediatek: Add MT8188 ccusys clock support
clk: mediatek: Add MT8188 camsys clock support
clk: mediatek: Add MT8188 infrastructure clock support
clk: mediatek: Add MT8188 peripheral clock support
clk: mediatek: Add MT8188 topckgen clock support
clk: mediatek: Add MT8188 apmixedsys clock support
...
* clk-loongson:
clk: clk-loongson2: add clock controller driver support
dt-bindings: clock: add loongson-2 boot clock index
MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
MIPS: loongson32: Update the clock initialization
clk: loongson1: Re-implement the clock driver
clk: loongson1: Remove the outdated driver
dt-bindings: clock: Add Loongson-1 clock
* clk-socfpga:
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
Stephen Boyd [Mon, 24 Apr 2023 22:18:23 +0000 (15:18 -0700)]
Merge tag 'qcom-clk-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
New drivers for Global clock controller on SM7150, IPQ9574, MSM8917 and
IPQ5332 are added. New GPU clock controllers for SM6115, SM6125, SM6375
and SA8775P are added.
The APSS IPQ PLL driver is refactored to support different PLL types,
support for the Stromer Plus PLL type is added, and support for IPQ5332
is introduced.
Helpers for settings sleep, wake and retain bits of CBCR registers are
introduced and used in some of the newly introduced GPU clock drivers.
The platform_driver remove callbacks is transitioned to remove_new, as
part of the system wide cleanup effort.
In the Display clock controller for QCM2290, the MDSS_CORE reset is
introduced and the non-existent DSI1PHY clock is removed.
IPQ4019 Global clock controller is transitioned to parent_data.
USB GDSCs in SM6375, MSM8996 and MSM8998 are changed to use retention as
disabled state, to avoid collapsing them during suspend.
The CX GDSC in the SM6375 GPU clock controller has it's disable-wait
value corrected.
QCM2290 SDCC2 src clock moves to floor_ops.
The two EMAC GDSCs are added for SC8280XP.
Relevant RCGs in the SM6115 Global clock controller are moved to use
shared_ops.
PCIe PIPE clock operations on SM8350 are updated, to ensure the mux is
parked when the parent PLL is disabled.
GDSCs are added to the SC7280 LPASS audio clock controller.
The RPM clock controller is transitioned to use the managed version of
of_clk_add_hw_provider().
Missing XO clocks are added to MSM8226 and MSM8974.
DeviceTree bindings are added for the various newly supported clock
controllers, the binding for KPSS ACC and GCC drivers are converted to
YAML and a few fixes are introduced.
* tag 'qcom-clk-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (57 commits)
clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
clk: qcom: add the GPUCC driver for sa8775p
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
clk: qcom: Add Global Clock Controller driver for IPQ9574
dt-bindings: clock: Add ipq9574 clock and reset definitions
clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
clk: qcom: apss-ipq-pll: add support for IPQ5332
dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
...
Stephen Boyd [Tue, 18 Apr 2023 19:48:39 +0000 (12:48 -0700)]
Merge tag 'v6.4-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull a couple Rockchip clk driver updates from Heiko Stübner:
Reparenting fix for the clock supplying camera modules on the rk3399
and more critical (bus-)clocks on the rk3588.
* tag 'v6.4-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3588: make gate linked clocks critical
clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
Sebastian Reichel [Mon, 3 Apr 2023 19:32:49 +0000 (21:32 +0200)]
clk: rockchip: rk3588: make gate linked clocks critical
RK3588 has a couple of hardware blocks called Native Interface Unit
(NIU) that gate the clocks to devices behind them. Effectively this
means that some clocks require two parent clocks being enabled.
Downstream implemented this by using a separate clock driver
("clk-link") for them, which enables the second clock using PM
framework.
In the upstream kernel we are currently missing support for the second
parent. The information about it is in the GATE_LINK() macro as
linkname, but that is not used. Thus the second parent clock is not
properly enabled. So far this did not really matter, since these clocks
are mostly required for the more advanced IP blocks, that are not yet
supported upstream. As this is about to change we need a fix. There
are three options available:
1. Properly implement support for having two parent clocks in the
clock framework.
2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
disabled. This wastes some power, but keeps the hack contained
within the clock driver. Going from this to the first solution
is easy once that has been implemented.
3. Enabling the extra clock in the consumer driver. This leaks some
implementation details into DT.
This patch implements the second option as an intermediate solution
until the first one is available. I used an alias for CLK_IS_CRITICAL,
so that it's easy to see which clocks are not really critical once
the clock framework supports a better way to implement this.
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
Add the compatible for the Qualcomm Graphics Clock control module present
on sa8775p platforms. It matches the generic QCom GPUCC description. Add
device-specific DT bindings defines as well.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411125910.401075-2-brgl@bgdev.pl
On SM8350 platform the PCIe PIPE clocks require additional handling to
function correctly. They are to be switched to the tcxo source before
turning PCIe GDSCs off and should be switched to PHY PIPE source once
they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops,
which provide support for this dance.
The qdsp6ss memory region is being shared by ADSP remoteproc device and
lpasscc clock device, hence causing memory conflict.
To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver,
skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and
also assign max_register value.
When this property is set, the remoteproc is used to boot the
LPASS and therefore qdsp6ss clocks would be used to bring LPASS
out of reset, hence they are directly controlled by the remoteproc.
This is a cleanup done to handle overlap of regmap of lpasscc
and adsp remoteproc blocks.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-2-quic_mohs@quicinc.com
Stephen Boyd [Thu, 13 Apr 2023 20:55:28 +0000 (13:55 -0700)]
clk: starfive: Avoid casting iomem pointers
Let's use a wrapper struct for the auxiliary_device made in
jh7110_reset_controller_register() so that we can stop casting iomem
pointers. The casts trip up tools like sparse, and make for some awkward
casts that are largely unnecessary. While we're here, change the
allocation from devm and actually free the auxiliary_device memory in
the release function. This avoids any use after free problems where the
parent device driver is unbound from the device but the
auxiliuary_device is still in use accessing devm freed memory.
clk: microchip: fix potential UAF in auxdev release callback
Similar to commit 1c11289b34ab ("peci: cpu: Fix use-after-free in
adev_release()"), the auxiliary device is not torn down in the correct
order. If auxiliary_device_add() fails, the release callback will be
called twice, resulting in a UAF. Due to timing, the auxdev code in this
driver "took inspiration" from the aforementioned commit, and thus its
bugs too!
Moving auxiliary_device_uninit() to the unregister callback instead
avoids the issue.
Tom Rix [Thu, 6 Apr 2023 01:09:35 +0000 (21:09 -0400)]
clk: mediatek: fhctl: Mark local variables static
smatch reports
drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol
'fhctl_offset_v1' was not declared. Should it be static?
drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol
'fhctl_offset_v2' was not declared. Should it be static?
These variables are only used in one file so should be static.
clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert the SiFive clk
drivers to use the new symbol.
clk: si514: Use managed `of_clk_add_hw_provider()`
Use the managed `devm_of_clk_add_hw_provider()` instead of
`of_clk_add_hw_provider()`. This makes sure the provider gets automatically
removed on unbind and allows to completely eliminate the drivers `remove()`
callback.
clk: axs10x: Use managed `of_clk_add_hw_provider()`
Use the managed `devm_of_clk_add_hw_provider()` instead of
`of_clk_add_hw_provider()`. This makes sure the provider gets automatically
removed on unbind and allows to completely eliminate the drivers `remove()`
callback.
clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`
Use the managed `devm_of_clk_add_hw_provider()` instead of
`of_clk_add_hw_provider()`. This makes sure the provider gets automatically
removed on unbind and allows to completely eliminate the drivers `remove()`
callback.
Stephen Boyd [Wed, 5 Apr 2023 18:21:30 +0000 (11:21 -0700)]
Merge tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into clk-starfive
Pull Starfive clk driver updates from Conor Dooley:
- Initial JH7110 clk/reset support
A rake of patches, initially worked on by Emil & later picked up by Hal
that add support for the sys/aon clock & reset controllers on StarFive's
JH7110 SoC.
This SoC is largely similar to the existing JH7100, so a bunch of
refactoring is done to share as many bits as possible between the two.
What's here (plus the already applied pinctrl bits) should be sufficient
to boot a basic initramfs.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-jh7110-clk-reset-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: generalise StarFive clk/reset entries
reset: starfive: Add StarFive JH7110 reset driver
clk: starfive: Add StarFive JH7110 always-on clock driver
clk: starfive: Add StarFive JH7110 system clock driver
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: starfive: Extract the common JH71X0 reset code
reset: starfive: Factor out common JH71X0 reset code
reset: Create subdirectory for StarFive drivers
reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
clk: starfive: Factor out common JH7100 and JH7110 code
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Update the MAINTAINERS entry for StarFive's clock and reset drivers to
account for the addition of JH7110 support and Hal's role in that.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[conor: split this out from the binding patch, since it touches more
than the binding; resort the entries per Hal's request] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add driver for the StarFive JH7110 always-on clock controller
and register an auxiliary device for always-on reset controller
which is named as "rst-aon".
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.
There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.
Switch to 32bit I/O in preparation for supporting these resets too.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
reset: starfive: Factor out common JH71X0 reset code
The StarFive JH7100 SoC has additional reset controllers for audio and
video, but the registers follow the same structure. On the JH7110 the
reset registers don't get their own memory range, but instead follow the
clock control registers. The registers still follow the same structure
though, so let's factor out the common code to handle all these cases.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
clk: starfive: Factor out common JH7100 and JH7110 code
The clock control registers on the StarFive JH7100 and JH7110 work
identically, so factor out the code then drivers for the two SoCs
can share it without depending on each other. No functional change.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Hal Feng [Sat, 1 Apr 2023 11:19:15 +0000 (19:19 +0800)]
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
Using ARCH_FOO symbol is preferred than SOC_FOO.
Set obj-y for starfive/ in Makefile, so the StarFive drivers
can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n.
Stephen Boyd [Tue, 4 Apr 2023 20:45:53 +0000 (13:45 -0700)]
clk: mediatek: Use right match table, include mod_devicetable
This is copy/pasta that breaks modular builds. Fix the match table to
use the right pointer, or the right device table type. And while we're
including the header, fix the order to be linux, dt-bindings, and
finally local.
Stephen Boyd [Mon, 3 Apr 2023 19:05:23 +0000 (12:05 -0700)]
Merge tag 'samsung-clk-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk drivers updates from Krzysztof Kozlowski:
- Exynos850: Add CMU_G3D clock controller for the Mali GPU. This
brings new PLLs and few cleanups/simplifications in core Exynos clock
controller code, so they can be easier re-used in Exynos850 clock
controller driver.
New CMU_G3D clock controller needs Devicetree bindings header changes
with clock indices which are pulled from Samsung SoC repository.
- Extract Exynos5433 (ARM64) clock controller power management code to
common driver parts, so later it can be re-used by other Exynos clock
controller drivers. This only prepares for such re-usage, which is
expected to come later for Exynos850.
- Exynos850: make PMU_ALIVE_PCLK clock critical, because it is needed
for core block - Power Management Unit.
- Cleanup: remove() callback returns void.
* tag 'samsung-clk-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
clk: samsung: Convert to platform remove callback returning void
clk: samsung: exynos5433: Extract PM support to common ARM64 layer
clk: samsung: Extract parent clock enabling to common function
clk: samsung: Extract clocks registration to common function
clk: samsung: exynos850: Add AUD and HSI main gate clocks
clk: samsung: exynos850: Implement CMU_G3D domain
clk: samsung: clk-pll: Implement pll0818x PLL type
clk: samsung: Set dev in samsung_clk_init()
clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
clk: samsung: Remove np argument from samsung_clk_init()
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
Garmin.Chang [Fri, 31 Mar 2023 12:36:15 +0000 (20:36 +0800)]
clk: mediatek: Add MT8188 vdosys1 clock support
Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Garmin.Chang [Fri, 31 Mar 2023 12:36:14 +0000 (20:36 +0800)]
clk: mediatek: Add MT8188 vdosys0 clock support
Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Arnd Bergmann [Mon, 27 Feb 2023 08:59:10 +0000 (09:59 +0100)]
clk: tegra20: fix gcc-7 constant overflow warning
Older gcc versions get confused by comparing a u32 value to a negative
constant in a switch()/case block:
drivers/clk/tegra/clk-tegra20.c: In function 'tegra20_clk_measure_input_freq':
drivers/clk/tegra/clk-tegra20.c:581:2: error: case label does not reduce to an integer constant
case OSC_CTRL_OSC_FREQ_12MHZ:
^~~~
drivers/clk/tegra/clk-tegra20.c:593:2: error: case label does not reduce to an integer constant
case OSC_CTRL_OSC_FREQ_26MHZ:
Minghao Chi [Fri, 11 Nov 2022 06:39:35 +0000 (14:39 +0800)]
clock: milbeaut: use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Clément Léger [Tue, 31 Jan 2023 08:32:27 +0000 (09:32 +0100)]
clk: add missing of_node_put() in "assigned-clocks" property parsing
When returning from of_parse_phandle_with_args(), the np member of the
of_phandle_args structure should be put after usage. Add missing
of_node_put() calls in both __set_clk_parents() and __set_clk_rates().
Konrad Dybcio [Tue, 7 Mar 2023 13:29:28 +0000 (14:29 +0100)]
clk: Print an info line before disabling unused clocks
Currently, the regulator framework informs us before calling into
their unused cleanup paths, which eases at least some debugging. The
same could be beneficial for clocks, so that random shutdowns shortly
after most initcalls are done can be less of a guess.
Add a pr_info before disabling unused clocks to do so.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:12 +0000 (17:15 +0100)]
clk: xilinx: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:11 +0000 (17:15 +0100)]
clk: x86: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:10 +0000 (17:15 +0100)]
clk: uniphier: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:09 +0000 (17:15 +0100)]
clk: ti: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:08 +0000 (17:15 +0100)]
clk: tegra: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:07 +0000 (17:15 +0100)]
clk: stm32: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:03 +0000 (17:15 +0100)]
clk: mvebu: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:02 +0000 (17:15 +0100)]
clk: mmp: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:00 +0000 (17:15 +0100)]
clk: keystone: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:14:59 +0000 (17:14 +0100)]
clk: hisilicon: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Uwe Kleine-König [Sun, 12 Mar 2023 16:14:58 +0000 (17:14 +0100)]
clk: stm32mp1: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
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