Stephen Boyd [Fri, 6 Apr 2018 20:38:08 +0000 (13:38 -0700)]
Merge branch 'clk-davinci' into clk-next
* clk-davinci:
clk: davinci: add a reset lookup table for psc0
reset: modify the way reset lookup works for board files
reset: add support for non-DT systems
Stephen Boyd [Fri, 6 Apr 2018 20:36:50 +0000 (13:36 -0700)]
Merge branch 'reset/lookup' of git://git.pengutronix.de/git/pza/linux into clk-davinci
We need this to be able to use the reset_controller_add_lookup() API.
* 'reset/lookup' of git://git.pengutronix.de/git/pza/linux:
reset: modify the way reset lookup works for board files
reset: add support for non-DT systems
Stephen Boyd [Fri, 6 Apr 2018 20:22:06 +0000 (13:22 -0700)]
Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and 'clk-ti-flag-fix' into clk-next
* clk-davinci:
clk: davinci: Remove redundant dev_err calls
clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
clk: davinci: New driver for TI DA8XX CFGCHIP clocks
dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks
clk: davinci: Add platform information for TI DM646x PSC
clk: davinci: Add platform information for TI DM644x PSC
clk: davinci: Add platform information for TI DM365 PSC
clk: davinci: Add platform information for TI DM355 PSC
clk: davinci: Add platform information for TI DA850 PSC
clk: davinci: Add platform information for TI DA830 PSC
clk: davinci: New driver for davinci PSC clocks
dt-bindings: clock: New bindings for TI Davinci PSC
clk: davinci: Add platform information for TI DM646x PLL
clk: davinci: Add platform information for TI DM644x PLL
clk: davinci: Add platform information for TI DM365 PLL
clk: davinci: Add platform information for TI DM355 PLL
clk: davinci: Add platform information for TI DA850 PLL
clk: davinci: Add platform information for TI DA830 PLL
clk: davinci: New driver for davinci PLL clocks
dt-bindings: clock: Add new bindings for TI Davinci PLL clocks
* clk-si544:
clk: Add driver for the si544 clock generator chip
* clk-rockchip:
clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
clk: rockchip: Fix error return in phase clock registration
clk: rockchip: Correct the behaviour of restoring cached phase
clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
clk: rockchip: Add 1.6GHz PLL rate for rk3399
clk: rockchip: Restore the clock phase after the rate was changed
clk: rockchip: Prevent calculating mmc phase if clock rate is zero
clk: rockchip: Free the memory on the error path
clk: rockchip: document hdmi_phy external input for rk3328
clk: rockchip: add flags for rk3328 dclk_lcdc
clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
clk: rockchip: protect all remaining rk3328 interconnect clocks
clk: rockchip: export sclk_hdmi_sfc on rk3328
clk: rockchip: remove HCLK_VIO from rk3328 dt header
clk: rockchip: fix hclk_vio_niu on rk3328
* clk-uniphier:
clk: uniphier: add additional ethernet clock lines for Pro4
clk: uniphier: add SATA clock control support
clk: uniphier: add PCIe clock control support
clk: uniphier: add ethernet clock control support for PXs3
clk: uniphier: add Pro4/Pro5/PXs2 audio system clock
* clk-ti-flag-fix:
clk: ti: fix flag space conflict with clkctrl clocks
clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
Stephen Boyd [Fri, 6 Apr 2018 20:21:57 +0000 (13:21 -0700)]
Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next
* clk-mediatek:
clk: mediatek: add audsys support for MT2701
clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
dt-bindings: clock: mediatek: add audsys support for MT2701
dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
clk: mediatek: update missing clock data for MT7622 audsys
clk: mediatek: fix PWM clock source by adding a fixed-factor clock
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
* clk-hisi:
clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
clk: hisilicon: mark wdt_mux_p[] as const
clk: hisilicon: Mark phase_ops static
clk: hi3798cv200: add emmc sample and drive clock
clk: hisilicon: add hisi phase clock support
clk: hi3798cv200: add COMBPHY0 clock support
clk: hi3798cv200: fix define indentation
clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
clk: hi3798cv200: correct IR clock parent
clk: hi3798cv200: fix unregister call sequence in error path
* clk-allwinner:
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
clk: sunxi-ng: add support for the Allwinner H6 CCU
dt-bindings: add device tree binding for Allwinner H6 main CCU
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
clk: sunxi-ng: Add check for minimal rate to NM PLLs
clk: sunxi-ng: Use u64 for calculation of nkmp rate
clk: sunxi-ng: Mask nkmp factors when setting register
clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name
Stephen Boyd [Fri, 6 Apr 2018 20:21:45 +0000 (13:21 -0700)]
Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' and 'clk-gpio' into clk-next
* clk-spreadtrum:
clk: sprd: add RTC gate for SC9860
dt-bindings: clocks: add APB RTC gate for SC9860
* clk-stm32f:
clk: stm32: Add clk entry for SDMMC2 on stm32F769
clk: stm32: Add DSI clock for STM32F469 Board
clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK
* clk-stm32mp1:
clk: stm32: add configuration flags for each of the stm32 drivers
clk: stm32mp1: add Debug clocks
clk: stm32mp1: add MCO clocks
clk: stm32mp1: add RTC clock
clk: stm32mp1: add Peripheral & Kernel Clocks
clk: stm32mp1: add Kernel timers
clk: stm32mp1: add Sub System clocks
clk: stm32mp1: add Post-dividers for PLL
clk: stm32mp1: add PLL clocks
clk: stm32mp1: add Source Clocks for PLLs
clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators
clk: stm32mp1: Introduce STM32MP1 clock driver
dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings
* clk-hi655x:
clk: enable hi655x common clk automatically
* clk-gpio:
clk: clk-gpio: Allow GPIO to sleep in set/get_parent
Stephen Boyd [Fri, 6 Apr 2018 20:21:33 +0000 (13:21 -0700)]
Merge branches 'clk-ti', 'clk-amlogic', 'clk-tegra' and 'clk-samsung' into clk-next
* clk-ti:
clk: keystone: sci-clk: add support for dynamically probing clocks
clk: ti: add support for clock latching to mux clocks
clk: ti: add support for clock latching to divider clocks
clk: ti: add generic support for clock latching
clk: ti: add support for register read-modify-write low-level operation
dt-bindings: clock: ti: add latching support to mux and divider clocks
* clk-amlogic: (50 commits)
clk: meson: Drop unused local variable and add static
clk: meson: clean-up clk81 clocks
clk: meson: add fdiv clock gates
clk: meson: add mpll pre-divider
clk: meson: axg: add hifi pll clock
clk: meson: axg: add hifi clock bindings
clk: meson: add ROUND_CLOSEST to the pll driver
clk: meson: add gp0 frac parameter for axg and gxl
clk: meson: improve pll driver results with frac
clk: meson: remove special gp0 lock loop
clk: meson: poke pll CNTL last
clk: meson: add fractional part of meson8b fixed_pll
clk: meson: use hhi syscon if available
clk: meson: remove obsolete cpu_clk
clk: meson: rework meson8b cpu clock
clk: meson: split divider and gate part of mpll
clk: meson: migrate plls clocks to clk_regmap
clk: meson: migrate the audio divider clock to clk_regmap
clk: meson: migrate mplls clocks to clk_regmap
clk: meson: add regmap helpers for parm
...
* clk-tegra:
clk: tegra: Fix pll_u rate configuration
clk: tegra: Specify VDE clock rate
clk: tegra20: Correct PLL_C_OUT1 setup
clk: tegra: Mark HCLK, SCLK and EMC as critical
clk: tegra: MBIST work around for Tegra210
clk: tegra: add fence_delay for clock registers
clk: tegra: Add la clock for Tegra210
* clk-samsung: (22 commits)
clk: samsung: Mark a few things static
clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412
clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices
clk: samsung: exynos5420: Add more entries to EPLL rate table
clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU
clk: samsung: Add Exynos5 sub-CMU clock driver
soc: samsung: pm_domains: Add blacklisting clock handling
clk: samsung: Add compile time PLL rate validators
clk: samsung: s3c2410: Fix PLL rates
clk: samsung: exynos7: Fix PLL rates
clk: samsung: exynos5433: Fix PLL rates
clk: samsung: exynos5260: Fix PLL rates
clk: samsung: exynos5250: Fix PLL rates
clk: samsung: exynos3250: Fix PLL rates
clk: exynos5433: Extend list of available AUD_PLL output frequencies
clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclk
clk: samsung: Add a git tree entry to MAINTAINERS
clk: samsung: Remove redundant dev_err call in exynos_audss_clk_probe()
...
Nikita Yushchenko [Tue, 20 Mar 2018 08:33:23 +0000 (11:33 +0300)]
clk: cs2000: set pm_ops in hibernate-compatible way
Use SET_LATE_SYSTEM_SLEEP_PM_OPS() macro instead of direct assignment to
.resume_early field.
This fixes initialization of CS2000 in restore from hibernation in case
of kernel used to load image did not initialize CS2000 while kernel
being restored had CS2000 initialized.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Boris Brezillon [Thu, 22 Mar 2018 09:11:30 +0000 (10:11 +0100)]
clk: bcm2835: De-assert/assert PLL reset signal when appropriate
In order to enable a PLL, not only the PLL has to be powered up and
locked, but you also have to de-assert the reset signal. The last part
was missing. Add it so PLLs that were not enabled by the FW/bootloader
can be enabled from Linux.
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dong Aisheng [Wed, 28 Mar 2018 06:46:39 +0000 (09:46 +0300)]
clk: imx7d: Move clks_init_on before any clock operations
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.
Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Anson Huang [Wed, 28 Mar 2018 06:46:38 +0000 (09:46 +0300)]
clk: imx7d: Correct ahb clk parent select
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.
Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Peter Chen [Wed, 28 Mar 2018 06:46:35 +0000 (09:46 +0300)]
clk: imx7d: Add USB clock information
Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
which is the output of USBOTG2 PHY.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Wed, 21 Mar 2018 14:20:12 +0000 (09:20 -0500)]
clk: socfpga: stratix10: add clock driver for Stratix10 platform
Add a clock driver for the Stratix10 SoC. The driver is similar to the
Cyclone5/Arria10 platforms, with the exception that this driver only uses
one single clock binding.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dinh Nguyen [Wed, 21 Mar 2018 14:20:10 +0000 (09:20 -0500)]
dt-bindings: documentation: add clock bindings information for Stratix10
Document that Stratix10 clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Stratix10
platform.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tero Kristo [Tue, 27 Mar 2018 17:47:04 +0000 (20:47 +0300)]
clk: ti: fix flag space conflict with clkctrl clocks
The introduction of support for CLK_SET_RATE_PARENT flag for clkctrl
clocks used a generic clock flag, which causes a conflict with the
rest of the clkctrl flags, namely the NO_IDLEST flag. This can cause
boot failures on certain platforms where this flag is introduced, by
omitting the wait for the clockctrl module to be fully enabled before
proceeding with rest of the code.
Fix this by moving all the clkctrl specific flags to their own bit-range.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes: 49159a9dc3da ("clk: ti: add support for CLK_SET_RATE_PARENT flag") Reported-by: Christophe Lyon <christophe.lyon@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Kunihiko Hayashi [Fri, 30 Mar 2018 09:44:14 +0000 (18:44 +0900)]
clk: uniphier: add additional ethernet clock lines for Pro4
Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.
Stephen Boyd [Thu, 5 Apr 2018 20:28:16 +0000 (13:28 -0700)]
Merge tag 'v4.17-rockchip-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull more Rockchip clk driver updates from Heiko Stuebner:
Some more fixes for Rockchip clocks mainly resulting from the changes in
phase-handling. Which revealed some parent issues on rk3228 and rk3328 as
well as additional issue in how handle phase restoration.
And to top it off two assignments of already existing clock ids for rk3399.
* tag 'v4.17-rockchip-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
clk: rockchip: Fix error return in phase clock registration
clk: rockchip: Correct the behaviour of restoring cached phase
clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
Bartosz Golaszewski [Fri, 23 Mar 2018 13:04:48 +0000 (14:04 +0100)]
reset: modify the way reset lookup works for board files
Commit 7af1bb19f1d7 ("reset: add support for non-DT systems")
introduced reset control lookup mechanism for boards that still use
board files.
The routine used to register lookup entries takes the corresponding
reset_controlled_dev structure as argument.
It's been determined however that for the first user of this new
interface - davinci psc driver - it will be easier to register the
lookup entries using the reset controller device name.
This patch changes the way lookup entries are added.
Bartosz Golaszewski [Wed, 28 Feb 2018 13:08:57 +0000 (14:08 +0100)]
reset: add support for non-DT systems
The reset framework only supports device-tree. There are some platforms
however, which need to use it even in legacy, board-file based mode.
An example of such architecture is the DaVinci family of SoCs which
supports both device tree and legacy boot modes and we don't want to
introduce any regressions.
We're currently working on converting the platform from its hand-crafted
clock API to using the common clock framework. Part of the overhaul will
be representing the chip's power sleep controller's reset lines using
the reset framework.
This changeset extends the core reset code with a new reset lookup
entry structure. It contains data allowing the reset core to associate
reset lines with devices by comparing the dev_id and con_id strings.
It also provides a function allowing drivers to register lookup entries
with the framework.
The new lookup function is only called as a fallback in case the
of_node field is NULL and doesn't change anything for current users.
Tested with a dummy reset driver with several lookup entries.
An example lookup table registration from a driver can be found below:
Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: David Lechner <david@lechnology.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Mike Looijmans [Tue, 20 Mar 2018 08:15:41 +0000 (09:15 +0100)]
clk: Add driver for the si544 clock generator chip
This patch adds the driver and devicetree documentation for the
Silicon Labs SI544 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 200kHz
to 1500MHz.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Linus Walleij [Thu, 22 Mar 2018 10:16:18 +0000 (11:16 +0100)]
clk: ux500: Drop AB8540/9540 support
The AB8540 was an evolved version of the AB8500, but it was never
mass produced or put into products, only reference designs exist.
The upstream support was never completed and it is unlikely that
this will happen so drop the support for now to simplify
maintenance of the AB8500.
Stephen Boyd [Fri, 23 Mar 2018 16:35:40 +0000 (09:35 -0700)]
Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clock changes from Maxime Ripard:
Our usual bunch of changes for the next merge window. The most significant
addition is the support of the H6 clock unit. Other than that, there's a
bunch of fixes for the video clocks on the H3 and H5, and some Kconfig
cleanup.
* tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
clk: sunxi-ng: add support for the Allwinner H6 CCU
dt-bindings: add device tree binding for Allwinner H6 main CCU
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
clk: sunxi-ng: Add check for minimal rate to NM PLLs
clk: sunxi-ng: Use u64 for calculation of nkmp rate
clk: sunxi-ng: Mask nkmp factors when setting register
clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name
Lin Huang [Tue, 20 Mar 2018 02:06:28 +0000 (10:06 +0800)]
clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.
Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Shawn Lin [Wed, 21 Mar 2018 02:39:20 +0000 (10:39 +0800)]
clk: rockchip: Fix error return in phase clock registration
The newly added clock notifier may return an error code but so far the
error output in the function would only return an error pointer from
registering the clock.
So when the clock notifier fails the clock would be unregistered but the
return would still be the clock pointer which could then not be
dereferenced correctly. So fix the error handling to prevent that.
Fixes: 60cf09e45fbc ("clk: rockchip: Restore the clock phase after the rate was changed") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Shawn Lin [Wed, 21 Mar 2018 02:39:20 +0000 (10:39 +0800)]
clk: rockchip: Correct the behaviour of restoring cached phase
We can't restore every phase, for instance the invalid phase and
the phase for coming rate which is out of the scope of boards'
ability. And this patch also corrects the error path to return
invalid pointer to clk if clk_notifier_register failed introduced
by the same offending commit.
Fixes: 60cf09e45fbc ("clk: rockchip: Restore the clock phase after the rate was changed") Reported-by: wlq <wlq@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: wlq <wlq@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Shawn Lin [Wed, 21 Mar 2018 02:39:18 +0000 (10:39 +0800)]
clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if
clock rate is zero") catches some gremlins for clk-rk3328.c that the
parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not
sclk_{sdmmc, sdio, emmc}.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Shawn Lin [Wed, 21 Mar 2018 02:39:19 +0000 (10:39 +0800)]
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
manual with the card clock having the 0 while the hclk is named
without appended 0. So standardize one one format to prevent
confusion, as there also is only one (non-sdio) mmc controller on
the soc.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Geert Uytterhoeven [Thu, 15 Mar 2018 09:44:37 +0000 (10:44 +0100)]
clk: renesas: rcar-gen3: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
clk_readl()/clk_writel() and readl()/writel() to access the clock
registers. Settle on the generic readl()/writel().
Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Icenowy Zheng [Wed, 21 Mar 2018 02:46:25 +0000 (10:46 +0800)]
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing
in the ccu-sun50i-h6 driver.
Add this missing clock to the driver.
Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Wei Yongjun [Tue, 20 Mar 2018 14:19:34 +0000 (14:19 +0000)]
clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.
This is detected by Coccinelle semantic patch.
@@
expression pdev, res, n, t, e, e1, e2;
@@
res = platform_get_resource(pdev, t, n);
+ if (!res)
+ return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);
David Lechner [Fri, 16 Mar 2018 02:52:35 +0000 (21:52 -0500)]
clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon
register on TI DA8XX-type SoCs.
The USB0 (USB 2.0) PHY clock is an interesting case because it calls
clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled
temporarily while we are locking the PLL, which takes place during the
clk_enable() callback.
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
David Lechner [Fri, 16 Mar 2018 02:52:26 +0000 (21:52 -0500)]
clk: davinci: New driver for davinci PSC clocks
This adds a new driver for mach-davinci PSC clocks. This is porting the
code from arch/arm/mach-davinci/psc.c to the common clock framework and
is converting it to use regmap to simplify the code. Additionally, it
adds device tree support for these clocks.
Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the keystone
driver makes the assumption that there is only one PSC per SoC and uses
global variables, but here we have two controllers per SoC.
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
David Lechner [Fri, 16 Mar 2018 02:52:25 +0000 (21:52 -0500)]
dt-bindings: clock: New bindings for TI Davinci PSC
This adds a new binding for the Power Sleep Controller (PSC) for the
mach-davinci family of processors.
Note: Although TI Keystone has a very similar PSC, we are not using the
existing bindings. Keystone is using a legacy one-node-per-clock binding
(actually two nodes if you count the separate reset binding for the same
IP block). Also, some davinci LPSCs have quirks that aren't handled by
the keystone bindings, so we would be adding one compatible string per
clock with quirks instead of just a new compatible string for each
controller.
Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
David Lechner [Fri, 16 Mar 2018 02:52:18 +0000 (21:52 -0500)]
clk: davinci: New driver for davinci PLL clocks
This adds a new driver for mach-davinci PLL clocks. This is porting the
code from arch/arm/mach-davinci/clock.c to the common clock framework.
Additionally, it adds device tree support for these clocks.
The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent
compile errors until the clock code in arch/arm/mach-davinci is removed.
Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the register
layouts are a bit different, which would add even more if/else mess
to the keystone clocks. And the keystone PLL driver doesn't support
setting clock rates.
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
David Lechner [Fri, 16 Mar 2018 02:52:17 +0000 (21:52 -0500)]
dt-bindings: clock: Add new bindings for TI Davinci PLL clocks
This adds a new binding for the PLL IP blocks in the mach-davinci
family of processors. Currently, only da850 has device tree support
but these bindings can also work for other SoCs in this family just
by adding new compatible strings.
Note: Although these PLL controllers are very similar to the TI Keystone
SoCs, we are not re-using those bindings. The Keystone bindings use a
legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs
have a slightly different PLL register layout and a number of quirks
that can't be handled by the existing bindings, so the keystone bindings
could not be used as-is anyway.
Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Weiyi Lu [Mon, 12 Mar 2018 07:03:42 +0000 (15:03 +0800)]
clk: mediatek: update clock driver of MT2712
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
It exposes an issue that clk core, clk_core_get_phase, always
returns the cached core->phase which should be either updated
by calling clk_set_phase or directly from the first place the
clk was registered.
When registering the clk, the core->phase geting from ->get_phase()
may return negative value indicating error. This is quite common
since the clk's phase may be highly related to its parent chain,
but it was temporarily orphan when registered, since its parent
chains hadn't be ready at that time, so the clk drivers decide to
return error in this case. However, if no clk_set_phase is called or
maybe the ->set_phase() isn't even implemented, the core->phase would
never be updated. This is wrong, and we should try to update it when
all its parent chains are settled down, like the way of updating clock
rate for that. But it's not deserved to complicate the code now and
just update it anyway when calling clk_core_get_phase, which would be
much simple and enough.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Richard Genoud [Tue, 13 Mar 2018 15:27:02 +0000 (16:27 +0100)]
clk: mvebu: armada-38x: add support for missing clocks
Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
or 1333MHz (industrial).
They have also some dip-switches to select a different clock (666, 800,
1066, 1200).
The funny thing is that the recovery button is on the MPP34 fq selector.
So, when booting an industrial board with this button down, the frequency
666MHz is selected (and the kernel didn't boot).
This patch add all the missing clocks.
The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).
Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385") Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants Cc: <stable@vger.kernel.org> # 3.16.x Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Mike Looijmans [Tue, 13 Mar 2018 08:54:03 +0000 (09:54 +0100)]
clk: clk-gpio: Allow GPIO to sleep in set/get_parent
When changing or retrieving clock parents, the caller is in a sleepable
state (like prepare) so the GPIO operation need not be atomic. Replace
gpiod_{g|s}et_value with gpiod_{g|s}et_value_cansleep in the {g|s}et_parent
calls for the GPIO based clock mux.
This fixes a "slowpath" warning when the GPIO controller is an I2C expander
or something similar.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Riku Voipio [Mon, 12 Mar 2018 10:49:45 +0000 (12:49 +0200)]
clk: enable hi655x common clk automatically
Without COMMON_CLK_HI655X Wifi and bluetooth are non-functional on Hikey.
As suggested by Arnd, enable the driver automatically when the parent
driver is selected. With sensible defaults in place, we can leave other
choices for EXPERT.
Cc: John Stultz <john.stultz@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Suggested-by: Arnd Bergmann <arnd@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Benjamin Gaignard [Mon, 12 Mar 2018 09:32:48 +0000 (10:32 +0100)]
clk: stm32: add configuration flags for each of the stm32 drivers
Add two configuration flags to be able to not compile all the time
stm32f and stm32h7 drivers when ARCH_STM32 is set.
That help to save some space on those small platforms.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Gabriel Fernandez [Fri, 9 Mar 2018 06:57:30 +0000 (07:57 +0100)]
clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK
Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
hsi and sysclk are overwritten by gpioa and gpiob.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Tested-by: Philippe Cornu <philippe.cornu@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ryder Lee [Tue, 6 Mar 2018 09:09:29 +0000 (17:09 +0800)]
dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
The MediaTek audio hardware block that exposes functionalities that are
handled by separate subsystems in the kernel. These functions are all
mapped somewhere at 0x112xxxxx, and there are some control bits are mixed
up with other functions within the same registers.
This patch modifies example to illustrate child nodes.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Sean Wang [Thu, 1 Mar 2018 03:27:51 +0000 (11:27 +0800)]
clk: mediatek: fix PWM clock source by adding a fixed-factor clock
The clock for which all PWM devices on MT7623 or MT2701 actually depending
on has to be divided by four from its parent clock axi_sel in the clock
path prior to PWM devices.
Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
clock axi_sel allows that PWM devices can have the correct resolution
calculation.
Cc: stable@vger.kernel.org Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Sean Wang [Thu, 1 Mar 2018 03:27:50 +0000 (11:27 +0800)]
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
Just add binding for a fixed-factor clock axisel_d4, which would be
referenced by PWM devices on MT7623 or MT2701 SoC.
Cc: stable@vger.kernel.org Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Gregory CLEMENT [Wed, 28 Feb 2018 14:07:51 +0000 (15:07 +0100)]
clk: mvebu: cp110: Fix clock tree representation
Thanks to new documentation, we have a better view of the clock tree.
There were few mistakes in the first version of this driver, the main one
being the parental link between the clocks. Actually the tree is more
flat that we though. Most of the IP blocks require two clocks: one for
the IP itself and one for accessing the registers, and unlike what we
wrote there is no link between these two clocks.
The other mistakes were about the name of the clocks: the root clock is
not the Audio PLL but the PLL0, and what we called the EIP clock is named
the x2 Core clock and is used by other IP block than the EIP ones.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When we build this driver with on x86-32, gcc produces a false-positive warning:
drivers/clk/renesas/clk-sh73a0.c: In function 'sh73a0_cpg_clocks_init':
drivers/clk/renesas/clk-sh73a0.c:155:10: error: 'parent_name' may be used uninitialized in this function [-Werror=maybe-uninitialized]
return clk_register_fixed_factor(NULL, name, parent_name, 0,
We can work around that warning by adding a fake initialization, I tried
and failed to come up with any better workaround. This is currently one
of few remaining warnings for a 4.14.y randconfig build, so it would be
good to also have it backported at least to that version. Older versions
have more randconfig warnings, so we might not care.
I had not noticed this earlier, because one patch in my randconfig test
tree removes the '-ffreestanding' option on x86-32, and that avoids
the warning. The -ffreestanding flag was originally global but moved
into arch/i386 by Andi Kleen in commit 6edfba1b33c7 ("[PATCH] x86_64:
Don't define string functions to builtin") as a 'temporary workaround'.
Like many temporary hacks, this turned out to be rather long-lived, from
all I can tell we still need a simple fix to asm/string_32.h before it
can be removed, but I'm not sure about how to best do that.