Dave Airlie [Fri, 6 Sep 2024 06:02:05 +0000 (16:02 +1000)]
Merge tag 'mediatek-drm-next-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
Mediatek DRM Next for Linux 6.12
1. Support alpha blending
2. Remove cl in struct cmdq_pkt
3. Fixup for ovl adaptor
4. Declare Z Position for all planes
5. Drop unnecessary check for property presence
6. Add dsi per-frame lp code for mt8188
7. Fix missing configuration flags in mtk_crtc_ddp_config()
8. Use spin_lock_irqsave() for CRTC event lock
9. Add power domain binding to the mediatek DPI controller
Dave Airlie [Fri, 6 Sep 2024 01:24:37 +0000 (11:24 +1000)]
Merge tag 'drm-intel-next-2024-09-03' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
- Fix probe on 'nomodeset and deprecate i915.modeset=0 (Jani)
- Update new entries in VBT BDB block definitions (Dnyaneshwar)
- Fix clang build (Andy Shevchenko)
- More clean up on drvdata usage in display code (Jani)
- Increase fastwake DP sync pulse count as a quirk (Jouni)
Jani Nikula [Fri, 30 Aug 2024 10:15:46 +0000 (13:15 +0300)]
drm/i915/psr: convert intel_psr.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_psr.[ch] to struct intel_display.
Jani Nikula [Fri, 30 Aug 2024 10:15:45 +0000 (13:15 +0300)]
drm/i915/pps: convert intel_pps.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_pps.[ch] to struct intel_display.
Jani Nikula [Fri, 30 Aug 2024 10:15:44 +0000 (13:15 +0300)]
drm/i915/pps: pass intel_dp to pps_name()
Currently all of intel_pps.c passes struct intel_dp around. Do the same
with pps_name() instead of passing both struct drm_i915_private and
struct intel_pps.
Jani Nikula [Fri, 30 Aug 2024 10:15:43 +0000 (13:15 +0300)]
drm/i915/dp: convert intel_dp_link_training.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_dp_link_training.[ch] to struct intel_display.
Jani Nikula [Fri, 30 Aug 2024 10:15:42 +0000 (13:15 +0300)]
drm/i915/dp: convert intel_dp_aux.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_dp_aux.[ch] to struct intel_display.
Jani Nikula [Fri, 30 Aug 2024 10:15:41 +0000 (13:15 +0300)]
drm/i915/dp: convert intel_dp_tunnel.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_dp_tunnel.[ch] to struct intel_display.
Jani Nikula [Fri, 30 Aug 2024 10:15:40 +0000 (13:15 +0300)]
drm/i915/dp: convert g4x_dp.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
g4x_dp.[ch] to struct intel_display.
Jani Nikula [Fri, 30 Aug 2024 10:15:39 +0000 (13:15 +0300)]
drm/i915/hdmi: convert to struct intel_display
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_hdmi.[ch] to struct intel_display. Remove intel_hdmi_to_i915().
Jani Nikula [Fri, 30 Aug 2024 10:15:38 +0000 (13:15 +0300)]
drm/xe/display: use xe && 0 to avoid warnings about unused variables
Avoid warnings about unused variables when the IS_LP(), IS_GEN9_LP(),
and IS_GEN9_BC() macros are the only users of a variable. This is not
currently the case, but prepare for future changes.
drm/i915/display: Increase Fast Wake Sync length as a quirk
In commit "drm/i915/display: Increase number of fast wake precharge pulses"
we were increasing Fast Wake sync pulse length to fix problems observed on
Dell Precision 5490 laptop with AUO panel. Later we have observed this is
causing problems on other panels.
Fix these problems by increasing Fast Wake sync pulse length as a quirk
applied for Dell Precision 5490 with problematic panel.
Fixes: f77772866385 ("drm/i915/display: Increase number of fast wake precharge pulses") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Closes: http://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9739 Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2246 Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11762 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Cc: <stable@vger.kernel.org> # v6.10+ Link: https://patchwork.freedesktop.org/patch/msgid/20240902064241.1020965-3-jouni.hogander@intel.com
drm/i915/display: Add mechanism to use sink model when applying quirk
Currently there is no way to apply quirk on device only if certain panel
model is installed. This patch implements such mechanism by adding new
quirk type intel_dpcd_quirk which contains also sink_oui and sink_device_id
fields and using also them to figure out if applying quirk is needed.
New intel_init_dpcd_quirks is added and called after drm_dp_read_desc with
proper sink device identity read from dpcdc.
v3:
- !mem_is_zero fixed to mem_is_zero
v2:
- instead of using struct intel_quirk add new struct intel_dpcd_quirk
Jani Nikula [Thu, 29 Aug 2024 14:47:47 +0000 (17:47 +0300)]
drm/i915/hdcp: migrate away from kdev_to_i915() in GSC messaging
Use to_intel_display() instead of kdev_to_i915() in the HDCP component
API hooks. Avoid further drive-by changes at this point, and just
convert the display pointer to i915, and leave the struct intel_display
conversion for later.
The NULL error checking in the hooks make this a bit cumbersome. I'm not
actually sure they're really required, but don't go down that rabbit
hole just now.
drm/xe: Fix merge fails related to display runtime PM
The most recent merge commits introduced some fails to drm/drm-next,
I've noticed these when looking at the xe patches.
Solve it!
Fixes: 8bdb468dd7a5 ("Merge tag 'drm-xe-next-2024-08-28' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next") Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
[sima: add fixes line, and drop 3rd hunk because that's just a bugfix,
not mismerge, which should go in seperately with proper fixes line and
review/testing.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20240902112002.489225-1-maarten.lankhorst@linux.intel.com
Jani Nikula [Thu, 29 Aug 2024 14:47:46 +0000 (17:47 +0300)]
drm/i915/hdcp: migrate away from kdev_to_i915() in bind/unbind
Use to_intel_display() instead of kdev_to_i915() in the HDCP component
API hooks. Avoid further drive-by changes at this point, and just
convert the display pointer to i915, and leave the struct intel_display
conversion for later.
Jani Nikula [Thu, 29 Aug 2024 14:47:45 +0000 (17:47 +0300)]
drm/i915/audio: migrate away from kdev_to_i915()
Use to_intel_display() instead of kdev_to_i915() in the audio component
API hooks. Avoid further drive-by changes at this point, and just
convert the display pointer to i915, and leave the struct intel_display
conversion for later.
Jani Nikula [Thu, 29 Aug 2024 14:47:43 +0000 (17:47 +0300)]
drm/i915 & drm/xe: save struct drm_device to drvdata
In the future, the display code shall not have any idea about struct
xe_device or struct drm_i915_private, but will need to get at the struct
drm_device via drvdata. Store the struct drm_device pointer to drvdata
instead of the driver specific pointer.
Avoid passing NULL to container_of() via to_i915()/to_xe_device(). (It
does return NULL for NULL pointers when the offset happens to be 0, but
otherwise returns garbage pointers for NULL.)
Dmitry Baryshkov [Sun, 4 Aug 2024 05:40:07 +0000 (08:40 +0300)]
drm/msm/dsi: correct programming sequence for SM8350 / SM8450
According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.
Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/606947/ Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-3-1149dd8399fe@linaro.org
Add support for the HDMI PHY as present on the Qualcomm MSM8998 SoC.
This code is mostly copy & paste of the vendor code from msm-4.4
kernel.lnx.4.4.r38-rel.
Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Patchwork: https://patchwork.freedesktop.org/patch/605631/ Link: https://lore.kernel.org/r/20240724-hdmi-tx-v7-4-e44a20553464@freebox.fr
[DB: replaced division with do_div64 to fix build issues on ARM32] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Baryshkov [Sat, 31 Aug 2024 10:10:44 +0000 (13:10 +0300)]
drm/msm/dpu: Configure DP INTF/PHY selector
Some platforms provides a mechanism for configuring the mapping between
(one or two) DisplayPort intfs and their PHYs.
In particular SC8180X requires this to be configured, since on this
platform there are fewer controllers than PHYs.
The change implements the logic for optionally configuring which PHY
each of the DP INTFs should be connected to and marks the SC8180X DPU to
program 2 entries.
For now the request is simply to program the mapping 1:1, any support
for alternative mappings is left until the use case arrise.
Note that e.g. msm-4.14 unconditionally maps INTF 0 to PHY 0 on all
platforms, so perhaps this is needed in order to get DisplayPort working
on some other platforms as well.
Otto Pflüger [Mon, 22 Jul 2024 14:58:19 +0000 (16:58 +0200)]
drm/msm/adreno: Add A306A support
Add support for Adreno 306A GPU what is found in MSM8917 SoC.
This GPU marketing name is Adreno 308.
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
[use internal name of the GPU, reword the commit message] Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Barnabás Czémán <trabarni@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/605403/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Wed, 28 Aug 2024 15:06:59 +0000 (17:06 +0200)]
drm/msm/a6xx: Add A621 support
A621 is a clear A662 derivative (same lineage as A650), no explosions
or sick features, other than a NoC bug which can stall the GPU..
Add support for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611100/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Wed, 28 Aug 2024 15:06:58 +0000 (17:06 +0200)]
drm/msm/a6xx: Set GMU CGC properties on a6xx too
This was apparently never done before.. Program the expected values.
This also gets rid of sneakily setting that register through the HWCG
reg list on A690.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611098/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Wed, 28 Aug 2024 15:06:57 +0000 (17:06 +0200)]
drm/msm/a6xx: Use the per-GPU value for gmu_cgc_mode
This register's magic value differs wildly between different GPUs, use
the hardcoded data instead of trying to make some logic out of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611096/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Wed, 28 Aug 2024 15:06:56 +0000 (17:06 +0200)]
drm/msm/a6xx: Store correct gmu_cgc_mode in struct a6xx_info
Store the correct values that we happen to have for some A7xx SKUs in
the GPU info struct and fill out the missing information for A6xx GPUs
based on downstream kernel information.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611094/
[add missing entry to a615 catalog to resolve conflict] Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Wed, 28 Aug 2024 15:06:55 +0000 (17:06 +0200)]
drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info
The if-else monster is so unmaintainable that one case is repeated
twice. Get rid of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611092/
[add missing entry to a615 catalog to resolve conflict] Signed-off-by: Rob Clark <robdclark@chromium.org>
Konrad Dybcio [Fri, 19 Jul 2024 10:03:26 +0000 (12:03 +0200)]
drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check
A650 family includes A660 family (they've got a big family), A650
itself, and some more A6XX_GEN3 SKUs, all of which should fall into
the same branch of the if-condition. Simplify that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/605206/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Vladimir Lypak [Sun, 1 Sep 2024 13:54:03 +0000 (13:54 +0000)]
drm/msm/a5xx: workaround early ring-buffer emptiness check
There is another cause for soft lock-up of GPU in empty ring-buffer:
race between GPU executing last commands and CPU checking ring for
emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS
event and RPTR shadow (which is used to check ring emptiness) is updated
a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its
last commands slow enough or we check that ring too fast we will miss a
chance to trigger switch to lower priority ring because current ring isn't
empty just yet. This can escalate to lock-up situation described in
previous patch.
To work-around this issue we keep track of last submit sequence number
for each ring and compare it with one written to memptrs from GPU during
execution of CACHE_FLUSH_TS event.
Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/612047/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Vladimir Lypak [Sun, 1 Sep 2024 13:54:02 +0000 (13:54 +0000)]
drm/msm/a5xx: fix races in preemption evaluation stage
On A5XX GPUs when preemption is used it's invietable to enter a soft
lock-up state in which GPU is stuck at empty ring-buffer doing nothing.
This appears as full UI lockup and not detected as GPU hang (because
it's not). This happens due to not triggering preemption when it was
needed. Sometimes this state can be recovered by some new submit but
generally it won't happen because applications are waiting for old
submits to retire.
One of the reasons why this happens is a race between a5xx_submit and
a5xx_preempt_trigger called from IRQ during submit retire. Former thread
updates ring->cur of previously empty and not current ring right after
latter checks it for emptiness. Then both threads can just exit because
for first one preempt_state wasn't NONE yet and for second one all rings
appeared to be empty.
To prevent such situations from happening we need to establish guarantee
for preempt_trigger to make decision after each submit or retire. To
implement this we serialize preemption initiation using spinlock. If
switch is already in progress we need to re-trigger preemption when it
finishes.
Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/612045/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Vladimir Lypak [Sun, 1 Sep 2024 13:54:01 +0000 (13:54 +0000)]
drm/msm/a5xx: properly clear preemption records on resume
Two fields of preempt_record which are used by CP aren't reset on
resume: "data" and "info". This is the reason behind faults which happen
when we try to switch to the ring that was active last before suspend.
In addition those faults can't be recovered from because we use suspend
and resume to do so (keeping values of those fields again).
Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/612043/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Vladimir Lypak [Sun, 1 Sep 2024 13:54:00 +0000 (13:54 +0000)]
drm/msm/a5xx: disable preemption in submits by default
Fine grain preemption (switching from/to points within submits)
requires extra handling in command stream of those submits, especially
when rendering with tiling (using GMEM). However this handling is
missing at this point in mesa (and always was). For this reason we get
random GPU faults and hangs if more than one priority level is used
because local preemption is enabled prior to executing command stream
from submit.
With that said it was ahead of time to enable local preemption by
default considering the fact that even on downstream kernel it is only
enabled if requested via UAPI.
Fixes: a7a4c19c36de ("drm/msm/a5xx: fix setting of the CP_PREEMPT_ENABLE_LOCAL register") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/612041/ Signed-off-by: Rob Clark <robdclark@chromium.org>
is called on gpu->pdev == NULL, as the GPU device has not been fully
initialized yet.
Turns out that there's more than just the aforementioned path that
causes this to happen (e.g. the case when there's speedbin data in the
catalog, but opp-supported-hw is missing in DT).
Assigning msm_gpu->pdev earlier seems like the least painful solution
to this, therefore do so.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/602742/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Aleksandr Mishin [Fri, 5 Jul 2024 09:13:12 +0000 (12:13 +0300)]
drm/msm: Fix incorrect file name output in adreno_request_fw()
In adreno_request_fw() when debugging information is printed to the log
after firmware load, an incorrect filename is printed. 'newname' is used
instead of 'fwname', so prefix "qcom/" is being added to filename.
Looks like "copy-paste" mistake.
Fix this mistake by replacing 'newname' with 'fwname'.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 2c41ef1b6f7d ("drm/msm/adreno: deal with linux-firmware fw paths") Signed-off-by: Aleksandr Mishin <amishin@t-argos.ru> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/602382/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 13:04:59 +0000 (14:04 +0100)]
drm/msm: Fix UBWC macrotile_mode for a680
Make it match the MDSS settings for sc8180x and downstream.
Note that without the previous commit that exposes the value of
macrotile_mode to mesa, this will break mesa which expects the legacy
default value of 0. Therefore we do *not* want to backport it.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607398/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 13:04:58 +0000 (14:04 +0100)]
drm/msm: Expose expanded UBWC config uapi
This adds extra parameters that affect UBWC tiling that will be used by
the Mesa implementation of VK_EXT_host_image_copy.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607401/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 13:04:57 +0000 (14:04 +0100)]
drm/msm: Expand UBWC config setting
According to downstream we should be setting RBBM_NC_MODE_CNTL to a
non-default value on a663 and a680, we don't support a663 and on a680
we're leaving it at the wrong (suboptimal) value. Just set it on all
GPUs. Similarly, plumb through level2_swizzling_dis which will be
necessary on a663.
ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on
the display side. Similarly macrotile_mode should match the display
side.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607397/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 13:04:56 +0000 (14:04 +0100)]
drm/msm: Update a6xx register XML
Update to Mesa commit 36a13d2b3b0 ("freedreno: fix a7xx perfcntr
countables").
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607395/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 12:34:29 +0000 (13:34 +0100)]
drm/msm: Fix CP_BV_DRAW_STATE_ADDR name
This was missed because we weren't using the a750-specific indexed regs.
Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/607394/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 12:34:28 +0000 (13:34 +0100)]
drm/msm: Dump correct dbgahb clusters on a750
This was missed thanks to the family mixup fixed in the previous commit.
Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607393/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott [Wed, 7 Aug 2024 12:34:27 +0000 (13:34 +0100)]
drm/msm: Use a7xx family directly in gpu_state
With a7xx, we need to import a new header for each new generation and
switch to a different list of registers, instead of making
backwards-compatible changes. Using the helpers inadvertently made a750
use the a740 list of registers, instead use the family directly to fix
this.
Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750") Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607392/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Richard Acayan [Tue, 6 Aug 2024 21:44:56 +0000 (17:44 -0400)]
drm/msm/adreno: add a615 support
The Adreno A615 is used in SDM670. Add an entry to support it.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/607238/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Fri, 9 Aug 2024 18:37:52 +0000 (11:37 -0700)]
drm/msm: Remove unused pm_state
This was added in commit ec446d09366c ("drm/msm: call
drm_atomic_helper_suspend() and drm_atomic_helper_resume()"), but unused
since commit ca8199f13498 ("drm/msm/dpu: ensure device suspend happens
during PM sleep") which switched to drm_mode_config_helper_suspend()/
drm_mode_config_helper_resume()..
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/607746/
Li Zetao [Wed, 21 Aug 2024 01:21:34 +0000 (09:21 +0800)]
drm/msm/adreno: Use kvmemdup to simplify the code
Use kvmemdup instead of kvmalloc() + memcpy() to simplify the code.
No functional change intended.
Signed-off-by: Li Zetao <lizetao1@huawei.com> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/609596/ Signed-off-by: Rob Clark <robdclark@chromium.org>
Rohit Agarwal [Fri, 30 Aug 2024 08:45:42 +0000 (08:45 +0000)]
dt-bindings: display: mediatek: dpi: Add power domains
Add power domain binding to the mediatek DPI controller
for MT8186.
Also, add power domain binding for other SoCs like
MT6795 and MT8173 that already had power domain property.
Dave Airlie [Fri, 30 Aug 2024 03:41:26 +0000 (13:41 +1000)]
Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Cross-driver (xe-core) Changes:
- Require BMG scanout buffers to be 64k physically aligned (Maarten)
Core (drm) Changes:
- Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka)
Driver Changes:
- General cleanup and more work moving towards intel_display isolation (Jani)
- New display workaround (Suraj)
- Use correct cp_irq_count on HDCP (Suraj)
- eDP PSR fix when CRC is enabled (Jouni)
- Fix DP MST state after a sink reset (Imre)
- Fix Arrow Lake GSC firmware version (John)
- Use chained DSBs for LUT programming (Ville)
Dave Airlie [Fri, 30 Aug 2024 03:41:05 +0000 (13:41 +1000)]
Merge tag 'drm-xe-next-2024-08-28' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next
UAPI Changes:
- Fix OA format masks which were breaking build with gcc-5
Cross-subsystem Changes:
Driver Changes:
- Use dma_fence_chain_free in chain fence unused as a sync (Matthew Brost)
- Refactor hw engine lookup and mmio access to be used in more places
(Dominik, Matt Auld, Mika Kuoppala)
- Enable priority mem read for Xe2 and later (Pallavi Mishra)
- Fix PL1 disable flow in xe_hwmon_power_max_write (Karthik)
- Fix refcount and speedup devcoredump (Matthew Brost)
- Add performance tuning changes to Xe2 (Akshata, Shekhar)
- Fix OA sysfs entry (Ashutosh)
- Add first GuC firmware support for BMG (Julia)
- Bump minimum GuC firmware for platforms under force_probe to match LNL
and BMG (Julia)
- Fix access check on user fence creation (Nirmoy)
- Add/document workarounds for Xe2 (Julia, Daniele, John, Tejas)
- Document workaround and use proper WA infra (Matt Roper)
- Fix VF configuration on media GT (Michal Wajdeczko)
- Fix VM dma-resv lock (Matthew Brost)
- Allow suspend/resume exec queue backend op to be called multiple times
(Matthew Brost)
- Add GT stats to debugfs (Nirmoy)
- Add hwconfig to debugfs (Matt Roper)
- Compile out all debugfs code with ONFIG_DEUBG_FS=n (Lucas)
- Remove dead kunit code (Jani Nikula)
- Refactor drvdata storing to help display (Jani Nikula)
- Cleanup unsused xe parameter in pte handling (Himal)
- Rename s/enable_display/probe_display/ for clarity (Lucas)
- Fix missing MCR annotation in couple of registers (Tejas)
- Fix DGFX display suspend/resume (Maarten)
- Prepare exec_queue_kill for PXP handling (Daniele)
- Fix devm/drmm issues (Daniele, Matthew Brost)
- Fix tile and ggtt fini sequences (Matthew Brost)
- Fix crashes when probing without firmware in place (Daniele, Matthew Brost)
- Use xe_managed for kernel BOs (Daniele, Matthew Brost)
- Future-proof dss_per_group calculation by using hwconfig (Matt Roper)
- Use reserved copy engine for user binds on faulting devices
(Matthew Brost)
- Allow mixing dma-fence jobs and long-running faulting jobs (Francois)
- Cleanup redundant arg when creating use BO (Nirmoy)
- Prevent UAF around preempt fence (Auld)
- Fix display suspend/resume (Maarten)
- Use vma_pages() helper (Thorsten)
- Calculate pagefault queue size (Stuart, Matthew Auld)
- Fix missing pagefault wq destroy (Stuart)
- Fix lifetime handling of HW fence ctx (Matthew Brost)
- Fix order destroy order for jobs (Matthew Brost)
- Fix TLB invalidation for media GT (Matthew Brost)
- Document GGTT (Rodrigo Vivi)
- Refactor GGTT layering and fix runtime outer protection (Rodrigo Vivi)
- Handle HPD polling on display pm runtime suspend/resume (Imre, Vinod)
- Drop unrequired NULL checks (Apoorva, Himal)
- Use separate rpm lockdep map for non-d3cold-capable devices (Thomas Hellström)
- Support "nomodeset" kernel command-line option (Thomas Zimmermann)
- Drop force_probe requirement for LNL and BMG (Lucas, Balasubramani)
host1x:
- fix syncpoint IRQ during resume
- use iommu_paging_domain_alloc()
imx:
- ipuv3: convert to struct drm_edid
omapdrm:
- improve error handling
panel:
- add support for BOE TV101WUM-LL2 plus DT bindings
- novatek-nt35950: improve error handling
- nv3051d: improve error handling
- panel-edp: add support for BOE NE140WUM-N6G; revert support for
SDC ATNA45AF01
- visionox-vtdr6130: improve error handling; use
devm_regulator_bulk_get_const()
renesas:
- rz-du: add support for RZ/G2UL plus DT bindings
Dnyaneshwar Bhadane [Wed, 21 Aug 2024 12:17:40 +0000 (17:47 +0530)]
drm/i915/bios: Update new entries in VBT BDB block definitions
New entries updated in BDB definition from VBT v257 to v260.
Extend fields in backlight power controller VBT block 43 for VBT v257.
Add t6 delay support fields in edp panel power block 27 for VBT v260.
Update supported VBT version range for obsolete fields.
v2:
- Update the commit message with description(Jani)
- Rename variable names align to spec names(Jani)
Jani Nikula [Wed, 28 Aug 2024 11:19:09 +0000 (14:19 +0300)]
drm/i915: deprecate the i915.modeset module parameter
The i915.modeset parameter doesn't really provide any useful benefit
over the nomodeset kernel parameter. Anything that i915.modeset does can
be achieved via nomodeset or not probing i915 at all.
Unfortunately, the i915.modeset parameter is widely referenced on
various forums, and removing it is not that simple. Start off by
deprecating it in the module parameter documentation, and logging a
warning message on non-default values.
Jani Nikula [Wed, 28 Aug 2024 11:19:08 +0000 (14:19 +0300)]
drm/i915: fail module probe on nomodeset and i915.modeset=0
Since commit b30324adaf8d ("drm/i915: Deprecated UMS support") we've
silently failed the probe, without propagating errors, on nomodeset and
i915.modeset=0. This has been to not upset userspace. See the above
commit for details.
Since then, we've removed both the UMS and KMS kconfig options in commit 03dae59c72ff ("drm/i915: Ditch UMS config option") and commit fd930478fb79 ("drm/i915: Remove KMS Kconfig option") respectively.
Another ten years or so have passed. Continue with the deprecation by
actually failing the probe with nomodeset and i915.modeset=0.
Jason-JH.Lin [Tue, 27 Aug 2024 14:55:19 +0000 (22:55 +0800)]
drm/mediatek: Fix missing configuration flags in mtk_crtc_ddp_config()
In mtk_crtc_ddp_config(), mtk_crtc will use some configuration flags to
generate instructions to cmdq_handle, such as:
state->pending_config
mtk_crtc->pending_planes
plane_state->pending.config
mtk_crtc->pending_async_planes
plane_state->pending.async_config
These configuration flags may be set to false when a GCE IRQ comes calling
ddp_cmdq_cb(). This may result in missing prepare instructions,
especially if mtk_crtc_update_config() with the flase need_vblank (no need
to wait for vblank) cases.
Therefore, the mtk_crtc->config_updating flag is set at the beginning of
mtk_crtc_update_config() to ensure that these configuration flags won't be
changed when the mtk_crtc_ddp_config() is preparing instructions.
But somehow the ddp_cmdq_cb() didn't use the mtk_crtc->config_updating
flag to prevent those pending config flags from being cleared.
To avoid missing the configuration when generating the config instruction,
the config_updating flag should be added into ddp_cmdq_cb() and be
protected with spin_lock.
Shuijing Li [Mon, 26 Aug 2024 06:06:20 +0000 (14:06 +0800)]
drm/mediatek: dsi: Add dsi per-frame lp code for mt8188
Adding the per-frame lp function of mt8188, which can keep HFP in HS and
reduce the time required for each line to enter and exit low power.
Per Frame LP:
|<----------One Active Frame-------->|
--______________________________________----___________________
^HSA+HBP^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^ ^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---------------One Active Frame----------->|
--______________--______________--______________----______________
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^
drm/mediatek: Drop unnecessary check for property presence
of_property_read_u32() returns -EINVAL if a property is not present, so
the preceding check for presence with of_find_property() can be
dropped. Really, what the errno is shouldn't matter. Either the property
can be read and used or it can't and is ignored.
This is part of a larger effort to remove callers of of_find_property()
and similar functions. of_find_property() leaks the DT struct property
and data pointers which is a problem for dynamically allocated nodes
which may be freed.
AngeloGioacchino Del Regno [Thu, 18 Jul 2024 08:25:07 +0000 (10:25 +0200)]
drm/mediatek: Declare Z Position for all planes
MediaTek SoCs support multiple planes, one of which is the primary
and all the others are overlays (and CURSOR is the last overlay).
In all currently supported SoCs, the Z order of the overlays can't
be changed with any fast muxing action, and can only be changed by
swapping the contents of the entire register set of one overlay
with the other to internally reorder the layer properties, which
is indeed feasible, but probably more expensive than desired.
Declare the Z position for all planes with an immutable property
at least for now, so that the userspace can take its decisions
accordingly.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:32 +0000 (22:10 +0300)]
drm/i915/dsb: Use chained DSBs for LUT programming
In order to better handle the necessary DSB DEwake tricks let's
switch over to using a chained DSB for the actual LUT programming.
The CPU will start 'dsb_color_commit', which in turn will start the
chained 'dsb_color_vblank'.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:31 +0000 (22:10 +0300)]
drm/i915/dsb: s/dsb/dsb_color_vblank/
We'll soon utilize several DSBs during the commit. To that end
rename the current crtc_state->dsb to crtc_state->dsb_color_vblank
to better reflect its role (color managemnent stuff programmed during
vblank).
Ville Syrjälä [Mon, 24 Jun 2024 19:10:30 +0000 (22:10 +0300)]
drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done
In order to avoid the DSB keeping the DEwake permanently
asserted we must clear DSB_PMCTRL_2.DSB_FORCE_DEWAKE once
we are done. For good measure do the same for
DSB_PMCTRL.DSB_ENABLE_DEWAKE.
Experimentally this doens't seem to be actually necessary
(unlike with DSB_FORCE_DEWAKE). That is, the DSB_ENABLE_DEWAKE
doesn't seem to do anything whenever the DSB is not active.
But I'd hate to waste a ton of power in case there I'm wrong
and there is some way DEwake could remaing asserted. One extra
register write is a small price to pay for some peace of mind.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:29 +0000 (22:10 +0300)]
drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK
Allow intel_dsb_chain() to start the chained DSB
at start of the undelaye vblank. This is slightly
more involved than simply setting the bit as we
must use the DEwake mechanism to eliminate pkgC
latency.
And DSB_ENABLE_DEWAKE itself is problematic in that
it allows us to configure just a single scanline,
and if the current scanline is already past that
DSB_ENABLE_DEWAKE won't do anything, rendering the
whole thing moot.
The current workaround involves checking the pipe's current
scanline with the CPU, and if it looks like we're about to
miss the configured DEwake scanline we set DSB_FORCE_DEWAKE
to immediately assert DEwake. This is somewhat racy since the
hardware is making progress all the while we're checking it on
the CPU.
We can make things less racy by chaining two DSBs and handling
the DSB_FORCE_DEWAKE stuff entirely without CPU involvement:
1. CPU starts the first DSB immediately
2. First DSB configures the second DSB, including its dewake_scanline
3. First DSB starts the second w/ DSB_WAIT_FOR_VBLANK
4. First DSB asserts DSB_FORCE_DEWAKE
5. First DSB waits until we're outside the dewake_scanline-vblank_start
window
6. First DSB deasserts DSB_FORCE_DEWAKE
That will guarantee that the we are fully awake when the second
DSB starts to actually execute.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:28 +0000 (22:10 +0300)]
drm/i915/dsb: Introduce intel_dsb_chain()
In order to handle the DEwake tricks without involving
the CPU we need a mechanism by which one DSB can start
another one. Add a basic function to do so. We'll extend
it later with additional code to actually deal with
DEwake.
Add functions to emit a DSB scanline window wait instructions.
We can either wait for the scanline to be IN the window
or OUT of the window.
The hardware doesn't handle wraparound so we must manually
deal with it by swapping the IN range to the inverse OUT
range, or vice versa.
Also add a bit of paranoia to catch the edge case of waiting
for the entire frame. That doesn't make sense since an IN
wait would be a nop, and an OUT wait would imply waiting
forever. Most of the time this also results in both scanline
ranges (original and inverted) to have lower=upper+1
which is nonsense from the hw POV.
For now we are only handling the case where the scanline wait
happens prior to latching the double buffered registers during
the commit (which might change the timings due to LRR/VRR/etc.)
Ville Syrjälä [Mon, 24 Jun 2024 19:10:26 +0000 (22:10 +0300)]
drm/i915/dsb: Precompute DSB_CHICKEN
Adjust the code that determines the correct DSB_CHICKEN value
to be usable for use within DSB commands themselves. Ie.
precompute it based on our knowledge of what the hardware state
(VRR vs. not mainly) will be at the time of the commit.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:25 +0000 (22:10 +0300)]
drm/i915/dsb: Account for VRR properly in DSB scanline stuff
When determining various scanlines for DSB use we should take into
account whether VRR is active at the time when the DSB uses said
scanline information. For now all DSB scanline usage occurs prior
to the actual commit, so we only need to care about the state of
VRR at that time.
I've decided to move intel_crtc_scanline_to_hw() in its entirety
to the DSB code as it will also need to know the actual state
of VRR in order to do its job 100% correctly.
TODO: figure out how much of this could be moved to some
more generic place and perhaps be shared with the CPU
vblank evasion code/etc...
Ville Syrjälä [Mon, 24 Jun 2024 19:10:24 +0000 (22:10 +0300)]
drm/i915/dsb: Fix dewake scanline
Currently we calculate the DEwake scanline based on
the delayed vblank start, while in reality it should be computed
based on the undelayed vblank start (as that is where the DSB
actually starts). Currently it doesn't really matter as we
don't have any vblank delay configured, but that may change
in the future so let's be accurate in what we do.
We can also remove the max() as intel_crtc_scanline_to_hw()
can deal with negative numbers, which there really shouldn't
be anyway.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:23 +0000 (22:10 +0300)]
drm/i915/dsb: Shuffle code around
Relocate intel_dsb_dewake_scanline() and dsb_chicken() upwards
in the file. I need to reuse these while emitting DSB
commands, and I'd like to keep the DSB command emission
stuff more or less grouped together in the file.
Also drop the intel_ prefix from intel_dsb_dewake_scanline() since
it's all internal stuff and thus doesn't need so much namespacing.
Ville Syrjälä [Mon, 24 Jun 2024 19:10:22 +0000 (22:10 +0300)]
drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier
Currently we switch from out software idea of a scanline
to the hw's idea of a scanline during the commit phase in
_intel_dsb_commit(). While that is slightly easier due to
fastsets fiddling with the timings, we'll also need to
generate proper hw scanline numbers already when emitting
DSB scanline wait instructions. So this approach won't
do in the future. Switch to hw scanline numbers earlier.
Also intel_dsb_dewake_scanline() itself already makes
some assumptions about VRR that don't take into account
VRR toggling during fastsets, so technically delaying
the sw->hw conversion doesn't even help us.
The other reason for delaying the conversion was that we
are using intel_get_crtc_scanline() during intel_dsb_commit()
which gives us the current sw scanline. But this is pretty
low level stuff anyway so just using raw PIPEDSL reads seems
fine here, and that of course gives us the hw scanline
directly, reducing the need to do so many conversions.
v2: Return the non-hw scanline from intel_dsb_dewake_scanline()
Ville Syrjälä [Wed, 10 Jul 2024 12:41:37 +0000 (15:41 +0300)]
drm/i915: Fix readout degamma_lut mismatch on ilk/snb
On ilk/snb the pipe may be configured to place the LUT before or
after the CSC depending on various factors, but as there is only
one LUT (no split mode like on IVB+) we only advertise a gamma_lut
and no degamma_lut in the uapi to avoid confusing userspace.
This can cause a problem during readout if the VBIOS/GOP enabled
the LUT in the pre CSC configuration. The current code blindly
assigns the results of the readout to the degamma_lut, which will
cause a failure during the next atomic_check() as we aren't expecting
anything to be in degamma_lut since it's not visible to userspace.
Fix the problem by assigning whatever LUT we read out from the
hardware into gamma_lut.
Cc: stable@vger.kernel.org Fixes: d2559299d339 ("drm/i915: Make ilk_read_luts() capable of degamma readout") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11608 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240710124137.16773-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Neil Armstrong [Wed, 28 Aug 2024 16:03:39 +0000 (18:03 +0200)]
drm/panel: visionox-vtdr6130: switch to mipi_dsi wrapped functions
Make usage of the new _multi() mipi_dsi functions instead of the
deprecated macros, improving error handling and printing.
bloat-o-meter gives a 12% gain on arm64:
Function old new delta
visionox_vtdr6130_unprepare 208 204 -4
visionox_vtdr6130_prepare 1192 896 -296
Total: Before=2348, After=2048, chg -12.78%
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