Tomasz Figa [Thu, 12 Dec 2013 16:07:21 +0000 (17:07 +0100)]
ARM: dts: Add clock provider specific properties to max77686 node
This patch adds a label and #clock-cells property to device node of
max77686 PMIC to allow using it as a clock provider.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:20 +0000 (17:07 +0100)]
clk: max77686: Register OF clock provider
If max77686 chip is instantiated from device tree, it is desirable to
have an OF clock provider to allow device tree based look-up of clocks.
This patch adds OF clock provider registration to the clk-max77686
driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:19 +0000 (17:07 +0100)]
clk: max77686: Refactor driver data handling
As a prerequisite for further patch adding OF clock provider support to
the driver, this patch changes the driver to store an array of struct
clk * as driver data.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:18 +0000 (17:07 +0100)]
clk: max77686: Fix clean-up in error and remove paths
This patch fixes invalid kfree() and adds missing call to clk_unregister()
in error and remove paths in max77686_clk_probe(). While at it, error
handling is also cleaned up.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:17 +0000 (17:07 +0100)]
clk: max77686: Make max77686_clk_register() return struct clk *
As a preparation for further patches, this patch modifies the clock
registration helper function to return a pointer to the newly registered
clock. No functional change is done to the driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:16 +0000 (17:07 +0100)]
clk: max77686: Refactor successful exit of probe function
The function can simply return 0, without jumping to a separate label,
which does exactly the same. This patch does not introduce any
functional change, just a clean-up.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:15 +0000 (17:07 +0100)]
clk: max77686: Provide .recalc_rate() operation
It is usually nice to know frequency of a clock, so this patch adds a
.recalc_rate() callback returning rates of provided clocks.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:14 +0000 (17:07 +0100)]
clk: max77686: Correct callback used for checking clock status
Changing status of clock gates in max77686 requires i2c transfers, which
can sleep, so this is done in prepare and unprepare callbacks. Due to
this, checking whether whether the clock is ungated must be done
in is_prepared() callback as well, for consistency.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Sun, 29 Dec 2013 21:37:56 +0000 (13:37 -0800)]
Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi
Allwinner sunXi SoCs clock changes
This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.
Chen-Yu Tsai [Tue, 24 Dec 2013 13:26:17 +0000 (21:26 +0800)]
clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.
Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
Boris BREZILLON [Sat, 21 Dec 2013 09:34:47 +0000 (10:34 +0100)]
clk: add clk accuracy retrieval support
The clock accuracy is expressed in ppb (parts per billion) and represents
the possible clock drift.
Say you have a clock (e.g. an oscillator) which provides a fixed clock of
20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is
20Hz/20MHz = 1000 ppb (or 1 ppm).
Clock users may need the clock accuracy information in order to choose
the best clock (the one with the best accuracy) across several available
clocks.
This patch adds clk accuracy retrieval support for common clk framework by
means of a new function called clk_get_accuracy.
This function returns the given clock accuracy expressed in ppb.
In order to get the clock accuracy, this implementation adds one callback
called recalc_accuracy to the clk_ops structure.
This callback is given the parent clock accuracy (if the clock is not a
root clock) and should recalculate the given clock accuracy.
This callback is optional and may be implemented if the clock is not
a perfect clock (accuracy != 0 ppb).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Soren Brinkmann [Wed, 27 Nov 2013 20:16:23 +0000 (12:16 -0800)]
clk/zynq/clkc: Add 'fclk-enable' feature
In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.
FPGA clocks are handled following the rules below:
If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.
If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a driver for SILabs 570, 571, 598, 599 programmable oscillators.
The devices generate low-jitter clock signals and are reprogrammable via
an I2C interface.
Adding clocks from a kernel module can cause a NULL pointer
dereference if the parent of a clock is added after the clock is
added. This happens because __clk_init() iterates over the list
of orphans and reparents the orphans to the clock being
registered before creating the debugfs entry for the clock.
Create the debugfs entry first before reparenting the orphans.
Takashi Yoshii [Tue, 8 Oct 2013 05:32:17 +0000 (14:32 +0900)]
clk: emev2: Add support for emev2 SMU clocks with DT
Device tree clock binding document for EMMA Mobile EV2 SMU,
And Common clock framework based implementation of it.
Following nodes are defined to describe clock tree.
- renesas,emev2-smu
- renesas,emev2-smu-clkdiv
- renesas,emev2-smu-gclk
These bindings are designed manually based on
19UH0037EJ1000_SMU : System Management Unit User's Manual
So far, reparent is not implemented, and is fixed to index #0.
Clock tree description is not included, and should be provided
by device-tree.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Laurent Pinchart [Thu, 17 Oct 2013 21:54:07 +0000 (23:54 +0200)]
clk: shmobile: Add DIV6 clock support
DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Laurent Pinchart [Wed, 6 Nov 2013 12:14:19 +0000 (13:14 +0100)]
clk: shmobile: Add R-Car Gen2 clocks support
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Grygorii Strashko [Sat, 23 Nov 2013 21:31:12 +0000 (16:31 -0500)]
clk: keystone: gate: fix error handling on init
This patch fixes Keystone gate control clock driver initialization path:
1) clk_register_psc() returns error code and not a pure pointer, hence
its return value need to be checked using IS_ERR(clk) macro.
2) Mapped IO memory isn't unmapped in case of errors, hence fix it.
Murali Karicheri [Sat, 23 Nov 2013 21:26:52 +0000 (16:26 -0500)]
clk: keystone: use clkod register bits for postdiv
DDR3A/B, ARM and PA PLL controllers have clkod register bits for
configuring postdiv values. So use it instead of using fixed
post dividers for these pll controllers. Assume that if fixed-postdiv
attribute is not present, use clkod register value for pistdiv.
Also update the Documentation of bindings to reflect the same.
Sylwester Nawrocki [Sat, 24 Aug 2013 13:00:10 +0000 (15:00 +0200)]
clk: Implement clk_unregister
clk_unregister() is currently not implemented and it is required when
a clock provider module needs to be unloaded.
Normally the clock supplier module is prevented to be unloaded by
taking reference on the module in clk_get().
For cases when the clock supplier module deinitializes despite the
consumers of its clocks holding a reference on the module, e.g. when
the driver is unbound through "unbind" sysfs attribute, there are
empty clock ops added. These ops are assigned temporarily to struct
clk and used until all consumers release the clock, to avoid invoking
callbacks from the module which just got removed.
Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Sylwester Nawrocki [Sat, 24 Aug 2013 18:10:41 +0000 (20:10 +0200)]
clk: Add common __clk_get(), __clk_put() implementations
This patch adds common __clk_get(), __clk_put() clkdev helpers that
replace their platform specific counterparts when the common clock
API is used.
The owner module pointer field is added to struct clk so a reference
to the clock supplier module can be taken by the clock consumers.
The owner module is assigned while the clock is being registered,
in functions _clk_register() and __clk_register().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Fri, 23 Aug 2013 15:03:44 +0000 (17:03 +0200)]
clkdev: Fix race condition in clock lookup from device tree
There is currently a race condition in the device tree part of clk_get()
function, since the pointer returned from of_clk_get_by_name() may become
invalid before __clk_get() call. E.g. due to the clock provider driver
remove() callback being called in between of_clk_get_by_name() and
__clk_get().
Fix this by doing both the look up and __clk_get() operations with the
clock providers list mutex held. This ensures that the clock pointer
returned from __of_clk_get_from_provider() call and passed to __clk_get()
is valid, as long as the clock supplier module first removes its clock
provider instance and then does clk_unregister() on the corresponding
clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Fri, 23 Aug 2013 15:03:43 +0000 (17:03 +0200)]
clk: Provide not locked variant of of_clk_get_from_provider()
Add helper functions for the of_clk_providers list locking and
an unlocked variant of of_clk_get_from_provider().
These functions are intended to be used in the clkdev to avoid
race condition in the device tree based clock look up in clk_get().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Tue, 29 Oct 2013 19:51:04 +0000 (20:51 +0100)]
omap3isp: Modify clocks registration to avoid circular references
The clock core code is going to be modified so clk_get() takes
reference on the clock provider module. Until the potential circular
reference issue is properly addressed, we pass NULL as the first
argument to clk_register(), in order to disallow sub-devices taking
a reference on the ISP module back trough clk_get(). This should
prevent locking the modules in memory.
Haojian Zhuang [Wed, 13 Nov 2013 00:51:23 +0000 (08:51 +0800)]
clk: hisilicon: add common clock support
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Wei Yongjun [Tue, 29 Oct 2013 02:07:57 +0000 (03:07 +0100)]
clk: tegra: fix __clk_lookup() return value checks
In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Thierry Reding [Wed, 27 Nov 2013 16:26:03 +0000 (17:26 +0100)]
clk: tegra: Do not print errors for clk_round_rate()
clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.
Dinh Nguyen [Thu, 24 Oct 2013 08:18:30 +0000 (03:18 -0500)]
clk: socfpga: Remove check for "reg" property in socfpga_clk_init
The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().
Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Alex Elder [Wed, 27 Nov 2013 15:39:49 +0000 (09:39 -0600)]
clk: clean up everything on debugfs error
[Maybe the third time will be the charm. -Alex]
If CONFIG_COMMON_CLK_DEBUG is defined, clk_debug_create_one() is
called to populate a debugfs directory with a few entries that are
common for all clock types.
If an error happens after creating the first one debugfs_remove() is
called on the clock's directory. The problem with this is that no
cleanup is done on the debugfs files already created in that
directory, so the directory never actually gets removed. This
problem is silently ignored.
Fix this by calling debugfs_remove_recursive() instead. Reset the
clk->dentry field to null afterward, to ensure it can't be mistaken
as a valid pointer.
Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Thierry Reding [Mon, 18 Nov 2013 15:11:36 +0000 (16:11 +0100)]
clk: tegra: Initialize DSI low-power clocks
The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Thierry Reding [Tue, 29 Oct 2013 15:51:12 +0000 (16:51 +0100)]
clk: tegra: Properly setup PWM clock on Tegra30
The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Thierry Reding [Tue, 29 Oct 2013 15:51:11 +0000 (16:51 +0100)]
clk: tegra: Initialize secondary gr3d clock on Tegra30
There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Joseph Lo [Thu, 26 Sep 2013 09:46:23 +0000 (17:46 +0800)]
clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 25 Sep 2013 09:27:51 +0000 (17:27 +0800)]
clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops
Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.
Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com>
Peter De Schrijver [Wed, 4 Sep 2013 14:04:19 +0000 (17:04 +0300)]
clk: tegra: move periph clocks to common file
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Tue, 17 Sep 2013 12:42:24 +0000 (15:42 +0300)]
clk: tegra: move audio clk to common file
Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 2 Sep 2013 12:09:08 +0000 (15:09 +0300)]
clk: tegra: add header for common tegra clock IDs
Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 25 Nov 2013 12:44:13 +0000 (14:44 +0200)]
clk: tegra: use pll_ref as the pll_e parent
Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Fri, 6 Sep 2013 11:37:37 +0000 (14:37 +0300)]
clk: tegra: move some PLLC and PLLXC init to clk-pll.c
VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 2 Sep 2013 12:22:02 +0000 (15:22 +0300)]
clk: tegra: common periph_clk_enb_refcnt and clks
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Thu, 22 Aug 2013 15:44:06 +0000 (18:44 +0300)]
clk: tegra: simplify periph clock data
This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Andrew Chew [Wed, 7 Aug 2013 11:25:09 +0000 (19:25 +0800)]
clk: tegra: Set the clk parent of host1x to pll_p
The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock. We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.
Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
projects / users / jedix / linux-maple.git / log