Jeffrey Hugo [Mon, 27 Mar 2023 15:54:52 +0000 (09:54 -0600)]
accel/qaic: Add MHI controller
An AIC100 device contains a MHI interface with a number of different
channels for controlling different aspects of the device. The MHI
controller works with the MHI bus to enable and drive that interface.
AIC100 uses the BHI protocol in PBL to load SBL. The MHI controller
expects the SBL to be located at /lib/firmware/qcom/aic100/sbl.bin and
expects the MHI bus to manage the process of loading and sending SBL to
the device.
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Acked-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1679932497-30277-4-git-send-email-quic_jhugo@quicinc.com
Jeffrey Hugo [Mon, 27 Mar 2023 15:54:51 +0000 (09:54 -0600)]
accel/qaic: Add uapi and core driver file
Add the QAIC driver uapi file and core driver file that binds to the PCIe
device. The core driver file also creates the accel device and manages
all the interconnections between the different parts of the driver.
The driver can be built as a module. If so, it will be called "qaic.ko".
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Acked-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1679932497-30277-3-git-send-email-quic_jhugo@quicinc.com
Jeffrey Hugo [Mon, 27 Mar 2023 15:54:50 +0000 (09:54 -0600)]
accel/qaic: Add documentation for AIC100 accelerator driver
The Qualcomm Cloud AI 100 (AIC100) device is an Artificial Intelligence
accelerator PCIe card. It contains a number of components both in the
SoC and on the card which facilitate running workloads:
QSM: management processor
NSPs: workload compute units
DMA Bridge: dedicated data mover for the workloads
MHI: multiplexed communication channels
DDR: workload storage and memory
The Linux kernel driver for AIC100 is called "QAIC" and is located in the
accel subsystem.
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Acked-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1679932497-30277-2-git-send-email-quic_jhugo@quicinc.com
Daniel Vetter [Wed, 5 Apr 2023 13:31:05 +0000 (15:31 +0200)]
drm/atomic-helper: Don't set deadline for modesets
If the crtc is being switched on or off then the semantics of
computing the timestampe of the next vblank is somewhat ill-defined.
And indeed, the code splats with a warning in the timestamp
computation code. Specifically it hits the check to make sure that
atomic drivers have full set up the timing constants in the drm_vblank
structure, and that's just not the case before the crtc is actually
on.
For robustness it seems best to just not set deadlines for modesets.
v2: Also skip on inactive crtc (Ville)
Link: https://lore.kernel.org/dri-devel/dfc21f18-7e1e-48f0-c05a-d659b9c90b91@linaro.org/ Fixes: d39e48ca80c0 ("drm/atomic-helper: Set fence deadline for vblank") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rob Clark <robdclark@chromium.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # test patch only Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230405133105.947834-1-daniel.vetter@ffwll.ch
Daniel Vetter [Tue, 4 Apr 2023 19:40:38 +0000 (21:40 +0200)]
drm/fb-helper: fix input validation gaps in check_var
Apparently drivers need to check all this stuff themselves, which for
most things makes sense I guess. And for everything else we luck out,
because modern distros stopped supporting any other fbdev drivers than
drm ones and I really don't want to argue anymore about who needs to
check stuff. Therefore fixing all this just for drm fbdev emulation is
good enough.
Note that var->active is not set or validated. This is just control
flow for fbmem.c and needs to be validated in there as needed.
Daniel Vetter [Tue, 4 Apr 2023 19:40:37 +0000 (21:40 +0200)]
drm/fb-helper: drop redundant pixclock check from drm_fb_helper_set_par()
The fb_check_var hook is supposed to validate all this stuff. Any
errors from fb_set_par are considered driver/hw issues and resulting
in dmesg warnings.
Luckily we do fix up the pixclock already, so this is all fine.
Daniel Vetter [Tue, 4 Apr 2023 19:40:36 +0000 (21:40 +0200)]
drm/fb-helper: set x/yres_virtual in drm_fb_helper_check_var
Drivers are supposed to fix this up if needed if they don't outright
reject it. Uncovered by 6c11df58fd1a ("fbmem: Check virtual screen
sizes in fb_set_var()").
Add a panel entry with delay_200_500_e50 for the AUO NE135FBM-N41
version 8.1, found on a number of ACER laptops, including the
Swift 3 (SF313-52, SF313-53), Chromebook Spin 513 (CP513-2H) and
others.
Pin-yen Lin [Fri, 31 Mar 2023 03:02:04 +0000 (11:02 +0800)]
drm/bridge: ps8640: Use constant sleep time for polling hpd
The default hpd_wait_us in panel_edp.c is 2 seconds. This makes the
sleep time in the polling of _ps8640_wait_hpd_asserted become 200ms.
Change it to a constant 20ms to speed up the function.
Marek Vasut [Mon, 3 Apr 2023 19:02:42 +0000 (21:02 +0200)]
drm/bridge: ti-sn65dsi83: Do not generate HFP/HBP/HSA and EOT packet
Do not generate the HS front and back porch gaps, the HSA gap and
EOT packet, as per "SN65DSI83 datasheet SLLSEC1I - SEPTEMBER 2012
- REVISED OCTOBER 2020", page 22, these packets are not required.
This makes the TI SN65DSI83 bridge work with Samsung DSIM on i.MX8MN.
drm: bridge: ldb: add support for using channel 1 only
The LDB driver currently checks whether dual mode is used, otherwise it
assumes only channel 0 is in use. Add support for using only channel 1. In
device tree terms, this means linking port 2 only.
Doing this cleanly requires changing the logic of the probe functions from
this:
1. use of_graph_get_remote_node() on port 1 to find the panel
2. use drm_of_lvds_get_dual_link_pixel_order() to detect dual mode
to this:
1. use of_graph_get_remote_node() twice to find remote ports
2. reuse the result of the above to know whether each channel is enabled
and to find the panel
3. if (both channels as enabled)
use drm_of_lvds_get_dual_link_pixel_order() to detect dual mode
Also add a dev_dbg() to log the detected mode and log an error in case no
panel was found (no channel enabled).
Karol Wachowski [Mon, 3 Apr 2023 12:15:45 +0000 (14:15 +0200)]
accel/ivpu: Remove D3hot delay for Meteorlake
VPU on MTL has hardware optimizations and does not require 10ms
D0 - D3hot transition delay imposed by PCI specification (PCIe
r6.0, sec 5.9.) .
The delay removal is traditionally done by adding PCI ID to
quirk_remove_d3hot_delay() in drivers/pci/quirks.c . But since
we do not need that optimization before driver probe and we
can better specify in the ivpu driver on what (future) hardware
use the optimization, we do not use quirk_remove_d3hot_delay()
for that.
Marek Vasut [Tue, 21 Feb 2023 20:04:07 +0000 (21:04 +0100)]
dt-bindings: display: Start the info graphics with HS/VS change
The VS signal change is synchronized to HS signal change, start the
info graphics with that event, instead of having that event occur in
the middle of it.
Scope trace of DPI bus with HS/VS active HIGH looks as follows:
________________...__
VS...___/__ __ \______...
HS...___/ \_______/ \__...__/ \___...
^ ^
| |
| Used to start here -'
|
'--- Start info graphics here
The TC358767/TC358867/TC9595 are capable of DSI burst mode, which
is more energy efficient than the non-burst modes. Make use of it.
The TC358767/TC358867/TC9595 are capable of DSI non-continuous clock,
since it sources the internal PLL clock from external clock source.
The DSI non-continuous clock further reduces power utilization.
The TC358767/TC358867/TC9595 may use DSI LPM for command transmissions,
make sure this is configured correctly in the DSI mode flags.
Simon Ser [Thu, 2 Mar 2023 14:35:13 +0000 (14:35 +0000)]
drm/vram-helper: turn on PRIME import/export
We don't populate drm_driver.gem_prime_import_sg_table so only
DMA-BUFs exported from our own device can be imported. We don't
populate drm_gem_object_funcs.get_sg_table so DMA-BUFs cannot be
imported into another device. Still, this is useful to user-space
to share buffers between processes and between API boundaries
(e.g. wlroots hard-requires PRIME import/export support).
v2: expand commit message
Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Tian Tao <tiantao6@hisilicon.com> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Hans de Goede <hdegoede@redhat.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302143502.500661-2-contact@emersion.fr
Simon Ser [Thu, 2 Mar 2023 14:35:09 +0000 (14:35 +0000)]
drm/prime: reject DMA-BUF attach when get_sg_table is missing
drm_gem_map_dma_buf() requires drm_gem_object_funcs.get_sg_table
to be implemented, or else WARNs.
Allow drivers to leave this hook unimplemented to implement purely
local DMA-BUFs (ie, DMA-BUFs which cannot be imported anywhere
else but the device which allocated them). In that case, reject
imports to other devices in drm_gem_map_attach().
v2: new patch
v3: use ENOSYS
Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Tian Tao <tiantao6@hisilicon.com> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Hans de Goede <hdegoede@redhat.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302143502.500661-1-contact@emersion.fr
Francesco Dolcini [Thu, 30 Mar 2023 09:31:31 +0000 (11:31 +0200)]
drm/bridge: lt8912b: Fix DSI Video Mode
LT8912 DSI port supports only Non-Burst mode video operation with Sync
Events and continuous clock on clock lane, correct dsi mode flags
according to that removing MIPI_DSI_MODE_VIDEO_BURST flag.
Erico Nunes [Sun, 12 Mar 2023 23:30:52 +0000 (00:30 +0100)]
drm/lima: add show_fdinfo for drm usage stats
This exposes an accumulated active time per client via the fdinfo
infrastructure per execution engine, following
Documentation/gpu/drm-usage-stats.rst.
In lima, the exposed execution engines are gp and pp.
Erico Nunes [Sun, 12 Mar 2023 23:30:50 +0000 (00:30 +0100)]
drm/lima: add usage counting method to ctx_mgr
lima maintains a context manager per drm_file, similar to amdgpu.
In order to account for the complete usage per drm_file, all of the
associated contexts need to be considered.
Previously released contexts also need to be accounted for but their
drm_sched_entity info is gone once they get released, so account for it
in the ctx_mgr.
AngeloGioacchino Del Regno [Thu, 23 Mar 2023 09:08:22 +0000 (10:08 +0100)]
drm/panfrost: Add basic support for speed binning
Some SoCs implementing ARM Mali GPUs are subject to speed binning:
this means that some versions of the same SoC model may need to be
limited to a slower frequency compared to the other:
this is being addressed by reading nvmem (usually, an eFuse array)
containing a number that identifies the speed binning of the chip,
which is usually related to silicon quality.
To address such situation, add basic support for reading the
speed-bin through nvmem, as to make it possible to specify the
supported hardware in the OPP table for GPUs.
This commit also keeps compatibility with any platform that does
not specify (and does not even support) speed-binning.
AngeloGioacchino Del Regno [Thu, 23 Mar 2023 09:08:21 +0000 (10:08 +0100)]
dt-bindings: gpu: mali-bifrost: Document nvmem for speedbin support
Some SoCs implementing ARM Mali GPUs may be subject to speed binning
and the usable bin is read from nvmem: document the addition of nvmem
and nvmem-cells for 'speed-bin'.
Rob Herring [Fri, 10 Mar 2023 14:47:05 +0000 (08:47 -0600)]
drm: Use of_property_read_bool() for boolean properties
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties.
Convert reading boolean properties to of_property_read_bool().
The nt36672a bindings were added with a mistake on VDDIO supply calling
it in one place vddio and in other vddi0. Typical name is rather vddio
which is also now used by DTS (sdm845-xiaomi-beryllium-common.dtsi) and
Linux driver.
Fixes: c2abcf30efb8 ("dt-bindings: display: novatek,nt36672a: Fix unevaluated properties warning") Fixes: 9528a02430df ("dt-bindings: display: panel: Add bindings for Novatek nt36672a") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
Daniel Vetter [Wed, 29 Mar 2023 14:00:23 +0000 (16:00 +0200)]
Merge v6.3-rc4 into drm-next
I just landed the fence deadline PR from Rob that a bunch of drivers
want/need to apply driver-specific patches. Backmerge -rc4 so that
they don't have to be stuck on -rc2 for no reason at all.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 29 Mar 2023 13:45:37 +0000 (15:45 +0200)]
Merge tag 'dma-fence-deadline' of https://gitlab.freedesktop.org/drm/msm into drm-next
This series adds a deadline hint to fences, so realtime deadlines
such as vblank can be communicated to the fence signaller for power/
frequency management decisions.
This is partially inspired by a trick i915 does, but implemented
via dma-fence for a couple of reasons:
1) To continue to be able to use the atomic helpers
2) To support cases where display and gpu are different drivers
See https://patchwork.freedesktop.org/series/93035/
This does not yet add any UAPI, although this will be needed in
a number of cases:
1) Workloads "ping-ponging" between CPU and GPU, where we don't
want the GPU freq governor to interpret time stalled waiting
for GPU as "idle" time
2) Cases where the compositor is waiting for fences to be signaled
before issuing the atomic ioctl, for example to maintain 60fps
cursor updates even when the GPU is not able to maintain that
framerate.
Rob Clark [Tue, 21 Sep 2021 16:35:50 +0000 (09:35 -0700)]
drm/scheduler: Add fence deadline support
As the finished fence is the one that is exposed to userspace, and
therefore the one that other operations, like atomic update, would
block on, we need to propagate the deadline from from the finished
fence to the actual hw fence.
v2: Split into drm_sched_fence_set_parent() (ckoenig)
v3: Ensure a thread calling drm_sched_fence_set_deadline_finished() sees
fence->parent set before drm_sched_fence_set_parent() does this
test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT).
Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Rob Clark [Tue, 28 Feb 2023 18:10:11 +0000 (10:10 -0800)]
dma-buf/sync_file: Surface sync-file uABI
We had all of the internal driver APIs, but not the all important
userspace uABI, in the dma-buf doc. Fix that. And re-arrange the
comments slightly as otherwise the comments for the ioctl nr defines
would not show up.
v2: Fix docs build warning coming from newly including the uabi header
in the docs build
Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Rob Herring [Fri, 10 Mar 2023 14:47:05 +0000 (08:47 -0600)]
drm: Use of_property_present() for testing DT property presence
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties. As
part of this, convert of_get_property/of_find_property calls to the
recently added of_property_present() helper when we just want to test
for presence of a property and nothing more.
Daniel Vetter [Tue, 28 Mar 2023 17:23:05 +0000 (19:23 +0200)]
Merge tag 'exynos-drm-next-for-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
A patch series for moving MIPI-DSI driver for Exynos DRM to drm/bridge
directory so that I.MX SoC family can also share the same device driver.
Samsung MIPI DSIM device is a common IP that can be used by Exynos and I.MX8M
Mini/Nano/Plus SoC. Regarding this, this patch series has added several
things below to existing MIPI DSI driver,
- Add exynos_dsi_type enum type to provide controller data from different
platforms.
- Add two pipeline detection ways support - existing Exynos DSI child node
and I.MX family of-graph port or ports.
- Consider component and bridged based DRM drivers.
- Add device tree binding support of I.MX family.
Marek Vasut [Wed, 8 Mar 2023 16:39:53 +0000 (22:09 +0530)]
drm: bridge: samsung-dsim: Add i.MX8M Plus support
Add extras to support i.MX8M Plus. The main change is the removal of
HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise
the implementation of this IP in i.MX8M Plus is very much compatible
with the i.MX8M Mini/Nano one.
Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <m.szyprowski@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:49 +0000 (22:09 +0530)]
drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.
In order to access this DSI controller between various platform SoCs,
the ideal way to incorporate this in the drm stack is via the drm bridge
driver.
We already have a consolidated code for supporting component and bridge
based DRM drivers, so keep the exynos component based code in existing
exynos_drm_dsi.c and move generic bridge code as part of samsung-dsim.c
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:48 +0000 (22:09 +0530)]
drm: exynos: dsi: Add host helper for te_irq_handler
IRQ handler for te-gpio seems to be common across DSIM host.
However, Exynos is handling this via CRTC drivers but there is no clear
evidence on how the same has been handled in i.MX8MM. Keeping the handler
as-it-is can be a viable option but adding DSIM bridge core in upcoming
patches is not possible to call Exynos CRTC handler as DSIM bridge has
to be common across DRM bridge core instead of platform specific DRM
drivers like Exynos here.
So, this patch handles the handler via platform host helper, so-that
handling platform specific hook across Exynos and generic can be
reasonable till it makes it generic across all platforms.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:47 +0000 (22:09 +0530)]
drm: exynos: dsi: Consolidate component and bridge
DSI host registration, attach and detach operations are quite
different for the component and bridge-based DRM drivers.
Supporting generic bridge driver to use both component and bridge
based DRM drivers can be tricky and would require additional host
related operation hooks.
Add host operation hooks for registering and unregistering Exynos
and generic drivers, where Exynos hooks are used in existing Exynos
component based DRM drivers and generic hooks are used in i.MX8M
bridge based DRM drivers.
Add host attach and detach operation hooks for Exynos component
DRM drivers and those get invoked while DSI core host attach and
detach gets called.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:46 +0000 (22:09 +0530)]
drm: exynos: dsi: Add atomic_get_input_bus_fmts
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
proper input format from list of supported output formats.
This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the other component closer to pipeline
components.
List of Pixel formats are taken from,
AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
3.7.4 Pixel formats
Table 14. DSI pixel packing formats
Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:45 +0000 (22:09 +0530)]
drm: exynos: dsi: Add input_bus_flags
LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting
the i.MX8M Mini/Nano DSI host to add additional Data Enable signal
active low (DE_LOW). This makes the valid data transfer on each
horizontal line.
So, add additional bus flags DE_LOW setting via input_bus_flags
for i.MX8M Mini/Nano platforms.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:44 +0000 (22:09 +0530)]
drm: exynos: dsi: Add atomic check
Look like an explicit fixing up of mode_flags is required for DSIM IP
present in i.MX8M Mini/Nano SoCs.
At least the LCDIF + DSIM needs active low sync polarities in order
to correlate the correct sync flags of the surrounding components in
the chain to make sure the whole pipeline can work properly.
On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
Rev. 3, 11/2020 says.
"13.6.3.5.2 RGB interface
Vsync, Hsync, and VDEN are active high signals."
i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
3.6.3.5.2 RGB interface
i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
13.6.2.7.2 RGB interface
both claim "Vsync, Hsync, and VDEN are active high signals.", the
LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
No clear evidence about whether it can be documentation issues or
something, so added proper comments on the code.
Comments are suggested by Marek Vasut.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Host transfer() in the DSI master will invoke only when the DSI commands
are sent from DSI devices like DSI Panel or DSI bridges and this host
the transfer wouldn't invoke for I2C-based-DSI bridge drivers.
Handling DSI host initialization in transfer calls misses the controller
setup for I2C configured DSI bridges.
This patch updates the DSI host initialization by calling host to init
from bridge pre_enable as the bridge pre_enable API is invoked by core
as it is common across all classes of DSI device drivers.
The host init during pre_enable is conditional and not invoked for Exynos
as existing downstream drm panels and bridges in Exynos are expecting
the host initialization during DSI transfer.
Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Look like PLL PMS_P offset value varies between platforms that have
Samsung DSIM IP.
However, there is no clear evidence for it as both Exynos and i.MX
8M Mini Application Processor Reference Manual is still referring
the PMS_P offset as 13.
The offset 13 is not working for i.MX8M Mini SoCs but the downstream
NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms
[1] [2].
PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P()
with offset 13 and then an additional offset of one bit added in
sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS().
Not sure whether it is reference manual documentation or something
else but this patch trusts the downstream code and handle PLL_P offset
via platform driver data so-that imx8mm driver data shall use
pll_p_offset to 14.
Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos.
Jagan Teki [Wed, 8 Mar 2023 16:39:40 +0000 (22:09 +0530)]
drm: exynos: dsi: Mark PHY as optional
The same Samsung MIPI DSIM master can also be used in NXP's
i.MX8M Mini/Nano/Plus SoC.
In i.MX8M Mini/Nano/Plus SoC the DSI Phy requires a MIPI DPHY
bit to reset in order to activate the PHY and that can be done
via upstream i.MX8M blk-ctrl driver.
So, mark the phy get as optional.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:39 +0000 (22:09 +0530)]
drm: exynos: dsi: Lookup OF-graph or Child node devices
In general, for MIPI DSI there are three ways to represent the
pipeline for an upstream bridge to find the connected downstream
panel or bridge.
1. Child panel or bridge as a conventional device tree child node.
2. Child panel or bridge as an OF-graph port node.
3. Child panel or bridge as an OF-graph ports node.
There are three different downstream panels or bridges that are
possible to connect an upstream DSI host bridge - DSI Panel,
DSI Bridge, and I2C-Configured DSI bridge.
An example of the downstream panel represented as a child node,
In, summary it is possible to represent all three downstream slaves
devices using OF-graph port or ports node however only DSI Panel and
DSI Bridge are possible but not possible to represent I2C-Configured
DSI bridge child nodes since I2C-Configure bridges are child of I2C
node, not upstream DSI host bridge and it is must represent them
endpoint port linking.
This indeed means, the OF-graph port or ports representation is
mandatory for I2C-Configured DSI bridges.
This patch tries to add an OF-graph port or ports representation
detection code on top of existing child node detection.
It is possible to replace the entire detection code using existing
drm_of helper drm_of_find_panel_or_bridge but it will break the
Exynos DSI since the pipeline doesn't support OF-graph port or ports
node.
Overall, this patch has a combination of child and OF-graph pipeline
detections in order to support the backward compatibility of Exynos
DSI child node and i.MX8M Mini/Nano/Plus OF-graph port or ports
node pipelines.
This is the first common DSI host bridge driver that needs to support
all possible downstream connection pipeline combinations.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Bjorn Andersson [Fri, 24 Mar 2023 16:59:09 +0000 (22:29 +0530)]
drm/panel-edp: Add B133UAN01.0 edp panel entry
This panel is found in Lenovo Flex 5G laptop, so add the entry for it
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230324165909.131831-1-vkoul@kernel.org
Caio Novais [Sat, 25 Mar 2023 13:15:32 +0000 (10:15 -0300)]
drm/scheduler: Fix variable name in function description
Compiling AMD GPU drivers displays two warnings:
drivers/gpu/drm/scheduler/sched_main.c:738: warning: Function parameter or member 'file' not described in 'drm_sched_job_add_syncobj_dependency'
drivers/gpu/drm/scheduler/sched_main.c:738: warning: Excess function
parameter 'file_private' description in
'drm_sched_job_add_syncobj_dependency'
Get rid of them by renaming the variable name on the function description
Hsin-Yi Wang [Mon, 27 Mar 2023 04:48:05 +0000 (12:48 +0800)]
drm/bridge: it6505: Add range and selector_reg
There are 2 banks on it6505, and when writing to different bank,
REG_BANK_SEL needs to be set to the targeted bank. The current code set
this additionally, which causes a race condition when a process is
writing bank 0 registers while another process set the bank to 1. Set
ranges in regmap config so the regmap API would handle the bank changes.
Linus Torvalds [Sun, 26 Mar 2023 17:22:44 +0000 (10:22 -0700)]
Merge tag 'usb-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt driver fixes from Greg KH:
"Here are a small set of USB and Thunderbolt driver fixes for reported
problems and a documentation update, for 6.3-rc4.
Included in here are:
- documentation update for uvc gadget driver
- small thunderbolt driver fixes
- cdns3 driver fixes
- dwc3 driver fixes
- dwc2 driver fixes
- chipidea driver fixes
- typec driver fixes
- onboard_usb_hub device id updates
- quirk updates
All of these have been in linux-next with no reported problems"
* tag 'usb-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (30 commits)
usb: dwc2: fix a race, don't power off/on phy for dual-role mode
usb: dwc2: fix a devres leak in hw_enable upon suspend resume
usb: chipidea: core: fix possible concurrent when switch role
usb: chipdea: core: fix return -EINVAL if request role is the same with current role
thunderbolt: Rename shadowed variables bit to interrupt_bit and auto_clear_bit
thunderbolt: Disable interrupt auto clear for rings
thunderbolt: Use const qualifier for `ring_interrupt_index`
usb: gadget: Use correct endianness of the wLength field for WebUSB
uas: Add US_FL_NO_REPORT_OPCODES for JMicron JMS583Gen 2
usb: cdnsp: changes PCI Device ID to fix conflict with CNDS3 driver
usb: cdns3: Fix issue with using incorrect PCI device function
usb: cdnsp: Fixes issue with redundant Status Stage
MAINTAINERS: make me a reviewer of USB/IP
thunderbolt: Use scale field when allocating USB3 bandwidth
thunderbolt: Limit USB3 bandwidth of certain Intel USB4 host routers
thunderbolt: Call tb_check_quirks() after initializing adapters
thunderbolt: Add missing UNSET_INBOUND_SBTX for retimer access
thunderbolt: Fix memory leak in margining
usb: dwc2: drd: fix inconsistent mode if role-switch-default-mode="host"
docs: usb: Add documentation for the UVC Gadget
...
Linus Torvalds [Sun, 26 Mar 2023 16:01:24 +0000 (09:01 -0700)]
Merge tag 'x86_urgent_for_v6.3_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Borislav Petkov:
- Add a AMX ptrace self test
- Prevent a false-positive warning when retrieving the (invalid)
address of dynamic FPU features in their init state which are not
saved in init_fpstate at all
- Randomize per-CPU entry areas only when KASLR is enabled
* tag 'x86_urgent_for_v6.3_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
selftests/x86/amx: Add a ptrace test
x86/fpu/xstate: Prevent false-positive warning in __copy_xstate_uabi_buf()
x86/mm: Do not shuffle CPU entry areas without KASLR
Linus Torvalds [Sun, 26 Mar 2023 15:56:09 +0000 (08:56 -0700)]
Merge tag 'smb3-client-fixes-6.3-rc3' of git://git.samba.org/sfrench/cifs-2.6
Pull cifs client fixes from Steve French:
"Twelve cifs/smb3 client fixes (most also for stable)
- forced umount fix
- fix for two perf regressions
- reconnect fixes
- small debugging improvements
- multichannel fixes"
* tag 'smb3-client-fixes-6.3-rc3' of git://git.samba.org/sfrench/cifs-2.6:
smb3: fix unusable share after force unmount failure
cifs: fix dentry lookups in directory handle cache
smb3: lower default deferred close timeout to address perf regression
cifs: fix missing unload_nls() in smb2_reconnect()
cifs: avoid race conditions with parallel reconnects
cifs: append path to open_enter trace event
cifs: print session id while listing open files
cifs: dump pending mids for all channels in DebugData
cifs: empty interface list when server doesn't support query interfaces
cifs: do not poll server interfaces too regularly
cifs: lock chan_lock outside match_session
cifs: check only tcon status on tcon related functions
Laurent Pinchart [Wed, 22 Feb 2023 03:49:39 +0000 (05:49 +0200)]
drm: rcar-du: Write correct values in DORCR reserved fields
The DORCR register controls the routing of clocks and data between DU
channels within a group. For groups that contain a single channel,
there's no routing option to control, and some fields of the register
are then reserved. On Gen2 those reserved fields are documented as
required to be set to 0, while on Gen3 and newer the PG1T, DK1S and PG1D
reserved fields must be set to 1.
The DU driver initializes the DORCR register in rcar_du_group_setup(),
where it ignores the PG1T, DK1S and PG1D, and then configures those
fields to the correct value in rcar_du_group_set_routing(). This hasn't
been shown to cause any issue, but prevents certifying that the driver
complies with the documentation in safety-critical use cases.
As there is no reasonable change that the documentation will be updated
to clarify that those reserved fields can be written to 0 temporarily
before starting the hardware, make sure that the registers are always
set to valid values.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Laurent Pinchart [Wed, 22 Feb 2023 22:08:14 +0000 (00:08 +0200)]
drm: rcar-du: Rename DORCR fields to make them 0-based
The DORCR fields were documented in the R-Car H1 datasheet with 1-based
named, and then got renamed to 0-based in Gen2. The 0-based names are
used for Gen3 and Gen4, making H1 an outlier. Rename the field macros to
make them 0-based, in order to increase readability of the code when
comparing it with the documentation.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Laurent Pinchart [Wed, 22 Feb 2023 03:54:03 +0000 (05:54 +0200)]
drm: rcar-du: Disable alpha blending for DU planes used with VSP
When the input to a DU channel comes from a VSP, the DU doesn't perform
any blending operation. Select XRGB8888 instead of ARGB8888 to ensure
that the corresponding registers don't get written with invalid values.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Laurent Pinchart [Wed, 22 Feb 2023 03:49:39 +0000 (05:49 +0200)]
drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3
The ESCR and OTAR registers are not present in all DU channels on Gen3
SoCs. ESCR only exists in channels that can be routed to an LVDS or
DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing
those registers for other channels. This replaces the DU gen check, as
Gen4 doesn't have LVDS or DPAD outputs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Laurent Pinchart [Mon, 13 Feb 2023 13:25:15 +0000 (15:25 +0200)]
drm: rcar-du: lvds: Fix LVDS PLL disable on D3/E3
On R-Car D3 and E3, the LVDS encoder provides the dot (pixel) clock to
the DU, regardless of whether the LVDS output is used or not. When using
the DPAD (RGB) output, the DU driver thus enables and disables the LVDS
PLL manually, while when using the LVDS output, it lets the LVDS bridge
driver handle the PLL configuration internally as part of the atomic
enable and disable operations.
This causes an issue when using the LVDS output. As bridges are disabled
before CRTCs, the current implementation violates the enable/disable
sequences documented in the hardware datasheet, which requires the dot
clock to be enabled before the CRTC is started and disabled after it
gets stopped.
Fix the problem by enabling/disabling the LVDS PLL manually from the DU
regardless of which output is used, and skipping the PLL handling in the
LVDS bridge atomic enable and disable operations.
This is however not enough. Disabling the LVDS encoder while leaving the
PLL on still results in a vertical blanking wait timeout when disabling
the DU. Investigation showed that the culprit is the LVEN bit. For an
unclear reason, clearing the bit when disabling the LVDS encoder blocks
vertical blanking interrupts. We thus have to delay disabling the whole
LVDS encoder, not just disabling the PLL, until the DU is disabled.
We could split the LVDS disable sequence by clearing the LVRES bit in
the LVDS bridge atomic disable handler, and delaying the rest of the
operations, in order to disable the LVDS output at bridge atomic disable
time, before stopping the CRTC. This would make the code more complex,
without a clear benefit, so keep the implementation simple(r).
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Laurent Pinchart [Mon, 13 Feb 2023 23:19:17 +0000 (01:19 +0200)]
drm: rcar-du: lvds: Move LVDS enable code to separate code section
To prepare for a rework of the LVDS disable code, which will need to be
called from rcar_lvds_pclk_disable(), move the LVDS enable code,
currently stored in the __rcar_lvds_atomic_enable() function, to a
separate code section separate from bridge operations. It will be then
extended with the LVDS disable code.
As part of this rework the __rcar_lvds_atomic_enable() function is
renamed to rcar_lvds_enable() to more clearly indicate its purpose.
Laurent Pinchart [Mon, 13 Feb 2023 23:07:18 +0000 (01:07 +0200)]
drm: rcar-du: lvds: Call function directly instead of through pointer
When disabling the companion bridge in rcar_lvds_atomic_disable(),
there's no need to go through the bridge's operations to call
.atomic_disable(). Call rcar_lvds_atomic_disable() on the companion
directly.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Linus Torvalds [Sat, 25 Mar 2023 20:12:36 +0000 (13:12 -0700)]
Merge tag 'xfs-6.3-fixes-7' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux
Pull yet more xfs bug fixes from Darrick Wong:
"The first bugfix addresses a longstanding problem where we use the
wrong file mapping cursors when trying to compute the speculative
preallocation quantity. This has been causing sporadic crashes when
alwayscow mode is engaged.
The other two fixes correct minor problems in more recent changes.
- Fix the new allocator tracepoints because git am mismerged the
changes such that the trace_XXX got rebased to be in function YYY
instead of XXX
- Ensure that the perag AGFL_RESET state is consistent with whatever
we've just read off the disk
- Fix a bug where we used the wrong iext cursor during a write begin"
* tag 'xfs-6.3-fixes-7' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux:
xfs: fix mismerged tracepoints
xfs: clear incore AGFL_RESET state if it's not needed
xfs: pass the correct cursor to xfs_iomap_prealloc_size
Linus Torvalds [Sat, 25 Mar 2023 19:57:34 +0000 (12:57 -0700)]
Merge tag 'xfs-6.3-fixes-4' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux
Pull xfs percpu counter fixes from Darrick Wong:
"We discovered a filesystem summary counter corruption problem that was
traced to cpu hot-remove racing with the call to percpu_counter_sum
that sets the free block count in the superblock when writing it to
disk. The root cause is that percpu_counter_sum doesn't cull from
dying cpus and hence misses those counter values if the cpu shutdown
hooks have not yet run to merge the values.
I'm hoping this is a fairly painless fix to the problem, since the
dying cpu mask should generally be empty. It's been in for-next for a
week without any complaints from the bots.
- Fix a race in the percpu counters summation code where the
summation failed to add in the values for any CPUs that were dying
but not yet dead. This fixes some minor discrepancies and incorrect
assertions when running generic/650"
* tag 'xfs-6.3-fixes-4' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux:
pcpcntr: remove percpu_counter_sum_all()
fork: remove use of percpu_counter_sum_all
pcpcntrs: fix dying cpu summation race
cpumask: introduce for_each_cpu_or
Linus Torvalds [Sat, 25 Mar 2023 19:51:25 +0000 (12:51 -0700)]
Merge tag 'xfs-6.3-fixes-3' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux
Pull xfs fixes from Darrick Wong:
"This batch started with some debugging enhancements to the new
allocator refactoring that we put in 6.3-rc1 to assist developers in
rebasing their dev branches.
As for more serious code changes -- there's a bug fix to make the
lockless allocator scan the whole filesystem before resorting to the
locking allocator. We're also adding a selftest for the venerable
directory/xattr hash function to make sure that it produces consistent
results so that we can address any fallout as soon as possible.
- Add a few debugging assertions so that people (me) trying to port
code to the new allocator functions don't mess up the caller
requirements
- Relax some overly cautious lock ordering enforcement in the new
allocator code, which means that file allocations will locklessly
scan for the best space they can get before backing off to the
traditional lock-and-really-get-it behavior
- Add tracepoints to make it easier to trace the xfs allocator
behavior
- Actually test the dir/xattr hash algorithm to make sure it produces
consistent results across all the platforms XFS supports"
* tag 'xfs-6.3-fixes-3' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux:
xfs: test dir/attr hash when loading module
xfs: add tracepoints for each of the externally visible allocators
xfs: walk all AGs if TRYLOCK passed to xfs_alloc_vextent_iterate_ags
xfs: try to idiot-proof the allocators
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