Jani Nikula [Thu, 30 Sep 2021 11:24:32 +0000 (14:24 +0300)]
drm/i915/dsi: fuse dsi_send_pkt_payld() and add_payld_to_queue()
Having two functions for this seems like excess duplication and
parameter juggling. Merge them together.
While at it, drop the extra error message, as wait_for_payload_credits()
already prints an error, and switch from incidental -EPERM (i.e. -1) to
actual error codes.
Jani Nikula [Thu, 30 Sep 2021 09:22:59 +0000 (12:22 +0300)]
drm/i915/pps: move pps (panel) modeset asserts to intel_pps.c
Move assert_panel_unlocked() to intel_pps.c and rename
assert_pps_unlocked(). Keep the functionality and the assert code
together.
There's still a bit of a split between the eDP PPS usage in intel_pps.c
and all the other PPS usage, and assert_pps_unlocked() is arguably more
related to the latter. However, intel_pps.c is the best fit for anything
touching the PPS registers.
José Roberto de Souza [Thu, 30 Sep 2021 00:14:07 +0000 (17:14 -0700)]
drm/i915/display/adlp: Allow PSR2 to be enabled
With all the recent fixes PSR2 is properly working in Alderlake-P but
due to some issues that don't have software workarounds it will not be
supported in display steppings older than B0.
Even with this patch PSR2 will no be enabled by default in ADL-P, it
still requires enable_psr2_sel_fetch to be set to true, what some
of our tests does.
José Roberto de Souza [Thu, 30 Sep 2021 00:14:06 +0000 (17:14 -0700)]
drm/i915/display/adlp: Optimize PSR2 power-savings in corner cases
The Wa_14014971508 is required to fix scanout when a feature that i915
do not support is enabled and this feature is not planned to be enabled
for adlp.
Keeping this workaround enabled can badly hurt power-savings when
a full frame fetch is required(see psr2_sel_fetch_plane_state_supported()
and psr2_sel_fetch_pipe_state_supported()).
Here a example that could badly hurt power-savings, userspace does
a page flip to a rotated plane, so CONTINUOS_FULL_FRAME set.
But then for a whole 30 seconds nothing in the screen requires updates
but because CONTINUOS_FULL_FRAME is set, it will not go into DC5/DC6.
Reverting Wa_14014971508 fixes that, as only a single frame will be
sent and then display can go to DC5/DC6 for those 30 seconds of
idleness.
José Roberto de Souza [Thu, 30 Sep 2021 00:14:05 +0000 (17:14 -0700)]
drm/i915/display: Fix glitches when moving cursor with PSR2 selective fetch enabled
Legacy cursor APIs are handled by intel_legacy_cursor_update(), that
calls drm_atomic_helper_update_plane() when going through the
slow/atomic path to update cursor, what was the case for PSR2
selective fetch.
drm_atomic_helper_update_plane() sets
drm_atomic_state->legacy_cursor_update to true when updating the
cursor plane, to allow several cursor updates to happen within the
same frame, as userspace does that.
If drivers waited for a vblank increment at the end of every cursor
movement that would cause a visible lag in the cursor.
But this optimization do not properly work with PSR2 selective fetch
dirt area calculation, for example if within a single frame the cursor
had 3 moves the final dirt area programmed to PSR2_MAN_TRK_CTL would
be based in the second movement as old state and third movement as new
state, not updating the area where cursor was in the first state.
So here switching back to the fast path approach in
intel_legacy_cursor_update() and handling cursor movements as
frontbuffer rendering(psr_force_hw_tracking_exit()), that is not the
most optimal for power-savings but is the solution that we have until
mailbox style updates is implemented.
Also removing the cursor workaround as not it is properly undestand
the issue and is know that it will never cover all the cases.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210930001409.254817-5-jose.souza@intel.com
José Roberto de Souza [Thu, 30 Sep 2021 00:14:04 +0000 (17:14 -0700)]
drm/i915/display: Handle frontbuffer rendering when PSR2 selective fetch is enabled
When PSR2 selective fetch is enabled writes to CURSURFLIVE alone do
not causes the panel to be updated when doing frontbuffer rendering.
From what I was able to figure from experiments the writes to
CURSURFLIVE takes PSR2 from deep sleep but panel is not updated
because PSR2_MAN_TRK_CTL has no start and end region set.
As we don't have the dirt area from current flush and invalidate API
and even if we did userspace could do several draws to frontbuffer and
we would need a way to append all the damaged areas of all the draws
that need to be part of next frame.
So here only programing PSR2_MAN_TRK_CTL to do a single full frame
fetch.
It is a safe approach as if scanout is in the visible area
the single full frame will only be visible for hardware in the next
frame because of the double buffering, and if scanout is in vblank
area it will be draw in the current frame.
No need to disable PSR and wait a few miliseconds to enable it again.
José Roberto de Souza [Thu, 30 Sep 2021 00:14:03 +0000 (17:14 -0700)]
drm/i915/display: Drop unnecessary frontbuffer flushes
This unnecessary flushes are hurting power-savings are it causes
features like PSR, FBC and DRRS to disable it self to handle
frontbuffer rendering, below some explanation of why each removed
call is not necessary.
The flush in intel_prepare_plane_fb() is not required as framebuffer
will be flipped and power-saving features do the proper flip handling
in hardware.
intel_find_initial_plane_obj() flush is not required because it is
only executed during driver load and at this point the power-saving
features are not even enabled.
And the last one intelfb_create(), is also not required as at this
point the fbdev was just allocated, userspace will draw on
it what will trigger frontbuffer invalidates and flushes later on.
Gwan-gyeong Mun [Thu, 30 Sep 2021 00:14:02 +0000 (17:14 -0700)]
drm/i915/display/psr: Do full fetch when handling multi-planar formats
We are still missing the PSR2 selective fetch handling of multi-planar
formats but until proper handle is added we can workaround it by
doing full frames fetch when state has such formats.
José Roberto de Souza [Thu, 30 Sep 2021 00:14:01 +0000 (17:14 -0700)]
drm/i915/display/psr: Handle plane and pipe restrictions at every page flip
PSR2 selective is not supported over rotated and scaled planes.
We had the rotation check in intel_psr2_sel_fetch_config_valid()
but that code path is only execute when a modeset is needed and
those plane parameters can change without a modeset.
Pipe selective fetch restrictions are also needed, it could be added
in intel_psr_compute_config() but pippe scaling is computed after
it is executed, so leaving as is for now.
There is no much loss in this approach as it would cause selective
fetch to not enabled as for alderlake-P and newer will cause it to
switch to PSR1 that will have the same power-savings as do full pipe
fetch.
Also need to check those restricions in the second
for_each_oldnew_intel_plane_in_state() loop because the state could
only have a plane that is not affected by those restricitons but
the damaged area intersect with planes that has those restrictions,
so a full pipe fetch is required.
Ville Syrjälä [Thu, 30 Sep 2021 13:43:10 +0000 (16:43 +0300)]
drm/i915: Nuke local copies/pointers of intel_dp->DP
Get rid of the local copies and pointers of intel_dp->DP and
instead just poke at it directly. Makes it much easier to see
where it actually gets used/modified.
Ville Syrjälä [Thu, 30 Sep 2021 13:43:09 +0000 (16:43 +0300)]
drm/i915: Remove DP_PORT_EN stuff from link training code
Setting DP_PORT_EN in intel_dp->DP is already handled by
intel_dp_enable_port() so there is no point in setting it also
from the link training code.
For DDI platforms a bit with that name doesn't even exist. The
counterpart is DDI_BUF_CTL_ENABLE, which is already set up by
intel_ddi_prepare_link_retrain(). Fortunately it is the same bit
so there was no harm in doing this from the platform independent
code as well. But it's just confusing when platform independent
code sets platform specific bits in intel_dp->DP. Just get rid
of it.
I want intel_dp->DP to be fully populated by the time the
initial vswing programming happens. To that end move the
intel_ddi_init_dp_buf_reg() call to an earlier spot.
Additionally we don't want intel_ddi_init_dp_buf_reg() to
set DDI_BUF_CTL_ENABLE since the port should only get enabled
at the start of link training (see intel_ddi_prepare_link_retrain()).
So any earlier write to the register should not set the enable bit.
Ville Syrjälä [Thu, 30 Sep 2021 13:43:07 +0000 (16:43 +0300)]
drm/i915: Clear leftover DP vswing/preemphasis values before modeset
Currently we clear the leftover vswing/preemphasis values only
at the start of link training. That means the initial vswing
programming performed during modeset is going to use stale values
left over from the previous link training sequence, and then at
the start of link training we're going to reset the levels back
to 0. Seems much better to make sure we start with level 0 from
the get go.
Additionally if LTTPRs are present the leftover vswing/preemphasis
values are those of the last link in the chain, so not the values
that our PHY is even using after a successful link training sequence.
So let's make sure everything is cleared up before we start
programming anything.
With patch "drm/i915/vbt: Fix backlight parsing for VBT 234+"
the size of bdb_lfp_backlight_data structure has been increased,
causing if-statement in the parse_lfp_backlight function
that comapres this structure size to the one retrieved from BDB,
always to fail for older revisions.
This patch calculates expected size of the structure for a given
BDB version and compares it with the value gathered from BDB.
Tested on Chromebook Pixelbook (Nocturne) (reports bdb->version = 221)
Fixes: d381baad29b4 ("drm/i915/vbt: Fix backlight parsing for VBT 234+") Tested-by: Lukasz Majczak <lma@semihalf.com> Signed-off-by: Lukasz Majczak <lma@semihalf.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210930134606.227234-1-lma@semihalf.com
Ville Syrjälä [Mon, 13 Sep 2021 14:44:34 +0000 (17:44 +0300)]
drm/i915: Configure TRANSCONF just the once with bigjoiner
Let's not configure the single transcoder's TRANSCONF multiple
times with bigjoiner. No real harm I suppose but since we already
have the bigjoiner if statement directly above might as well suck
this in there and skip the redundant programming.
Ville Syrjälä [Mon, 13 Sep 2021 14:44:33 +0000 (17:44 +0300)]
drm/i915: Pimp HSW+ transcoder state readout
Adjust the HSW+ transcoder state readout to just read through
all the possible transcoders for the pipe, and stuff the results
in a bitmask.
We can conveniently cross check the bitmask for invalid
combinations of enabled transcoders, and later we can easily
extend the bitmask readout to handle the bigjoiner case.
One slight change in behaviour is that we no longer read out
the AONOFF->force_pfit.pfit bit for all the enabled "panel
transcoders". But having more than one enabled would anyway
be illegal so no big loss. Also the AONOFF selection should
only ever be used on HSW, which only has the EDP transcoder
an no DSI transcoders.
Ville Syrjälä [Fri, 24 Sep 2021 14:13:30 +0000 (17:13 +0300)]
drm/i915/fbc: Allow FBC with Yf tiling
FBC+Yf tiling seems to work just fine, and unlike with linear
the hardware does appear to correctly calculate the CFB stride
with using the override stride on both cfl and glk. So no need
for any additional tweaks.
Ville Syrjälä [Wed, 29 Sep 2021 16:24:04 +0000 (19:24 +0300)]
drm/i915: Enable TPS3/4 on all platforms that support them
Stop using HBR2/3 support as a proxy for TPS3/4 support.
The two are no longer 1:1 in the hardware, arguably they
never were due to HSW ULX which does support TPS3 while
being limited to HBR1.
In more recent times GLK gained support for TPS4 while
being limited to HBR2. And on CNL+ some ports support
HBR3 while others are limited to HBR2, but all ports
support TPS4.
Ville Syrjälä [Wed, 29 Sep 2021 18:45:36 +0000 (21:45 +0300)]
drm/i915: Reject user modes that don't match fixed mode's refresh rate
When using a panel with a fixed mode we don't change the refresh
rate of the display. Reject any user requested mode which doesn't
match that fixed refresh rate.
Unfortunately when Xorg sees the scaling_mode property on the
connecor it likes to automagically cook up modes whose refresh
rate is a fair bit off from the fixed refresh rate we use. So
we have to give it some extra latitude so that we don't start to
reject all of it.
v2: sDVO now uses intel_panel_compute_config() too
v3: Add a debug message to inform the user what happened
Ville Syrjälä [Mon, 27 Sep 2021 18:52:07 +0000 (21:52 +0300)]
drm/i915: Introduce intel_panel_compute_config()
Let's introduce a compute_config() helper for fixed mode panels.
For now all it does is the fixed_mode->adjusted_mode copy.
Note that with sDVO we have to ask the external encoder chip
to spit out our actual display timings for us, so the fixed_mode
to adjusted_mode copy done by intel_panel_compute_config() is
redundant, but we still want to use it to do other checks for us
later. We'll be fine so long as we only call it before
intel_sdvo_get_preferred_input_mode() overwrites adjusted_mode
with the timings from the encoder.
Ville Syrjälä [Thu, 23 Sep 2021 20:01:06 +0000 (23:01 +0300)]
drm/i915: Reject modes that don't match fixed_mode vrefresh
When using a fixed mode we won't change the refresh rate ever.
So filter out all modes that don't match the fixed_mode's refresh
rate.
I'm going to declare the "rounded to nearest Hz refresh
rates must match" approach good enough for now.
Note that we could start supporting multiple refresh rates
with panels that can do it, but that would mean replacing
the single fixed mode concept with a list of fixed modes.
Then we could look for the closest match to the user's
requested refresh rate and use that. But all of that would
be a fair bit of work so we'll leave it for later.
Ville Syrjälä [Thu, 23 Sep 2021 20:01:05 +0000 (23:01 +0300)]
drm/i915: Use intel_panel_mode_valid() for DSI/LVDS/(s)DVO
All fixed mode panels should behave the same way when it comes to mode
filtering. Reuse the intel_panel_mode_valid() for all of them.
This changes the behaviour to match what we do for eDP, ie.
reject anything that doesn't exactly match the fixed mode
dimensions. Users can still manually provide different
sized modes which will be handled by the panel fitter just
as before. The difference is that we can no longer report
funny modes in the connector's mode list.
Imre Deak [Wed, 29 Sep 2021 13:28:33 +0000 (16:28 +0300)]
drm/i915/tc: Fix system hang on ADL-P during TypeC PHY disconnect
The PHY ownership release->AUX PW disable steps during a modeset
disable->PHY disconnect sequence can hang the system if the PHY
disconnect happens after disabling the PHY's PLL. The spec doesn't
require a specific order for these two steps, so this issue is still
being root caused by HW/FW teams. Until that is found, let's make
sure the disconnect happens before the PLL is disabled, and do this on
all platforms for consistency.
v2: Add a TODO comment to remove the w/a once the issue is root
caused/fixed. (Jose)
Imre Deak [Tue, 21 Sep 2021 00:23:12 +0000 (03:23 +0300)]
drm/i915/tc: Drop extra TC cold blocking from intel_tc_port_connected()
After the previous patch the driver holds a power domain blocking
TC-cold whenever the port is locked, so we can remove the extra blocking
around the lock/unlock sequence.
Imre Deak [Wed, 29 Sep 2021 13:28:32 +0000 (16:28 +0300)]
drm/i915/tc: Fix TypeC PHY connect/disconnect logic on ADL-P
So far TC-cold was blocked only for the duration of TypeC mode resets.
The DP-alt and legacy modes require TC-cold to be blocked also whenever
the port is in use (AUX transfers, enable modeset), and this was ensured
by the held PHY ownership flag. On ADL-P this doesn't work, since the
PHY ownership flag is in a register backed by the PW#2 power well.
Whenever this power well is disabled the ownership flag is cleared by
the HW under the driver.
The only way to cleanly release and re-acquire the PHY ownership flag
and also allow for power saving (by disabling the display power wells
and reaching DC5/6 states) is to hold the TC-cold blocking power domains
while the PHY is connected and disconnect/reconnect the PHY on-demand
around AUX transfers and modeset enable/disables. Let's do that,
disconnecting a PHY with a 1 sec delay after it becomes idle. For
consistency do this on all platforms and TypeC modes.
v2: Add tc_mode!=disconnected and phy_is_owned asserts to
__intel_tc_port_lock().
Imre Deak [Tue, 21 Sep 2021 00:23:10 +0000 (03:23 +0300)]
drm/i915/icl/tc: Remove the ICL special casing during TC-cold blocking
While a TypeC port mode is locked a DISPLAY_CORE power domain reference
is held, which implies a runtime PM ref. By removing the ICL !legacy
port special casing, a TC_COLD_OFF power domain reference will be taken
for such ports, which also translates to a runtime PM ref on that
platform. A follow-up change will stop holding the DISPLAY_CORE power
domain while the port is locked.
Imre Deak [Wed, 29 Sep 2021 13:28:31 +0000 (16:28 +0300)]
drm/i915/tc: Avoid using legacy AUX PW in TBT mode
For the ADL-P TBT mode the spec doesn't require blocking TC-cold by
using the legacy AUX power domain. To avoid the timeouts that this would
cause during PHY disconnect/reconnect sequences (which will be more
frequent after a follow-up change) use the TC_COLD_OFF power domain in
TBT mode on all platforms. On TGL this power domain blocks TC-cold via a
PUNIT command, while on other platforms the domain just takes a runtime
PM reference.
If the HPD live status indicates that the port mode needs to be reset
- for instance after switching from TBT to a DP-alt sink - still take
the AUX domain, since the IOM firmware handshake requires this.
Imre Deak [Wed, 29 Sep 2021 13:28:29 +0000 (16:28 +0300)]
drm/i915/tc: Add a mode for the TypeC PHY's disconnected state
A follow-up change will start to disconnect/re-connect PHYs around AUX
transfers and modeset enable/disables. To prepare for that add a new
TypeC PHY disconnected mode, to help tracking the TC-cold blocking power
domain status (no power domain in disconnected state, mode dependent
power domain in connected state).
v2: Move the !disconnected mode and phy-owned asserts in
__intel_tc_port_lock() later in the patchset, when the asserts will
hold. (Jose)
Imre Deak [Tue, 21 Sep 2021 00:23:06 +0000 (03:23 +0300)]
drm/i915/tc: Don't keep legacy TypeC ports in connected state w/o a sink
A follow-up patch will disconnect/reconnect PHYs around AUX transfers
and modeset enable/disables. To prepare for that and make things
consistent for all TypeC modes stop connecting the PHY in legacy mode
without a sink being connected. This was done before since in legacy
mode the PHY is dedicated to display usage, so there was no point in
disconnecting it. However after the follow-up changes the TC-cold
blocking power domains will be held as long as the PHY is in the
connected state, so we'll need to disconnect/re-connect the PHY in all
TypeC modes to allow for power saving.
Imre Deak [Wed, 29 Sep 2021 13:28:28 +0000 (16:28 +0300)]
drm/i915/tc: Check for DP-alt, legacy sinks before taking PHY ownership
On ADL-P the PHY ready/complete flag is always set even in TBT-alt mode.
To avoid taking the PHY ownership and the following spurious "PHY sudden
disconnect" messages on this platform when connecting the PHY in TBT
mode, check if there is any DP-alt or legacy sink connected before
taking the ownership.
v2: (Jose)
- Fix debug message clarifying that a TBT sink can be connected.
- Add comments describing the PHY complete HW flag semantic differences
between adl-p and other platforms.
Imre Deak [Tue, 21 Sep 2021 00:23:03 +0000 (03:23 +0300)]
drm/i915/tc: Remove waiting for PHY complete during releasing ownership
Waiting for the PHY complete flag to clear when releasing the PHY
ownership was add in
commit ddec362724f9 ("drm/i915: Wait for TypeC PHY complete flag to clear in safe mode")
This isn't required by the spec, the vague idea was to make the
handshake with the firmware more robust, without actual evidence for
when it would be needed. Checking this again, the flag doesn't clear on
ICL until after the PHY's PLL is disabled and the flag is permanently
set on ADL-P. To avoid the spurious timeout messages in dmesg, just
remove this wait.
Imre Deak [Tue, 21 Sep 2021 00:23:02 +0000 (03:23 +0300)]
drm/i915/adlp/tc: Fix PHY connected check for Thunderbolt mode
On ADL-P the PHY ready (aka status complete on other platforms) flag is
always set, besides when a DP-alt, legacy sink is connected also when a
TBT sink is connected or nothing is connected. So assume the PHY to be
connected when both the TBT live status and PHY ready flags are set.
Imre Deak [Wed, 29 Sep 2021 13:28:27 +0000 (16:28 +0300)]
drm/i915/tc: Fix TypeC port init/resume time sanitization
Atm during driver loading and system resume TypeC ports are accessed
before their HW/SW state is synced. Move the TypeC port sanitization to
the encoder's sync_state hook to fix this.
v2: Handle the encoder disabled case in gen11_dsi_sync_state() as well
(Jose, Jani)
Fixes: f9e76a6e68d3 ("drm/i915: Add an encoder hook to sanitize its state during init/resume") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-1-imre.deak@intel.com
drm/i915/gen11: Disable cursor clock gating in HDR mode
Display underrun in HDR mode when cursor is enabled.
RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
As per W/A 1604331009, Disable cursor clock gating in HDR mode.
Bspec : 33451
Changes since V6:
- Address checkpatch warnings
- Bit ordering
Changes since V5:
- replace intel_de_read with intel_de_rmw - Jani
Changes since V4:
- Added WA needed check - Ville
- Replace BIT with REG_BIT - Ville
- Add WA enable/disable support back which was
added in V1 - Ville
Changes since V3:
- Disable WA when not in HDR mode or cursor plane
not active - Ville
- Extract required args from crtc_state - Ville
- Create HDR mode API using bdw_set_pipemisc ref - Ville
- Tested with HDR video as well full setmode, WA
applies and disables
Changes since V2:
- Made it general gen11 WA
- Removed WA needed check
- Added cursor plane active check
- Once WA enable, software will not disable
Changes since V1:
- Modified way CLKGATE_DIS_PSL bit 28 was modified
Dave Airlie [Tue, 28 Sep 2021 22:57:46 +0000 (01:57 +0300)]
drm/i915/pm: drop get_fifo_size vfunc.
The i845_update_wm code was always calling the i845 variant,
and the i9xx_update_wm had only a choice between i830 and i9xx
paths, hardly worth the vfunc overhead.
drm/i915/display: Fix the dsc check while selecting min_cdclk
The right parameter that selects second dsc engine is dsc_split.
Hence use dsc_split instead of slice_count while selecting the
cdclk in order to accommodate 1ppc limitaion of vdsc.
Fixes: fe01883fdcef ("drm/i915: Get proper min cdclk if vDSC enabled") Suggested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210915054338.29869-1-vandita.kulkarni@intel.com
Ville Syrjälä [Tue, 21 Sep 2021 15:25:17 +0000 (18:25 +0300)]
drm/i915/fbc: Allow higher compression limits on FBC1
On FBC1 we can specify an arbitrary cfb stride. The hw will
simply throw away any compressed line that would exceed the
specified limit and keep using the uncompressed data instead.
Thus we can allow arbitrary compression limits.
The one thing we have to keep in mind though is that the cfb
stride is specified in units of 32B (gen2) or 64B (gen3+).
Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide
so as long as we limit outselves to the same 4x compression
limit that FBC2 has we are guaranteed to have a sufficiently
aligned cfb stride.
Ville Syrjälä [Tue, 21 Sep 2021 15:25:15 +0000 (18:25 +0300)]
drm/i915/fbc: Align FBC segments to 512B on glk+
Apply the same 512 byte FBC segment alignment to glk+ as we use
on skl+. The only real difference is that we now have a dedicated
register for the FBC override stride. Not 100% sure which
platforms really need the 512B alignment, but it's easiest
to just do it on everything.
Also the hardware no longer seems to misclaculate the CFB stride
for linear, so we can omit the use of the override stride for
linear unless the stride is misaligned.
Ville Syrjälä [Thu, 23 Sep 2021 04:21:51 +0000 (07:21 +0300)]
drm/i915/fbc: Rework cfb stride/size calculations
The code to calculate the cfb stride/size is a bit of mess.
The cfb size is getting calculated based purely on the plane
stride and plane height. That doesn't account for extra
alignment we want for the cfb stride. The gen9 override
stride OTOH is just calculated based on the plane width, and
it does try to make things more aligned but any extra alignment
added there is not considered in the cfb size calculations.
So not at all convinced this is working as intended. Additionally
the compression limit handling is split between the cfb allocation
code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just
confusing.
Let's streamline the whole thing:
- Start with the plane stride, convert that into cfb stride (cfb is
always 4 bytes per pixel). All the calculations will assume 1:1
compression limit since that will give us the max values, and we
don't yet know how much stolen memory we will be able to allocate
- Align the cfb stride to 512 bytes on modern platforms. This guarantees
the 4 line segment will be 512 byte aligned regardles of the final
compression limit we choose later. The 512 byte alignment for the
segment is required by at least some of the platforms, and just doing
it always seems like the easiest option
- Figure out if we need to use the override stride or not. For X-tiled
it's never needed since the plane stride is already 512 byte aligned,
for Y-tiled it will be needed if the plane stride is not a multiple
of 512 bytes, and for linear it's apparently always needed because the
hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
the PLANE_STRIDE*64 that it use with linear.
- The cfb size will be calculated based on the aligned cfb stride to
guarantee we actually reserved enough stolen memory and the FBC hw
won't end up scribbling over whatever else is allocated in stolen
- The compression limit handling we just do fully in the cfb allocation
code to make things less confusing
v2: Write the min cfb segment stride calculation in a more
explicit way to make it clear what is going on
v3: Remeber to update fbc->limit when changing to 16bpp
José Roberto de Souza [Wed, 22 Sep 2021 21:52:42 +0000 (14:52 -0700)]
drm/i915/display: Only keep PSR enabled if there is active planes
PSR always had a requirement to only be enabled if there is active
planes but not following that never caused any issues.
But that changes in Alderlake-P, leaving PSR enabled without
active planes causes transcoder/port underruns.
Similar behavior was fixed during the pipe disable sequence by
commit 84030adb9e27 ("drm/i915/display: Disable audio, DRRS and PSR before planes").
intel_dp_compute_psr_vsc_sdp() had to move from
intel_psr_enable_locked() to intel_psr_compute_config() because we
need to be able to disable/enable PSR from atomic states without
connector and encoder state.
José Roberto de Souza [Wed, 22 Sep 2021 21:52:41 +0000 (14:52 -0700)]
drm/i915/display: Match PSR2 selective fetch sequences with specification
We were not completely following the selective fetch programming
sequence, here some things we were doing wrong:
- not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
when doing a modeset
- programming PSR2_MAN_TRK_CTL out of vblank
With this changes the last remainig underrun found in Alderlake-P is
fixed.
Imre Deak [Mon, 6 Sep 2021 18:27:14 +0000 (21:27 +0300)]
drm/i915/adlp: Add support for remapping CCS FBs
Add support for remapping CCS FBs on ADL-P to remove the restriction
of the power-of-two sized stride and the 2MB surface offset alignment
for these FBs.
We can only remap the tiles on the main surface, not the tiles on the
CCS surface, so userspace has to generate the CCS surface aligning to
the POT size padded main surface stride (by programming the AUX
pagetable accordingly). For the required AUX pagetable setup, this
requires that either the main surface stride is 8 tiles or that the
stride is 16 tiles aligned (= 64 kbytes, the area mapped by one AUX
PTE).
v2:
- Init intel_remapped_info::plane_alignment only for remapped views and
do this from intel_fb_view_init().
Imre Deak [Mon, 6 Sep 2021 18:27:11 +0000 (21:27 +0300)]
drm/i915/adlp: Require always a power-of-two sized CCS surface stride
At the moment CCS FB strides must be power-of-two sized, but a follow-up
change will add support remapping these FBs, allowing the FB passed in
by userspace to have a non-POT sized stride. For these remapped FBs we
can only remap the main surface, not the CCS surface. This means that
userspace has to always generate the CCS surface aligning to the POT
stride padded main surface (by setting up the CCS AUX pagetables
accordingly). Adjust the CCS surface stride check to enforce this.
No functional change.
v2:
- Fix the gen12_ccs_aux_stride() is not static sparse warning.
Imre Deak [Mon, 6 Sep 2021 18:27:10 +0000 (21:27 +0300)]
drm/i915: Use tile block based dimensions for CCS origin x, y check
The tile size for all surface types is 4 kbyte (or 2 kbyte on old
platforms), with the exception of the TGL/ADL CCS surface where the tile
size is 64 bytes. To be able to remap CCS FBs the CCS surface tile needs
to be defined as 4 kbyte as well (the granularity of GTT pages in a
remapped view).
The only place using the dimension of the 64 byte CCS area is the initial
check for the main vs. CCS plane origin coordinate match. To prepare for
adding support for remapping CCS FBs let's call the 64 byte CCS area a
'tile block' and add a helper to retrieve the dimensions for it.
Ville Syrjälä [Fri, 14 May 2021 12:57:39 +0000 (15:57 +0300)]
drm/i915: Fix g4x cxsr enable condition
The intention was to check whether the primary plane is enabled
without any sprites planes being enabled. Instead we ended up checking
whether just any one of the planes is enabled. g4x isn't vlv/chv and
cxsr only works with the primary plane. Fix the check to examine the
bitmask of active planes rather than the number of bits set in said
bitmask.
Jani Nikula [Thu, 9 Sep 2021 12:52:03 +0000 (15:52 +0300)]
drm/i915/dg2: use 128b/132b transcoder DDI mode
128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.
Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.
v2:
- Use HAS_DP20 abstraction for 128b/132b mode (Ville)
- Use intel_dp_is_uhbr() helper
Jani Nikula [Thu, 9 Sep 2021 12:51:59 +0000 (15:51 +0300)]
drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.
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