Stephen Boyd [Wed, 1 Sep 2021 22:27:07 +0000 (15:27 -0700)]
Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-ralink' into clk-next
* clk-kirkwood:
clk: kirkwood: Fix a clocking boot regression
* clk-imx:
clk: imx8mn: Add M7 core clock
clk: imx8m: fix clock tree update of TF-A managed clocks
clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate
clk: imx8mn: use correct mux type for clkout path
clk: imx8mm: use correct mux type for clkout path
* clk-doc:
dt-bindings: clock: samsung: fix header path in example
MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
dt-bindings: clock: samsung: convert Exynos4 to dtschema
dt-bindings: clock: samsung: convert Exynos3250 to dtschema
dt-bindings: clock: samsung: convert Exynos542x to dtschema
dt-bindings: clock: samsung: add bindings for Exynos external clock
dt-bindings: clock: samsung: convert Exynos5250 to dtschema
dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
clk: zynqmp: Fix kernel-doc format
clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings
clk: zynqmp: fix kernel doc
* clk-zynq:
clk: zynqmp: Fix a memory leak
clk: zynqmp: Check the return type
* clk-ralink:
clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
Stephen Boyd [Wed, 1 Sep 2021 22:26:58 +0000 (15:26 -0700)]
Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5' into clk-next
- Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
* clk-nvidia:
clk: tegra: fix old-style declaration
clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
soc/tegra: fuse: Add runtime PM support
soc/tegra: fuse: Clear fuse->clk on driver probe failure
soc/tegra: pmc: Prevent racing with cpuilde driver
soc/tegra: bpmp: Remove unused including <linux/version.h>
* clk-rockchip:
clk: rockchip: make rk3308 ddrphy4x clock critical
clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
clk: rockchip: Add support for hclk_sfc on rk3036
clk: rockchip: rk3036: fix up the sclk_sfc parent error
clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036
* clk-at91:
clk: at91: clk-generated: Limit the requested rate to our range
* clk-vc5:
clk: vc5: Add properties for configuring SD/OE behavior
clk: vc5: Use dev_err_probe
dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
Stephen Boyd [Wed, 1 Sep 2021 22:26:42 +0000 (15:26 -0700)]
Merge branch 'clk-frac-divider' into clk-next
- Add power of two flag to fractional divider clk type
* clk-frac-divider:
clk: fractional-divider: Document the arithmetics used behind the code
clk: fractional-divider: Introduce POWER_OF_TWO_PS flag
clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience
clk: fractional-divider: Export approximation algorithm to the CCF users
Stephen Boyd [Wed, 1 Sep 2021 22:25:15 +0000 (15:25 -0700)]
Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk-next
- Migrate some clk drivers to clk_divider_ops.determine_rate
* clk-renesas:
clk: renesas: Make CLK_R9A06G032 invisible
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
clk: renesas: r9a07g044: Add clock and reset entries for ADC
clk: renesas: r9a07g044: Add clock and reset entries for CANFD
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
clk: renesas: r9a07g044: Add GPIO clock and reset entries
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
clk: renesas: r9a07g044: Add USB clocks/resets
clk: renesas: r9a07g044: Add DMAC clocks/resets
clk: renesas: r9a07g044: Add I2C clocks/resets
clk: renesas: r8a779a0: Add the DSI clocks
clk: renesas: r8a779a0: Add the DU clock
clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic
clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
clk: renesas: rzg2l: Avoid mixing error pointers and NULL
clk: renesas: rzg2l: Fix a double free on error
clk: renesas: rzg2l: Fix return value and unused assignment
clk: renesas: rzg2l: Remove unneeded semicolon
* clk-cleanup:
clk: palmas: Add a missing SPDX license header
clk: Align provider-specific CLK_* bit definitions
* clk-determine-divider:
clk: stm32mp1: Switch to clk_divider.determine_rate
clk: stm32h7: Switch to clk_divider.determine_rate
clk: stm32f4: Switch to clk_divider.determine_rate
clk: bcm2835: Switch to clk_divider.determine_rate
clk: divider: Implement and wire up .determine_rate by default
Stephen Boyd [Wed, 1 Sep 2021 22:24:59 +0000 (15:24 -0700)]
Merge branches 'clk-qcom', 'clk-socfpga', 'clk-mediatek', 'clk-lmk' and 'clk-x86' into clk-next
- Support video, gpu, display clks on qcom sc7280 SoCs
- GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
- Multimedia clks (MMCC) on qcom MSM8994/MSM8992
- Migrate to clk_parent_data in gcc-sdm660
- RPMh clks on qcom SM6350 SoCs
- Support for Mediatek MT8192 SoCs
* clk-qcom: (38 commits)
clk: qcom: Add SM6350 GCC driver
dt-bindings: clock: Add SM6350 GCC clock bindings
clk: qcom: rpmh: Add support for RPMH clocks on SM6350
dt-bindings: clock: Add RPMHCC bindings for SM6350
clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250
clk: qcom: Add Global Clock controller (GCC) driver for SM6115
dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC
clk: qcom: mmcc-msm8994: Add MSM8992 support
clk: qcom: Add msm8994 MMCC driver
dt-bindings: clock: Add support for MSM8992/4 MMCC
clk: qcom: Add Global Clock Controller driver for MSM8953
dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings
clk: qcom: gcc-sdm660: Replace usage of parent_names
clk: qcom: gcc-sdm660: Move parent tables after PLLs
clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create
PM: runtime: add devm_pm_clk_create helper
PM: runtime: add devm_pm_runtime_enable helper
clk: qcom: a53-pll: Add MSM8939 a53pll support
dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support
clk: qcom: a53pll/mux: Use unique clock name
...
* clk-socfpga:
clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
clk: socfpga: agilex: fix up s2f_user0_clk representation
clk: socfpga: agilex: fix the parents of the psi_ref_clk
* clk-mediatek: (22 commits)
clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167
clk: mediatek: Add MT8192 vencsys clock support
clk: mediatek: Add MT8192 vdecsys clock support
clk: mediatek: Add MT8192 scp adsp clock support
clk: mediatek: Add MT8192 msdc clock support
clk: mediatek: Add MT8192 mmsys clock support
clk: mediatek: Add MT8192 mfgcfg clock support
clk: mediatek: Add MT8192 mdpsys clock support
clk: mediatek: Add MT8192 ipesys clock support
clk: mediatek: Add MT8192 imp i2c wrapper clock support
clk: mediatek: Add MT8192 imgsys clock support
clk: mediatek: Add MT8192 camsys clock support
clk: mediatek: Add MT8192 audio clock support
clk: mediatek: Add MT8192 basic clocks support
clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
clk: mediatek: Add configurable enable control to mtk_pll_data
clk: mediatek: Fix asymmetrical PLL enable and disable control
clk: mediatek: Get regmap without syscon compatible check
clk: mediatek: Add dt-bindings of MT8192 clocks
dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192
...
* clk-lmk:
clk: lmk04832: drop redundant fallthrough statements
* clk-x86:
clk: x86: Rename clk-lpt to more specific clk-lpss-atom
Mikulas Patocka [Mon, 30 Aug 2021 09:42:27 +0000 (05:42 -0400)]
parisc: fix crash with signals and alloca
I was debugging some crashes on parisc and I found out that there is a
crash possibility if a function using alloca is interrupted by a signal.
The reason for the crash is that the gcc alloca implementation leaves
garbage in the upper 32 bits of the sp register. This normally doesn't
matter (the upper bits are ignored because the PSW W-bit is clear),
however the signal delivery routine in the kernel uses full 64 bits of sp
and it fails with -EFAULT if the upper 32 bits are not zero.
I created this program that demonstrates the problem:
Masahiro Yamada [Thu, 10 Jun 2021 02:03:31 +0000 (11:03 +0900)]
parisc: Fix compile failure when building 64-bit kernel natively
Commit 23243c1ace9f ("arch: use cross_compiling to check whether it is
a cross build or not") broke 64-bit parisc builds on 32-bit parisc
systems.
Helge mentioned:
- 64-bit parisc userspace is not supported yet [1]
- hppa gcc does not support "-m64" flag [2]
That means, parisc developers working on a 32-bit parisc machine need
to use hppa64-linux-gnu-gcc (cross compiler) for building the 64-bit
parisc kernel.
After the offending commit, gcc is used in such a case because
both $(SRCARCH) and $(SUBARCH) are 'parisc', hence cross_compiling is
unset.
A correct way is to introduce ARCH=parisc64 because building the 64-bit
parisc kernel on a 32-bit parisc system is not exactly a native build,
but rather a semi-cross build.
Fixes: 23243c1ace9f ("arch: use cross_compiling to check whether it is a cross build or not") Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reported-by: Meelis Roos <mroos@linux.ee> Tested-by: Meelis Roos <mroos@linux.ee> Cc: <stable@vger.kernel.org> # v5.13+ Signed-off-by: Helge Deller <deller@gmx.de>
Alan Stern [Wed, 1 Sep 2021 16:36:06 +0000 (12:36 -0400)]
HID: usbhid: Simplify code in hid_submit_ctrl()
This patch makes a small simplification to the code in
hid_submit_ctrl(). The test for maxpacket being > 0 is unnecessary,
because endpoint 0 always has a maxpacket value which is >= 8.
Furthermore, endpoint 0's maxpacket value is always a power of 2, so
instead of open-coding the round-to-next-multiple computation we can
call the optimized round_up() routine.
Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Tested-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Alan Stern [Wed, 1 Sep 2021 16:36:00 +0000 (12:36 -0400)]
HID: usbhid: Fix warning caused by 0-length input reports
Syzbot found a warning caused by hid_submit_ctrl() submitting a
control request to transfer a 0-length input report:
usb 1-1: BOGUS control dir, pipe 80000280 doesn't match bRequestType a1
(The warning message is a little difficult to understand. It means
that the control request claims to be for an IN transfer but this
contradicts the USB spec, which requires 0-length control transfers
always to be in the OUT direction.)
Now, a zero-length report isn't good for anything and there's no
reason for a device to have one, but the fuzzer likes to pick out
these weird edge cases. In the future, perhaps we will decide to
reject 0-length reports at probe time. For now, the simplest approach
for avoiding these warnings is to pretend that the report actually has
length 1.
Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Reported-and-tested-by: syzbot+9b57a46bf1801ce2a2ca@syzkaller.appspotmail.com Tested-by: Oleksandr Natalenko <oleksandr@natalenko.name> Tested-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Michal Kubecek [Wed, 1 Sep 2021 16:35:49 +0000 (12:35 -0400)]
HID: usbhid: Fix flood of "control queue full" messages
[patch description by Alan Stern]
Commit 7652dd2c5cb7 ("USB: core: Check buffer length matches wLength
for control transfers") causes control URB submissions to fail if the
transfer_buffer_length value disagrees with the setup packet's wLength
valuel. Unfortunately, it turns out that the usbhid can trigger this
failure mode when it submits a control request for an input report: It
pads the transfer buffer size to a multiple of the maxpacket value but
does not increase wLength correspondingly.
These failures have caused problems for people using an APS UPC, in
the form of a flood of log messages resembling:
hid-generic 0003:051D:0002.0002: control queue full
This patch fixes the problem by setting the wLength value equal to the
padded transfer_buffer_length value in hid_submit_ctrl(). As a nice
bonus, the code which stores the transfer_buffer_length value is now
shared between the two branches of an "if" statement, so it can be
de-duplicated.
Signed-off-by: Michal Kubecek <mkubecek@suse.cz> Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Fixes: 7652dd2c5cb7 ("USB: core: Check buffer length matches wLength for control transfers") Tested-by: Oleksandr Natalenko <oleksandr@natalenko.name> Tested-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Jiri Kosina <jkosina@suse.cz>
i915:
- Enable JSL and EHL by default
- preliminary XeHP/DG2 support
- remove all CNL support (never shipped)
- move to TTM for discrete memory support
- allow mixed object mmap handling
- GEM uAPI spring cleaning
- add I915_MMAP_OBJECT_FIXED
- reinstate ADL-P mmap ioctls
- drop a bunch of unused by userspace features
- disable and remove GPU relocations
- revert some i915 misfeatures
- major refactoring of GuC for Gen11+
- execbuffer object locking separate step
- reject caching/set-domain on discrete
- Enable pipe DMC loading on XE-LPD and ADL-P
- add PSF GV point support
- Refactor and fix DDI buffer translations
- Clean up FBC CFB allocation code
- Finish INTEL_GEN() and friends macro conversions
nouveau:
- add eDP backlight support
- implicit fence fix
msm:
- a680/7c3 support
- drm/scheduler conversion
panfrost:
- rework GPU reset
virtio:
- fix fencing for planes
ast:
- add detect support
bochs:
- move to tiny GPU driver
vc4:
- use hotplug irqs
- HDMI codec support
vmwgfx:
- use internal vmware device headers
ingenic:
- demidlayering irq
rcar-du:
- shutdown fixes
- convert to bridge connector helpers
zynqmp-dsub:
- misc fixes
mgag200:
- convert PLL handling to atomic
mediatek:
- MT8133 AAL support
- gem mmap object support
- MT8167 support
* tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm: (1318 commits)
drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box
drm/amd/display: Remove duplicate dml init
drm/amd/display: Update bounding box states (v2)
drm/amd/display: Update number of DCN3 clock states
drm/amdgpu: disable GFX CGCG in aldebaran
drm/amdgpu: Clear RAS interrupt status on aldebaran
drm/amdgpu: Add support for RAS XGMI err query
drm/amdkfd: Account for SH/SE count when setting up cu masks.
drm/amdgpu: rename amdgpu_bo_get_preferred_pin_domain
drm/amdgpu: drop redundant cancel_delayed_work_sync call
drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend
drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend
drm/amdkfd: map SVM range with correct access permission
drm/amdkfd: check access permisson to restore retry fault
drm/amdgpu: Update RAS XGMI Error Query
drm/amdgpu: Add driver infrastructure for MCA RAS
drm/amd/display: Add Logging for HDMI color depth information
drm/amd/amdgpu: consolidate PSP TA init shared buf functions
drm/amd/amdgpu: add name field back to ras_common_if
drm/amdgpu: Fix build with missing pm_suspend_target_state module export
...
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