Bjorn Helgaas [Mon, 1 Aug 2016 17:32:13 +0000 (12:32 -0500)]
Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-dra7xx', 'pci/host-hv', 'pci/host-vmd' and 'pci/host-xilinx' into next
* pci/host-aardvark:
arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700
PCI: aardvark: Add Aardvark PCI host controller driver
dt-bindings: add DT binding for the Aardvark PCIe controller
* pci/host-altera:
PCI: altera: Poll for link up status after retraining the link
PCI: altera: Check link status before retrain link
PCI: altera: Reorder read/write functions
* pci/host-dra7xx:
PCI: dra7xx: Fix return value in case of error
* pci/host-hv:
PCI: hv: Fix interrupt cleanup path
PCI: hv: Handle all pending messages in hv_pci_onchannelcallback()
PCI: hv: Don't leak buffer in hv_pci_onchannelcallback()
* pci/host-vmd:
x86/PCI: VMD: Separate MSI and MSI-X vector sharing
x86/PCI: VMD: Use x86_vector_domain as parent domain
x86/PCI: VMD: Use lock save/restore in interrupt enable path
x86/PCI: VMD: Initialize list item in IRQ disable
x86/PCI: VMD: Select device dma ops to override
* pci/host-xilinx:
PCI: xilinx: Fix return value in case of error
Manually apply changes from pci/demodularize-hosts and
pci/host-request-windows to drivers/pci/host/pci-aardvark.c
Bjorn Helgaas [Mon, 1 Aug 2016 17:25:37 +0000 (12:25 -0500)]
Merge branch 'pci/host-tegra' into next
* pci/host-tegra:
PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values
PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs
PCI: tegra: Stop setting pcibios_min_mem
PCI: tegra: Use generic pci_remap_iospace() rather than ARM32-specific one
PCI: tegra: Use lower-case hex consistently for register definitions
Conflicts:
drivers/pci/host/pci-tegra.c
Drop stray pci_ioremap_io() per Thierry Reding <treding@nvidia.com>;
removal tested by Jon Hunter <jonathanh@nvidia.com>.
Bjorn Helgaas [Mon, 1 Aug 2016 17:23:44 +0000 (12:23 -0500)]
Merge branch 'pci/resource' into next
* pci/resource:
unicore32/PCI: Remove pci=firmware command line parameter handling
ARM/PCI: Remove arch-specific pcibios_enable_device()
ARM64/PCI: Remove arch-specific pcibios_enable_device()
MIPS/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups
ARM/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups
PCI: generic: Claim bus resources on PCI_PROBE_ONLY set-ups
PCI: Add generic pci_bus_claim_resources()
alx: Use pci_(request|release)_mem_regions
ethernet/intel: Use pci_(request|release)_mem_regions
GenWQE: Use pci_(request|release)_mem_regions
lpfc: Use pci_(request|release)_mem_regions
NVMe: Use pci_(request|release)_mem_regions
PCI: Add helpers to request/release memory and I/O regions
PCI: Extending pci=resource_alignment to specify device/vendor IDs
sparc/PCI: Implement pci_resource_to_user() with pcibios_resource_to_bus()
powerpc/pci: Implement pci_resource_to_user() with pcibios_resource_to_bus()
microblaze/PCI: Implement pci_resource_to_user() with pcibios_resource_to_bus()
PCI: Unify pci_resource_to_user() declarations
microblaze/PCI: Remove useless __pci_mmap_set_pgprot()
powerpc/pci: Remove __pci_mmap_set_pgprot()
PCI: Ignore write combining when mapping I/O port space
Bjorn Helgaas [Mon, 1 Aug 2016 17:23:31 +0000 (12:23 -0500)]
Merge branches 'pci/aspm', 'pci/dpc', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/pm' and 'pci/virtualization' into next
* pci/aspm:
PCI/ASPM: Remove redundant check of pcie_set_clkpm
* pci/dpc:
PCI: Remove DPC tristate module option
PCI: Bind DPC to Root Ports as well as Downstream Ports
PCI: Fix whitespace in struct dpc_dev
PCI: Convert Downstream Port Containment driver to use devm_* functions
* pci/hotplug:
PCI: Allow additional bus numbers for hotplug bridges
* pci/misc:
PCI: Include <asm/dma.h> for isa_dma_bridge_buggy
PCI: Make bus_attr_resource_alignment static
MAINTAINERS: Add file patterns for PCI device tree bindings
PCI: Fix comment typo
* pci/pm:
PCI: pciehp: Ignore interrupts during D3cold
PCI: Document connection between pci_power_t and hardware PM capability
PCI: Add runtime PM support for PCIe ports
ACPI / hotplug / PCI: Runtime resume bridge before rescan
PCI: Power on bridges before scanning new devices
PCI: Put PCIe ports into D3 during suspend
PCI: Don't clear d3cold_allowed for PCIe ports
PCI / PM: Enforce type casting for pci_power_t
* pci/virtualization:
PCI: Add ACS quirk for Solarflare SFC9220
PCI: Add DMA alias quirk for Adaptec 3805
PCI: Mark Atheros AR9485 and QCA9882 to avoid bus reset
PCI: Add function 1 DMA alias quirk for Marvell 88SE9182
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: David Daney <david.daney@cavium.com>
Paul Gortmaker [Sat, 2 Jul 2016 23:13:32 +0000 (19:13 -0400)]
PCI: thunder-ecam: Make explicitly non-modular
This code is not being built as a module by anyone:
drivers/pci/host/Kconfig:config PCI_HOST_THUNDER_ECAM
drivers/pci/host/Kconfig: bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: David Daney <david.daney@cavium.com>
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog, remove "Module" from author comment] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Phil Edworthy <phil.edworthy@renesas.com> CC: Valentine Barshak <valentine.barshak@cogentembedded.com>
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog, remove "Module" from author comment] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Phil Edworthy <phil.edworthy@renesas.com>
Paul Gortmaker [Sat, 2 Jul 2016 23:13:28 +0000 (19:13 -0400)]
PCI: mvebu: Make explicitly non-modular
This code is not being built as a module by anyone:
drivers/pci/host/Kconfig:config PCI_MVEBU
drivers/pci/host/Kconfig: bool "Marvell EBU PCIe controller"
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog, remove "Module" from author comment] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Jason Cooper <jason@lakedaemon.net>
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com>
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com>
Paul Gortmaker [Sat, 2 Jul 2016 23:13:23 +0000 (19:13 -0400)]
PCI: designware-plat: Make it explicitly non-modular
This code is not being built as a module by anyone:
drivers/pci/host/Kconfig:config PCIE_DW_PLAT
drivers/pci/host/Kconfig: bool "Platform bus based DesignWare PCIe Controller"
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.
Replace module_platform_driver() with builtin_platform_driver(), which uses
the same init level priority, so init ordering is unchanged.
Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
[bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Edward Cree [Thu, 28 Jul 2016 17:13:56 +0000 (18:13 +0100)]
PCI: Add ACS quirk for Solarflare SFC9220
The Solarflare SFC9220 apparently lacks an ACS capability, but does not
perform peer-to-peer between functions. Add a quirk so we know about this
isolation.
[bhelgaas: changelog] Signed-off-by: Edward Cree <ecree@solarflare.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Thomas Petazzoni [Thu, 30 Jun 2016 09:32:32 +0000 (11:32 +0200)]
arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700
Add the SoC-level description of the PCIe controller found on the Marvell
Armada 3700 and enable this PCIe controller on the development board for
this SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Stephen Warren [Mon, 25 Jul 2016 21:02:27 +0000 (16:02 -0500)]
PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values
The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.
For reference, the values are all documented in NV bug 1771116 comment 20.
The ASIC team has validated all these values, except for the Tegra20 value
which is simply left unchanged in this patch.
Stephen Warren [Mon, 25 Jul 2016 21:02:21 +0000 (16:02 -0500)]
PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs
tegra_pcie_phy_power_on() calls tegra_pcie_phy_enable() only for legacy
SoCs. However, part of tegra_pcie_phy_enable() needs to happen in all
cases. Move that code up one level into tegra_pcie_phy_power_on().
[bhelgaas: changelog] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
pcibios_min_mem only exists on 32-bit ARM, so using it in pci-tegra.c
prevents the driver from being used on other arches.
In __pci_assign_resource(), we clip the available area based on
PCIBIOS_MIN_MEM. On 32-bit ARM, this is pcibios_min_mem, with a default
value of 0x01000000. For Tegra, we discover the space available for PCI
resource allocation from the device tree, and the lowest address that will
ever be available is 0x12000000 (on Tegra124).
The Tegra windows are always higher than the default pcibios_min_mem, so
the __pci_assign_resource() has no effect, so there's no need to adjust
pcibios_min_mem here.
PCI: tegra: Use lower-case hex consistently for register definitions
Most of the register definitions use lowercase hexadecimal values, with a
few exceptions using uppercase. Convert the latter to be more in line with
the former.
Keith Busch [Fri, 22 Jul 2016 03:40:28 +0000 (21:40 -0600)]
PCI: Allow additional bus numbers for hotplug bridges
A user may hot add a switch requiring more than one bus to enumerate. This
previously required a system reboot if BIOS did not sufficiently pad the
bus resource, which they frequently don't do.
Add a kernel parameter so a user can specify the minimum number of bus
numbers to reserve for a hotplug bridge's subordinate buses so rebooting
won't be necessary.
The default is 1, which is equivalent to previous behavior.
Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Keith Busch [Wed, 6 Jul 2016 16:06:00 +0000 (10:06 -0600)]
PCI: Bind DPC to Root Ports as well as Downstream Ports
PCIe port type values are not flags, so OR'ing them is not correct.
Previously the result was equivalent to PCIe Downstream Ports, so we were
missing binding to DPC-capable Root Ports.
Change the type to 'any' so we can bind to both port types. While this
will cause the code to check Upstream Ports, the driver won't claim them
since they are not DPC-capable.
Reported-by: Alexander Antonov <alexanderx.v.antonov@intel.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Mika Westerberg <mika.westerberg@linux.intel.com>
SR-IOV disabled from the host causes a memory leak. pci-hyperv usually
first receives a PCI_EJECT notification and then proceeds to delete the
hpdev list entry in hv_eject_device_work(). Later in hv_msi_free() since
the device is no longer on the device list hpdev is NULL and hv_msi_free
returns without freeing int_desc as part of hv_int_desc_free().
Ley Foon Tan [Tue, 21 Jun 2016 08:53:13 +0000 (16:53 +0800)]
PCI: altera: Poll for link up status after retraining the link
Some PCIe devices take a long time to reach link up state after retrain.
Poll for link up status after retraining the link. This is to make sure
the link is up before we access configuration space.
Ben Dooks [Fri, 17 Jun 2016 15:05:13 +0000 (16:05 +0100)]
PCI: Include <asm/dma.h> for isa_dma_bridge_buggy
At least on arm, <asm/dma.h> does not get included when building
drivers/pci/pci.o. This causes the following build warning which can be
fixed by including <asm/dma.h>:
drivers/pci/pci.c:37:5: warning: symbol 'isa_dma_bridge_buggy' was not declared. Should it be static?
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The switch is the only statement in the resource_list_for_each_entry()
loop, so remove unnecessary "continue" statements in the switch. Simplify
checking for the required non-prefetchable memory aperture.
Bjorn Helgaas [Mon, 6 Jun 2016 20:55:04 +0000 (15:55 -0500)]
PCI: tegra: Remove top-level resource from hierarchy
41534e53786d ("PCI: tegra: Implement a proper resource hierarchy") did two
things:
1) It added a top-level resource that encloses all resources declared in
the DT description, including registers and bridge apertures, and
2) It requested the bridge apertures, which means the PCI core can track
the resources used by PCI devices below the bridge.
The latter is necessary, but the former is questionable because there's no
guarantee that the bridge registers and the apertures are contiguous. In
this example:
the resource tree claims that [mem 0x00003a00-0x0fffffff] is consumed by
/pcie-controller@00003000, but it's not mentioned in the DT, and it might
actually be used by other devices.
Remove the top-level resource so we don't claim more than the device
actually consumes.
This reintroduces the problem that we can't match the resources, e.g.,
"pads", "afi", "cs", etc., to the DT device. I think this should be solved
by having the DT core request all resources of all devices in the DT (it
does not do that today). If a driver claims the device, it can request the
resources it uses. For example:
Bjorn Helgaas [Sat, 28 May 2016 23:37:46 +0000 (18:37 -0500)]
PCI: rcar: Simplify host bridge window iteration
The switch is the only statement in the resource_list_for_each_entry()
loop, so remove unnecessary cases and "continue" statements in the switch.
Inline rcar_pcie_release_of_pci_ranges(), which is only called once.
Bjorn Helgaas [Tue, 21 Jun 2016 14:19:34 +0000 (09:19 -0500)]
PCI: rcar: Drop gen2 dummy I/O port region
Previously we added a dummy I/O port region even though the R-Car
controller doesn't support PCI port I/O. This resulted in bogus root bus
resources like this:
pci_bus 0000:00: root bus resource [io 0xee080000-0xee0810ff]
pci_bus 0000:00: root bus resource [mem 0xee080000-0xee0810ff]
Drop the unused dummy I/O port region and set struct hw_pci.io_optional so
the ARM PCI code doesn't add a default one for us.
Bjorn Helgaas [Thu, 23 Jun 2016 16:33:24 +0000 (11:33 -0500)]
unicore32/PCI: Remove pci=firmware command line parameter handling
Remove support for the "pci=firmware" command line parameter, which was
way to keep the kernel from changing any PCI BAR assignments. This was
copied from ARM, but is not actually needed on unicore32.
The corresponding ARM support was removed by 903589ca7165 ("ARM: 8554/1:
kernel: pci: remove pci=firmware command line parameter handling").
On systems with PCI_PROBE_ONLY set, we rely on BAR assignments from
firmware. Previously we did not insert those resources into the resource
tree, so we had to skip pci_enable_resources() because it fails if
resources are not in the resource tree.
Now that we *do* insert resources even when PCI_PROBE_ONLY is set, we no
longer need the ARM-specific pcibios_enable_device(). Remove it so we
use the generic version.
[bhelgaas: changelog] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Russell King <linux@arm.linux.org.uk>
On systems with PCI_PROBE_ONLY set, we rely on BAR assignments from
firmware. Previously we did not insert those resources into the resource
tree, so we had to skip pci_enable_resources() because it fails if
resources are not in the resource tree.
Now that we *do* insert resources even when PCI_PROBE_ONLY is set, we no
longer need the ARM64-specific pcibios_enable_device(). Remove it so we
use the generic version.
Bjorn Helgaas [Thu, 23 Jun 2016 21:32:20 +0000 (16:32 -0500)]
MIPS/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups
We claim PCI BAR and bridge window resources in pci_bus_assign_resources(),
but when PCI_PROBE_ONLY is set, we treat those resources as immutable and
don't call pci_bus_assign_resources(), so the resources aren't put in the
resource tree.
When the resources aren't in the tree, they don't show up in /proc/iomem,
we can't detect conflicts, and we need special cases elsewhere for
PCI_PROBE_ONLY or resources without a parent pointer.
Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case.
If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix
the conflicts. Previously we didn't notice the conflicts, but now we will,
which may expose new failures.
Lorenzo Pieralisi [Thu, 23 Jun 2016 10:36:22 +0000 (11:36 +0100)]
ARM/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups
We claim PCI BAR and bridge window resources in pci_bus_assign_resources(),
but when PCI_PROBE_ONLY is set, we treat those resources as immutable and
don't call pci_bus_assign_resources(), so the resources aren't put in the
resource tree.
When the resources aren't in the tree, they don't show up in /proc/iomem,
we can't detect conflicts, and we need special cases elsewhere for
PCI_PROBE_ONLY or resources without a parent pointer.
Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case.
If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix
the conflicts. Previously we didn't notice the conflicts, but now we will,
which may expose new failures.
[bhelgaas: changelog, add resource comment, remove size/assign comments] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Russell King <linux@armlinux.org.uk>
Lorenzo Pieralisi [Wed, 8 Jun 2016 11:04:48 +0000 (12:04 +0100)]
PCI: generic: Claim bus resources on PCI_PROBE_ONLY set-ups
We claim PCI BAR and bridge window resources in pci_bus_assign_resources(),
but when PCI_PROBE_ONLY is set, we treat those resources as immutable and
don't call pci_bus_assign_resources(), so the resources aren't put in the
resource tree.
When the resources aren't in the tree, they don't show up in /proc/iomem,
we can't detect conflicts, and we need special cases elsewhere for
PCI_PROBE_ONLY or resources without a parent pointer.
Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case.
If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix
the conflicts. Previously we didn't notice the conflicts, but now we will,
which may expose new failures.
[bhelgaas: changelog, summarize comment] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com> CC: Arnd Bergmann <arnd@arndb.de> CC: David Daney <david.daney@cavium.com>
Lorenzo Pieralisi [Wed, 8 Jun 2016 11:04:47 +0000 (12:04 +0100)]
PCI: Add generic pci_bus_claim_resources()
All PCI resources (bridge windows and BARs) should be inserted in the
iomem_resource and ioport_resource trees so we know what space is occupied
and what is available for other devices. There's nothing arch-specific
about this, but it is currently done by arch-specific code.
Add a generic pci_bus_claim_resources() interface so we can migrate away
from the arch-specific code.
[bhelgaas: changelog] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Yinghai Lu <yinghai@kernel.org>
Johannes Thumshirn [Tue, 7 Jun 2016 07:44:06 +0000 (09:44 +0200)]
alx: Use pci_(request|release)_mem_regions
Now that we do have pci_request_mem_regions() and pci_release_mem_regions()
at hand, use it in the ethernet drivers.
Suggested-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> CC: Jay Cliburn <jcliburn@gmail.com> CC: Chris Snook <chris.snook@gmail.com> CC: David S. Miller <davem@davemloft.net>
Johannes Thumshirn [Tue, 7 Jun 2016 07:44:05 +0000 (09:44 +0200)]
ethernet/intel: Use pci_(request|release)_mem_regions
Now that we do have pci_request_mem_regions() and pci_release_mem_regions()
at hand, use it in the Intel ethernet drivers.
Suggested-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> CC: David S. Miller <davem@davemloft.net>
Johannes Thumshirn [Tue, 7 Jun 2016 07:44:03 +0000 (09:44 +0200)]
lpfc: Use pci_(request|release)_mem_regions
Now that we do have pci_request_mem_regions() and pci_release_mem_regions()
at hand, use it in the lpfc driver.
Suggested-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Dick Kennedy <dick.kennedy@broadcom.com> CC: James Smart <james.smart@avagotech.com> CC: James E.J. Bottomley <jejb@linux.vnet.ibm.com> CC: Martin K. Petersen <martin.petersen@oracle.com>
Johannes Thumshirn [Tue, 7 Jun 2016 07:44:01 +0000 (09:44 +0200)]
PCI: Add helpers to request/release memory and I/O regions
Add helpers to request and release a device's memory or I/O regions.
With these helpers in place, one does not need to select a device's memory
or I/O regions with pci_select_bars() prior to requesting or releasing
them.
Suggested-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
PCI: Extending pci=resource_alignment to specify device/vendor IDs
Some uio-based PCI drivers, e.g., uio_cif do not work if the assigned PCI
memory resources are not page aligned.
By using the kernel option "pci=resource_alignment" it is possible to force
single PCI boards to use page alignment for their memory resources.
However, this is fairly cumbersome if several of these boards are in use
as the specification of the cards has to be done via PCI bus/slot/function
number which might change, e.g., by adding another board.
Extend the kernel option "pci=resource_alignment" to allow specification of
relevant devices via PCI device/vendor (and subdevice/subvendor) IDs. The
specification of the devices via device/vendor is indicated by a leading
string "pci:" as argument to "pci=resource_alignment". The format of the
specification is pci:<vendor>:<device>[:<subvendor>:<subdevice>]
Bjorn Helgaas [Tue, 21 Jun 2016 15:54:29 +0000 (10:54 -0500)]
ARM: Make PCI I/O space optional
For callers of pci_common_init_dev(), we previously always required a PCI
I/O port resource. If the caller's ->setup() function had added an I/O
resource, we used that; otherwise, we added a default 64K I/O port space
for it.
There are PCI host bridges that do not support I/O port space, and we
should not add fictitious spaces for them.
If a caller sets struct hw_pci.io_optional, assume it is responsible for
adding any I/O port resource it desires, and do not add any default I/O
port space.
The switch is the only statement in the resource_list_for_each_entry()
loop, so remove unnecessary "continue" statements in the switch. Remove
unnecessary "goto" statements and label. Simplify checking for the
required non-prefetchable memory aperture.
Keith Busch [Mon, 20 Jun 2016 15:39:53 +0000 (09:39 -0600)]
x86/PCI: VMD: Separate MSI and MSI-X vector sharing
Child devices in a VMD domain that want to use MSI are slowing down MSI-X
using devices sharing the same vectors. Move all MSI usage to a single VMD
vector, and MSI-X devices can share the rest.
Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jon Derrick <jonathan.derrick@intel.com>
Jon Derrick [Mon, 20 Jun 2016 15:39:51 +0000 (09:39 -0600)]
x86/PCI: VMD: Use lock save/restore in interrupt enable path
Enabling interrupts may result in an interrupt raised and serviced while
VMD holds a lock, resulting in contention with the spin lock held while
enabling interrupts.
The solution is to disable preemption and save/restore the state during
interrupt enable and disable.
Fixes lockdep:
======================================================
[ INFO: HARDIRQ-safe -> HARDIRQ-unsafe lock order detected ]
4.6.0-2016-06-16-lockdep+ #47 Tainted: G E
------------------------------------------------------
kworker/0:1/447 [HC0[0]:SC0[0]:HE0:SE1] is trying to acquire:
(list_lock){+.+...}, at: [<ffffffffa04eb8fc>] vmd_irq_enable+0x3c/0x70 [vmd]
and this task is already holding:
(&irq_desc_lock_class){-.-...}, at: [<ffffffff810e1ff6>] __setup_irq+0xa6/0x610
which would create a new lock dependency:
(&irq_desc_lock_class){-.-...} -> (list_lock){+.+...}
The switch is the only statement in the resource_list_for_each_entry()
loop, so remove unnecessary "continue" statements in the switch. Simplify
checking for the required non-prefetchable memory aperture. Inline
altera_pcie_release_of_pci_ranges(), which is only called once.
Bjorn Helgaas [Tue, 31 May 2016 16:26:01 +0000 (11:26 -0500)]
PCI: xilinx-nwl: Free bridge resource list on failure
of_pci_get_host_bridge_resources() allocates a list of resources for host
bridge windows. If we fail after allocating that list, free it before we
return error.
Bjorn Helgaas [Tue, 31 May 2016 16:49:14 +0000 (11:49 -0500)]
PCI: xilinx: Free bridge resource list on failure
of_pci_get_host_bridge_resources() allocates a list of resources for host
bridge windows. If we fail after allocating that list, free it before we
return error.
Bjorn Helgaas [Tue, 31 May 2016 16:07:30 +0000 (11:07 -0500)]
PCI: xgene: Free bridge resource list on failure
of_pci_get_host_bridge_resources() allocates a list of resources for host
bridge windows. If we fail after allocating that list, free it before we
return error.
Bjorn Helgaas [Tue, 31 May 2016 16:14:08 +0000 (11:14 -0500)]
PCI: designware: Free bridge resource list on failure
of_pci_get_host_bridge_resources() allocates a list of resources for host
bridge windows. If we fail after allocating that list, free it before we
return error.
Lukas Wunner [Fri, 13 May 2016 11:15:31 +0000 (13:15 +0200)]
PCI: pciehp: Ignore interrupts during D3cold
If a hotplug port is suspended to D3cold, its slot status register cannot
be read. If that hotplug port happens to share its IRQ with other devices,
whenever an interrupt occurs for one of these devices, pciehp logs a
"no response from device" message and tries to read the PCI_EXP_SLTSTA
register, even though we know that will fail.
Bjorn Helgaas [Fri, 17 Jun 2016 20:23:52 +0000 (15:23 -0500)]
PCI: Document connection between pci_power_t and hardware PM capability
The dev.pme_support field, pci_pm_init(), pci_pme_capable(), and
pci_raw_set_power_state() depend on the fact that the pci_power_t values
(PCI_D0, PCI_D1, etc.) match the definition of the Capabilities PME_Support
and the Control/Status PowerState fields in the Power Management capability
(see PCI Bus Power Management spec r1.2, sec 3.2.3).
Add a note to this effect at the pci_power_t typedef.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Bjorn Helgaas [Fri, 17 Jun 2016 19:43:34 +0000 (14:43 -0500)]
sparc/PCI: Implement pci_resource_to_user() with pcibios_resource_to_bus()
"User" addresses are shown in /sys/devices/pci.../.../resource and
/proc/bus/pci/devices and used as mmap offsets for /proc/bus/pci/BB/DD.F
files. On sparc, these are PCI bus addresses, i.e., raw BAR values.
Previously pci_resource_to_user() computed the user address by
subtracting either pbm->io_space.start or pbm->mem_space.start from the
resource start.
We've already told the PCI core about those offsets here:
Bjorn Helgaas [Fri, 17 Jun 2016 19:43:34 +0000 (14:43 -0500)]
powerpc/pci: Implement pci_resource_to_user() with pcibios_resource_to_bus()
"User" addresses are shown in /sys/devices/pci.../.../resource and
/proc/bus/pci/devices and used as mmap offsets for /proc/bus/pci/BB/DD.F
files. For I/O port resources on powerpc, these are PCI bus addresses,
i.e., raw BAR values.
Previously pci_resource_to_user() computed the user address by subtracting
"hose->io_base_virt - _IO_BASE" from the resource start:
Bjorn Helgaas [Fri, 17 Jun 2016 19:43:34 +0000 (14:43 -0500)]
microblaze/PCI: Implement pci_resource_to_user() with pcibios_resource_to_bus()
"User" addresses are shown in /sys/devices/pci.../.../resource and
/proc/bus/pci/devices and used as mmap offsets for /proc/bus/pci/BB/DD.F
files. For I/O port resources on microblaze, these are PCI bus addresses,
i.e., raw BAR values.
Previously pci_resource_to_user() computed the user address by subtracting
"hose->io_base_virt - _IO_BASE" from the resource start:
Bjorn Helgaas [Fri, 17 Jun 2016 19:43:34 +0000 (14:43 -0500)]
PCI: Unify pci_resource_to_user() declarations
Replace the pci_resource_to_user() declarations in each arch that defines
HAVE_ARCH_PCI_RESOURCE_TO_USER with a single one in linux/pci.h.
Change the MIPS static inline implementation to a non-inline version so the
static inline doesn't conflict with the new non-static linux/pci.h
declaration.
The microblaze __pci_mmap_set_pgprot() was apparently copied from powerpc,
where it computes either an uncacheable pgprot_t or a write-combining one.
But on microblaze, we always use the regular uncacheable pgprot_t.
Remove the useless code in __pci_mmap_set_pgprot() and inline it at the
only call site.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
Yinghai Lu [Fri, 17 Jun 2016 19:43:33 +0000 (14:43 -0500)]
powerpc/pci: Remove __pci_mmap_set_pgprot()
The powerpc-specific __pci_mmap_set_pgprot() does two things:
1) Disables write combining for I/O port space mappings
This only affects procfs mappings. The pci_mmap_resource() sysfs path
only requests write combining for resources with IORESOURCE_PREFETCH
set, which doesn't include I/O resources.
The only way to request write combining for I/O port space mappings
was via the PCIIOC_WRITE_COMBINE ioctl and the proc_bus_pci_mmap()
path, and we recently changed that path to ignore write combining for
I/O, so this code in powerpc is no longer needed.
2) Automatically enables write combining for mappings of prefetchable
resources, even if not requested by the user
Both procfs (via PCIIOC_MMAP_IS_MEM and PCIIOC_WRITE_COMBINE ioctls)
and sysfs (via "resourceN_wc" files, which are created for resources
with IORESOURCE_PREFETCH) provide ways for the user to map PCI memory
space with write combining.
Users that desire write combining should use one of those ways instead
of relying on powerpc-specific behavior.
Remove the powerpc-specific __pci_mmap_set_pgprot().
The user-visible effect of this change is that powerpc users mapping
prefetchable PCI memory space via procfs without PCIIOC_WRITE_COMBINE or
via sysfs "resourceN" (not "resourceN_wc") will get regular uncacheable
mappings instead of the write combining mappings they used to get.
The new behavior matches the behavior on all other arches that support
write combining mapping.
[bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Wed, 8 Jun 2016 19:46:54 +0000 (14:46 -0500)]
PCI: Ignore write combining when mapping I/O port space
PCI exposes files like /proc/bus/pci/00/00.0 in procfs. These files
support operations like this:
ioctl(fd, PCIIOC_MMAP_IS_IO); # request I/O port space
ioctl(fd, PCIIOC_WRITE_COMBINE, 1); # request write-combining
mmap(fd, ...)
Write combining is useful on PCI memory space, but I don't think it makes
sense on PCI I/O port space.
We *could* change proc_bus_pci_ioctl() to make it impossible to set
mmap_state == pci_mmap_io and write_combine at the same time, but that
would break the following sequence, which is currently legal:
mmap(fd, ...) # default is I/O, non-combining
ioctl(fd, PCIIOC_WRITE_COMBINE, 1); # request write-combining
ioctl(fd, PCIIOC_MMAP_IS_MEM); # request memory space
mmap(fd, ...) # get write-combining mapping
Ignore the write-combining flag when mapping I/O port space.
This patch should have no functional effect, based on this analysis of all
implementations of pci_mmap_page_range():
- ia64 mips parisc sh unicore32 x86 do not support mapping of I/O port
space at all.
- arm cris microblaze mn10300 sparc xtensa support mapping of I/O port
space, but ignore the write_combine argument to pci_mmap_page_range().
- powerpc supports mapping of I/O port space and uses write_combine, and
it disables write combining for I/O port space in
__pci_mmap_set_pgprot().
This patch makes it possible to remove __pci_mmap_set_pgprot() from
powerpc, which simplifies that path.
Vitaly Kuznetsov [Fri, 17 Jun 2016 17:45:30 +0000 (12:45 -0500)]
PCI: hv: Handle all pending messages in hv_pci_onchannelcallback()
When we have an interrupt from the host we have a bit set in event page
indicating there are messages for the particular channel. We need to read
them all as we won't get signaled for what was on the queue before we
cleared the bit in vmbus_on_event(). This applies to all Hyper-V drivers
and the pass-through driver should do the same.
I did not meet any bugs; the issue was found by code inspection. We don't
have many events going through hv_pci_onchannelcallback(), which explains
why nobody reported the issue before.
While on it, fix handling non-zero vmbus_recvpacket_raw() return values by
dropping out. If the return value is not zero, it is wrong to inspect
buffer or bytes_recvd as these may contain invalid data.
Vitaly Kuznetsov [Mon, 30 May 2016 14:17:58 +0000 (16:17 +0200)]
PCI: hv: Don't leak buffer in hv_pci_onchannelcallback()
We don't free buffer on several code paths in hv_pci_onchannelcallback(),
put kfree() to the end of the function to fix the issue. Direct { kfree();
return; } can now be replaced with a simple 'break';
Arnd Bergmann [Wed, 15 Jun 2016 20:47:33 +0000 (15:47 -0500)]
PCI/MSI: irqchip: Fix PCI_MSI dependencies
The PCI_MSI symbol is used inconsistently throughout the tree, with some
drivers using 'select' and others using 'depends on', or using conditional
selects. This keeps causing problems; the latest one is a result of
ARCH_ALPINE using a 'select' statement to enable its platform-specific MSI
driver without enabling MSI:
warning: (ARCH_ALPINE) selects ALPINE_MSI which has unmet direct dependencies (PCI && PCI_MSI)
drivers/irqchip/irq-alpine-msi.c:104:15: error: variable 'alpine_msix_domain_info' has initializer but incomplete type
static struct msi_domain_info alpine_msix_domain_info = {
^~~~~~~~~~~~~~~
drivers/irqchip/irq-alpine-msi.c:105:2: error: unknown field 'flags' specified in initializer
.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^
drivers/irqchip/irq-alpine-msi.c:105:11: error: 'MSI_FLAG_USE_DEF_DOM_OPS' undeclared here (not in a function)
.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^~~~~~~~~~~~~~~~~~~~~~~~
There is little reason to enable PCI support for a platform that uses MSI
but then leave MSI disabled at compile time.
Select PCI_MSI from irqchips that implement MSI, and make PCI host bridges
that use MSI on ARM depend on PCI_MSI_IRQ_DOMAIN.
For all three architectures that support PCI_MSI_IRQ_DOMAIN (ARM, ARM64,
X86), enable it by default whenever MSI is enabled.
Keith Busch [Tue, 17 May 2016 17:22:18 +0000 (11:22 -0600)]
x86/PCI: VMD: Initialize list item in IRQ disable
Multiple calls to disable an IRQ would have caused the driver to
dereference a poisoned list item. This re-initializes the list to allow
multiple requests to disable the IRQ.
Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by Jon Derrick: <jonathan.derrick@intel.com>
projects / users / jedix / linux-maple.git / log