Ville Syrjälä [Fri, 17 May 2024 14:53:53 +0000 (17:53 +0300)]
drm/i915: Use intel_dp_has_dsc() during .compute_config()
Reuse intel_dp_has_dsc() during .compute_config() instead of
repeating some of the checks again by hand. We'll be adding
more checks to intel_dp_has_dsc() and this will make sure
we cover both .mode_valid() and .compute_config() with them.
Ville Syrjälä [Fri, 17 May 2024 14:53:51 +0000 (17:53 +0300)]
drm/i915: Extract intel_dp_has_dsc()
Extract a helper to check whether the source+sink combo
supports DSC. That basic check is needed both during mode
validation and compute config. We'll also need to add extra
checks to both places, so having a single place for it is nicer.
Jani Nikula [Fri, 7 Jun 2024 15:25:36 +0000 (18:25 +0300)]
drm/i915/gvt: use proper i915_reg_t for calc_index() parameters
In order to be able to use the proper register macros instead of the
underscore prefixed ones, pass i915_reg_t for the calc_index()
parameters.
Side note: DSPSURF is really about planes, not pipes. Fixed stride
doesn't work for plane C for CHV (but that's okay for gvt). This doesn't
support planes beyond C either. But all that is unrelated to the change
at hand.
Imre Deak [Mon, 10 Jun 2024 16:49:32 +0000 (19:49 +0300)]
drm/i915/dp: Add debugfs entry to force link retrain
Add a connector debugfs entry to force retrain an active link. This can
be used to test both custom link parameters (previously forced via the
force_link_rate/lane_count entries) or link train failure scenarios
(previously forced via the force_link_training_failure entry). The entry
will autoreset after the link-retrain is complete.
v2: Add the entry from intel_dp_link_training.c (Jani)
v3: Lock connection_mutex only for the required intel_dp state. (Ville)
Imre Deak [Mon, 10 Jun 2024 16:49:31 +0000 (19:49 +0300)]
drm/i915/dp: Add debugfs entry to force link training failure
Add a connector debugfs entry to force a failure during the following
1-2 link training. The entry will auto-reset after the specified link
training events are complete.
v2: Add the entry from intel_dp_link_training.c (Jani)
v3: Lock connection_mutex only for the required intel_dp state. (Ville)
Imre Deak [Mon, 10 Jun 2024 16:49:29 +0000 (19:49 +0300)]
drm/i915/dp: Add debugfs entries to force the link rate/lane count
Add connector debugfs entries to force the link rate/lane count to be
used by a link training afterwards. These settings will be clamped to
the supported, i.e. the source's and sink's common rate/lane count.
After forcing the link rate/lane count reset the link training
parameters and for a non-auto setting disable reducing the link
parameters via the fallback logic. The former one can be used after
testing link training failure scenarios - via debugfs entries added
later - to reset the reduced link parameters after the test.
v2:
- Add the entries from intel_dp_link_training.c (Jani)
- Rename the entries to i915_dp_set_link_rate/lane_count.
v3: (Ville)
- Rename the entries/struct fields to force_link_rate/lane_count.
- Lock connection_mutex only for the required intel_dp state.
Imre Deak [Mon, 10 Jun 2024 16:49:28 +0000 (19:49 +0300)]
drm/i915/dp_mst: Enable link training fallback for MST
Reduce the link parameters after a link training failure for MST
outputs, similarly to how this is done for SST.
For now allow the reduction only by staying in the 8b/10b vs. 128b/132b
mode. Enabling the mode switch is left for a follow-up patchset, after
taking measures ensuring that the mode switch happens properly. In
particular a rediscovery of the whole MST topology may be required for
such a switch, see the References below.
Imre Deak [Mon, 10 Jun 2024 16:49:27 +0000 (19:49 +0300)]
drm/i915/dp_mst: Reset intel_dp->link_trained during disabling
Reset the flag indicating an active link after disabling an MST link,
similarly to how this is done for SST outputs. This avoids trying to
retrain an MST link while its disabled.
Imre Deak [Mon, 10 Jun 2024 16:49:26 +0000 (19:49 +0300)]
drm/i915/dp: Disable link retraining after the last fallback step
After a link training failure if the link parameters can't be further
reduced, there is no point in trying to retrain the link in the driver.
This avoids excessive retrain attempts after detecting a bad link, for
instance while handling MST HPD IRQs, which is likely redundant as the
link training failed already twice with the same minimum link
parameters. Userspace can still try to retrain the link with these
parameters via a modeset.
While at it make the error message more accurate.
v2: Move converting the error to a debug message to the relevant
follow-up patch. (Ville)
Imre Deak [Mon, 10 Jun 2024 16:49:25 +0000 (19:49 +0300)]
drm/i915/dp: Use check link state work in the HPD IRQ handler
Simplify things by retraining a DP link if a bad link is detected in the
HPD IRQ handler from the encoder's check link state work, similarly to
how this is done after a modeset link training failure.
Imre Deak [Mon, 10 Jun 2024 16:49:24 +0000 (19:49 +0300)]
drm/i915/dp: Use check link state work in the detect handler
Simplify things by retraining a DP link if a bad link is detected in the
connector detect handler from the encoder's check link state work,
similarly to how this is done after a modeset link training failure.
v2: Add TODO: comment to remove the detect-time link state check.
(Ville)
Imre Deak [Mon, 10 Jun 2024 16:49:23 +0000 (19:49 +0300)]
drm/i915/dp: Use check link state work in the hotplug handler
Simplify things by retraining a DP link if a bad link is detected in the
hotplug handler from the encoder's check link state work, similarly to
how this is done after a modeset link training failure.
Imre Deak [Mon, 10 Jun 2024 16:49:22 +0000 (19:49 +0300)]
drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors
Send a modeset-retry uevent to all connectors in the same MST topology
after a link training failure and reduction of the link parameters. This
matches the way the same uevent is sent after a DP tunnel BW allocation
failure.
v2: Add NOTE that the atomic state may not be valid for SST links and
assert that it's valid for MST links. (Ville)
Imre Deak [Mon, 10 Jun 2024 16:49:21 +0000 (19:49 +0300)]
drm/i915/dp: Pass atomic state to link training function
The next patch adds sending a modeset-retry uevent after a link training
failure to all MST connectors on link. This requires the atomic state,
so pass it to intel_dp_start_link_train(). In case of SST where
retraining still happens by calling this function directly instead of a
modeset commit the atomic state is not available and NULL is passed
instead. This is ok, since in this case the encoder's only DP connector
is available from intel_dp->attached_connector not requiring the atomic
state.
v2: Add NOTE that the atomic state may not be valid for SST links and
assert that it's valid for MST links. (Ville)
Imre Deak [Mon, 10 Jun 2024 16:49:20 +0000 (19:49 +0300)]
drm/i915/dp: Reduce link params only after retrying with unchanged params
Try to maintain the current link parameters by retrying the link
training with unchanged link parameters before reducing these parameters
(sending an uevent to userspace to retrain the link instead).
Imre Deak [Mon, 10 Jun 2024 18:14:28 +0000 (21:14 +0300)]
drm/i915/dp: Recheck link state after modeset
Recheck the link state after a passing link training, with a 2 sec delay
to account for cases where the link goes bad following the link training
and the sink doesn't report this via an HPD IRQ.
The delayed work added here will be also used by a later patch after a
failed link training to try to retrain the link with unchanged link
params before reducing the link params.
v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports).
v3:
- Move the helpers to a new intel_encoder.c file, rename them
accordingly. (Ville)
- Add the work to intel_encoder instead of intel_digital_port.
- Call the encoder specific link check function via an encoder hook.
- Flush the link check work during encoder destroy from
intel_dp_encoder_flush_work().
- Flush the link check work during encoder suspend as well.
v4: Call intel_encoder_link_check_init() with a valid encoder pointer.
Imre Deak [Mon, 10 Jun 2024 16:49:18 +0000 (19:49 +0300)]
drm/i915/dp: Use a commit modeset for link retraining MST links
Instead of direct calls to the link train functions, retrain the link
via a commit modeset. The direct call means that the output port will be
disabled/re-enabled while the rest of the pipeline (transcoder) is
active, which doesn't seem to work on MST at least. It leads to
underruns and black screen, presumedly because the transcoder is not
disabled/re-enabled along the port.
Leave switching to a commit modeset on SST for a later patchset, as that
seems to work ok currently (though better to using a commit there too,
due to the suppressed underruns).
v2: Keep reverse line length order for local variables. (Ville)
Reduce the indentation in intel_dp_get_link_train_fallback_values() by
adding separate helpers to reduce the link rate and lane count. Also
simplify things by passing crtc_state to the function.
This also prepares for later patches in the patchset adding a limitation
on how the link params are reduced.
While at it use lt_dbg()/lt_err() for debug/error prints in the function
which will also print the connector/encoder prefix and add a debug print
about reducing the link parameters.
v2:
- Align reduce_lane_count()'s error handling flow with
reduce_link_rate(). (Ville, Jani)
- Use lt_dbg()/lt_err() in the function.
Imre Deak [Mon, 10 Jun 2024 16:49:14 +0000 (19:49 +0300)]
drm/i915/dp: Move link train params to a substruct in intel_dp
For clarity move the link training parameters updated during link
training based on the pass/fail LT result under a substruct in intel_dp.
This prepares for later patches in this patchset adding similar params
here. Rename intel_dp_reset_max_link_params() to
intel_dp_reset_link_params() to better reflect what state gets reset.
v2: Add the parameters to a more generic link substruct. (Jani)
Imre Deak [Mon, 10 Jun 2024 16:49:13 +0000 (19:49 +0300)]
drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs
Symbols consisting of multiple (4) TU timeslots may get split across
MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by
aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1
lane.
Atm, we also have to align the PBNs used to allocate BW along the MST
path, since DRM core keeps track of its own TU value, derived from the
PBN and that TU value must match what the driver calculates.
On some platforms the alignment is only required on 8b/10b links, a
follow-up patch will remove the limitation for those.
Imre Deak [Tue, 11 Jun 2024 15:33:51 +0000 (18:33 +0300)]
drm/i915/dp_mst: Fix DSC input BPP computation
The branch or sink device decompressing a stream may have a limitation
on the input/uncompressed BPP, which is lower than the base line BPP
(determined by the sink's EDID). In some cases a stream with an input
BPP higher than this limit will be converted automatically by the device
decompressing the stream, by truncating the BPP, however in some cases
- seen at least in Dell dock's DP->HDMI converters - the decompression
will fail.
Fix the above by limiting the input BPP correctly. This is done already
correctly for SST outputs.
Stanislav Lisovskiy [Fri, 7 Jun 2024 07:54:57 +0000 (10:54 +0300)]
drm/i915: Rename all bigjoiner to joiner
Lets unify both bigjoiner and ultrajoiner under simple "joiner" name,
because in future we might have multiple configurations, involving
multiple bigjoiners, ultrajoiner, however it is possible to use
same api for handling both.
v2: - Renamed back some bigjoiner specific parts for now(Ville)
Jouni Högander [Fri, 7 Jun 2024 13:49:13 +0000 (16:49 +0300)]
drm/i915/psr: Print Panel Replay status instead of frame lock status
Currently Panel Replay status printout is printing frame lock status. It
should print Panel Replay status instead. Panel Replay status register
field follows PSR status register field. Use existing PSR code for that.
Jouni Högander [Fri, 7 Jun 2024 13:49:12 +0000 (16:49 +0300)]
drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.
Jouni Högander [Fri, 7 Jun 2024 13:49:10 +0000 (16:49 +0300)]
drm/i915/psr: Split enabling sink for PSR and Panel Replay
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit
definitions for Panel Replay. Even thought PSR and Panel Replay enable
registers do have common bits they still have also different bits and same
bits with different meaning. For sake of clarity split enabling sink to PSR
and Panel Replay specific parts.
Also fix issue caused by using psr->panel_replay_enabled to early.
Jouni Högander [Fri, 7 Jun 2024 13:49:07 +0000 (16:49 +0300)]
drm/i915/display: Take panel replay into account in vsc sdp unpacking
Currently intel_dp_vsc_sdp_unpack is not taking into account Panel Replay
vsc sdp. Fix this by adding vsc sdp revision 0x6 and length 0x10 into
intel_dp_vsc_sdp_unpack
Jouni Högander [Fri, 7 Jun 2024 13:49:05 +0000 (16:49 +0300)]
drm/i915/alpm: Do not use fast_wake_lines for aux less wake time
We want to have own variables for fast wake lines and aux less wake
time. It might be needed to choose if we can enable Panel Replay Selective
Update or PSR2.
Also currently aux less wake time is overwritten by calculated fast wake
time.
v2:use aux less wake time in intel_alpm_lobf_compute_config
Mitul Golani [Mon, 10 Jun 2024 07:22:02 +0000 (12:52 +0530)]
drm/i915: Compute CMRR and calculate vtotal
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as small subset of
FAVT mode, when Panel is running on Fixed refresh rate
and on VRR framework then only enable CMRR to match with
actual refresh rate.
--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]
--v3:
- Removing RFC tag.
--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.
--v5:
- Correct vtotal paramas accuracy and add 2 digit precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
--v7:
- Update commit message to avoid confusion with Legacy VRR (Ankit).
- Add cmrr.enable in last, so remove from this patch.
--v8:
- Set cmrr.enable in current patch instead of separate patch (Ankit).
- Since vrr.enable and cmrr.enable are not mutually exclusive,
handle accordingly (Ankit).
- is_edp is not required inside is_cmrr_frac_required function (Ankit).
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
--v9:
- Move patch to last and set other bits before computing
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Mitul Golani [Mon, 10 Jun 2024 07:22:01 +0000 (12:52 +0530)]
drm/i915/display: Compute vrr vsync params
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
--v3:
- vrr.enable and cmrr.enable check together is not required as both
will be true at the same point in time. (Ankit)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Mitul Golani [Mon, 10 Jun 2024 07:21:56 +0000 (12:51 +0530)]
drm/i915: Define and compute Transcoder CMRR registers
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
--v4:
- Update place holder for CMRR register definition. (Jani)
--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.
--v6:
- Fixed indentation. (Jani)
- Add dependency header intel_display_reg_defs.h. (Jani)
- Rename file name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Mitul Golani [Mon, 10 Jun 2024 07:21:54 +0000 (12:51 +0530)]
drm/i915: Update indentation for VRR registers and bits
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
--v2:
- Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit).
- Fix all indentation related VRR registers and bits instead of
checkpatch one.
Ville Syrjälä [Wed, 5 Jun 2024 13:47:56 +0000 (16:47 +0300)]
drm/i915/bios: Define the "luminance and gamma" sub-struct of block 46
Since BDB version 211 block 46 has included more luminance and
gamma related information. Define it fully. The data is semi-based
on DisplayID v2.0 apparently.
The VBT spec does a very poor job of defining how the chromaticity
coordinates in block 46 are laid out. After double checking the
Windows implementation it turns out these more or less match the
EDID definition, where the 10bit values are split into 2bit + 8bit
chunks. Adjust our struct definition to reflect that.
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