Hawking Zhang [Mon, 10 Jun 2019 13:39:29 +0000 (21:39 +0800)]
drm/amd/powerplay: move get_thermal_temperature_range to ppt funcs
The thermal policy could be ASIC specific ones and depends on structures
in pptable. As a result, get_thermal_temperature_range should be implemented
as ppt funcs instead of smu funcs
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 16 May 2019 07:06:25 +0000 (15:06 +0800)]
drm/amd/powerplay: enable uclk dpm default on navi10
enable uclk (mclk) dpm by default on navi10
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Tue, 14 May 2019 09:08:36 +0000 (17:08 +0800)]
drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10
on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk
deep sleep kicking in.
Kevin Wang [Tue, 14 May 2019 06:01:01 +0000 (14:01 +0800)]
drm/amd/powerplay: add sclk sysfs interface support for navi10
miss sclk support in force_clk_levels function
Signed-off-by: Kevin Wang <kevin1.Wang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 13 May 2019 08:52:22 +0000 (16:52 +0800)]
drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board
disable DPM UCLK and SOC DS on A0 secure board
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 10 May 2019 08:31:57 +0000 (16:31 +0800)]
drm/amd/powerplay/smu11: add secure board check function (v2)
To determine whether the board is secure or not.
v2: rebase (Alex)
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 13 May 2019 08:56:17 +0000 (16:56 +0800)]
drm/amd/powerplay/smu11: enable ds socclk by default
Enable soc clk deep sleep.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 10 May 2019 07:29:11 +0000 (15:29 +0800)]
drm/amd/powerplay: fix amdgpu_pm_info show gpu load error
due to the smu dma/RTOS restriction, the interval of catching smu
metric table should be more than 1ms. otherwise it will cause the gpu
activity data corruption.
Signed-off-by:Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 6 May 2019 10:55:23 +0000 (18:55 +0800)]
drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume
CSIB BO is required to be pinned down to guarantee
bo is always valid when resume, and to be unpinned it
so that its content can be saved during suspend.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
The uclk dpm feature is not supported by some certain navi10
board like 18202, while supported by some board like 18201.
It causes modprobe failure on 18202 board.
[how]
Disabled this feature by default, it can be enabled by module parameter
uclk_dpm_support=1.
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 30 May 2019 04:15:54 +0000 (23:15 -0500)]
drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workable
This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact
VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now.
Huang Rui [Sun, 31 Mar 2019 08:08:21 +0000 (16:08 +0800)]
drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2)
This header is actually for each asic, so we should not include in smu_v11_0.c.
And rename the one for navi10.
v2: add hack for XGMI (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to
asic level.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 07:53:42 +0000 (15:53 +0800)]
drm/amd/powerplay: introduce smu power source type to handle AC/DC source for each asic
This patch introduces new smu power source type, it's to handle the different
AC/DC source defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 07:15:49 +0000 (15:15 +0800)]
drm/amd/powerplay: move Watermarks_t uses into asic level
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid
the conflicts with different asic.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 06:53:23 +0000 (14:53 +0800)]
drm/amd/powerplay: move SmuMetrics_t uses into asic level
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the
conflicts with different asic.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 05:25:04 +0000 (13:25 +0800)]
drm/amd/powerplay: move PPTable_t uses into asic level
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the
conflicts with different asic.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 04:49:11 +0000 (12:49 +0800)]
drm/amd/powerplay: use the table size member in the structure instead of getting directly
This patch uses the table size member in the structure instead of getting
directly, because the table is different in each asic.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 04:02:00 +0000 (12:02 +0800)]
drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the input
Table id may be different for each asic, so it's good to use this as the input
for common interface.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 31 Mar 2019 03:53:28 +0000 (11:53 +0800)]
drm/amd/powerplay: add tables_init interface for each asic
The smc tables defines should be in the asic level.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 29 Mar 2019 10:07:23 +0000 (18:07 +0800)]
drm/amd/powerplay: init table_count for smu tables on asic level
TABLE_COUNT should be inited in asic level. Because the value may be different
on each asic even on the same ip.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 29 Mar 2019 09:52:11 +0000 (17:52 +0800)]
drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic
This patch introduces new smu table type, it's to handle the different smu table
defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 30 May 2019 04:14:33 +0000 (23:14 -0500)]
drm/amd/powerplay: introduce smu feature type to handle feature mask for each asic
This patch introduces new smu feature type, it's to handle the different feature
mask defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 24 Mar 2019 11:22:07 +0000 (19:22 +0800)]
drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic
This patch introduces new smu clk type, it's to handle the different ppclk
defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 28 Mar 2019 09:14:42 +0000 (17:14 +0800)]
drm/amd/powerplay: enable DCEFCLK dpm support
Enabale DCEFCLK dpm on navi10
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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