Michael Walle [Wed, 16 Feb 2022 08:20:20 +0000 (09:20 +0100)]
pinctrl: ocelot: fix confops resource index
Prior to commit ad96111e658a ("pinctrl: ocelot: combine get resource and
ioremap into single call") the resource index was 1, now it is 0. But 0
is the base region for the pinctrl block. Fix it.
I noticed this because there was an error that the memory region was
ioremapped twice.
Fixes: ad96111e658a ("pinctrl: ocelot: combine get resource and ioremap into single call") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Colin Foster <colin.foster@in-advantage.com> Link: https://lore.kernel.org/r/20220216082020.981797-1-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 28 Feb 2022 22:55:50 +0000 (23:55 +0100)]
Merge tag 'intel-pinctrl-v5.18-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.18-1
* Introduce support for Alder Lake-N (required to revert misplaced ID)
* Add support for Raptor Lake-S
* Add support for Ice Lake-N (MacBookPro16,2)
* Miscellaneous fixes
The following is an automated git shortlog grouped by driver:
alderlake:
- Add Intel Alder Lake-N pin controller support
- Add Raptor Lake-S ACPI ID
baytrail:
- Clear direct_irq_en flag on broken configs
icelake:
- Add Ice Lake-N PCH pin controller support
intel:
- Fix a glitch when updating IRQ flags on a preconfigured line
- fix unexpected interrupt
Place correctly CONFIG_PINCTRL_ST in the Makefile:
- Place correctly CONFIG_PINCTRL_ST in the Makefile
Linus Walleij [Sun, 27 Feb 2022 01:18:54 +0000 (02:18 +0100)]
Merge tag 'renesas-pinctrl-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.18 (take two)
- Share more pin group data, to reduce kernel size and ease review,
- Improve the pin control table validator,
- Add support for the new R-Car S4-8 SoC,
- Miscellaneous fixes and improvements.
Linus reports that some Renesas pin control sub-drivers are still
including <linux/gpio.h> instead of <linux/gpio/driver.h>. As these
sub-drivers don't need either, the includes can just be removed.
Geert Uytterhoeven [Mon, 21 Feb 2022 16:21:58 +0000 (17:21 +0100)]
pinctrl: renesas: checker: Fix miscalculation of number of states
The checker failed to validate all enum IDs in the description of a
register with fixed-width register fields, due to a miscalculation of
the number of described states: each register field of n bits can have
"1 << n" possible states, not "1".
Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked
(SH-Mobile AG5 has more than 4000 enum IDs defined).
Andy Shevchenko [Tue, 15 Feb 2022 15:28:00 +0000 (17:28 +0200)]
pinctrl: icelake: Add Ice Lake-N PCH pin controller support
This adds pinctrl/GPIO support for Intel Ice Lake-N PCH. The Ice Lake-N
PCH GPIO is based on the same version of the Intel GPIO hardware than
Intel Cannon Lake with different set of pins and ACPI ID.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Tue, 15 Feb 2022 15:27:59 +0000 (17:27 +0200)]
pinctrl: alderlake: Add Intel Alder Lake-N pin controller support
This change driver adds pinctrl/GPIO support for Intel Alder Lake-N SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Tue, 15 Feb 2022 15:27:58 +0000 (17:27 +0200)]
pinctrl: alderlake: Add Raptor Lake-S ACPI ID
Intel Raptor Lake-S PCH has the same GPIO hardware than Alder Lake-S PCH
but the ACPI ID is different. Add this new ACPI ID to the list of supported
devices.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Geert Uytterhoeven [Thu, 23 Dec 2021 14:56:24 +0000 (15:56 +0100)]
pinctrl: renesas: checker: Validate I/O voltage configs consistency
Validate consistency of the pin control tables for pins with I/O voltage
capabilities. If a pin has I/O voltage register bits declarations
through .pin_to_pocctrl(), the SH_PFC_PIN_CFG_IO_VOLTAGE flag should be
set in the pin's configs, and vice versa.
Validate consistency of the pin control tables for pins with drive
strength capabilities. If a pin has drive strength register bits
declarations in drive_regs[], the SH_PFC_PIN_CFG_DRIVE_STRENGTH flag
should be set in the pin's configs, and vice versa.
Validate consistency of the pin control tables for pins with pull-up
and/or pull-down capabilities. If a pin has bias register bits
declarations in bias_regs[] or through .pin_to_portcr(), the
corresponding SH_PFC_PIN_CFG_PULL* flags should be set in the pin's
configs, and vice versa, and the .get_bias() and .set_bias() callbacks
should be implemented.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:56:19 +0000 (15:56 +0100)]
pinctrl: renesas: Pass sh_pfc_soc_info to rcar_pin_to_bias_reg()
Currently rcar_pin_to_bias_reg() takes a struct sh_pfc pointer, which is
only available after the pin control driver has been initialized,
thus preventing the checker from calling this function for validating
consistency of the pin control tables.
Fix this by replacing the parameter by a struct sh_pfc_soc_info pointer.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:56:18 +0000 (15:56 +0100)]
pinctrl: renesas: Factor out .pin_to_portcr() address handling
All implementations of the .pin_to_portcr() method implement the same
conversion from Port Control Register offset to virtual address. Factor
it out into the two callers.
Remove the pfc parameter, as it is no longer used.
Note that the failure handling in r8a7740_pin_to_portcr() is pro forma,
as the function is never called with an invalid pin number.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:56:17 +0000 (15:56 +0100)]
pinctrl: renesas: Remove unused pfc parameter from .pin_to_pocctrl()
The pfc parameter of the .pin_to_pocctrl() method was never used.
It is a relic of the old I/O voltage handling before commit 8775306dcf48092f ("pinctrl: sh-pfc: refactor voltage setting").
Remove the parameter, as it prevents the checker from calling this
function for validating consistency of the pin control tables.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:41:29 +0000 (15:41 +0100)]
pinctrl: renesas: r8a7791: Share MMC pin group data
Pin groups mmc_data[14] are subsets of mmc_data8.
Treat mmc_data8_b the same for consistency. Note that there is no need
to define 1-bit and 4-bit wide subsets for the b-variant, as they're
identical to the normal variants.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:41:16 +0000 (15:41 +0100)]
pinctrl: renesas: Add generic support for resizable buses
The VIN_DATA_PIN_GROUP() macro and vin_data{12,16,} unions are used to
define multiple VIN data groups with different numbers of lanes, while
referring to a single array of data pins, thus saving memory.
However, the same feature would be useful for other resizable buses,
like MMC, SDHI, QSPI, LCD, BSC, ...
Rework the mechanism for generic use:
- Use the new SH_PFC_PIN_GROUP_SUBSET() helper to remove the need for
bus-specific unions,
- Rename VIN_DATA_PIN_GROUP() to BUS_DATA_PIN_GROUP(),
- Rename the macro parameters to better reflect their purposes,
- Move the macro up, where it belongs.
Update all individual pin control drivers for the above changes.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:41:15 +0000 (15:41 +0100)]
pinctrl: renesas: Add generic support for pin group subsets
It is fairly common for the pins in a pin group to be a subset of the
pins in another pin group. Add a macro for defining a pin group that
refers to a subset of an array of pins. This allows pin groups to share
pin data, and thus save memory.
Reformat all macros that define structure initializers, to visually
resemble structure definitions:
- Move the opening curly brace to the previous line,
- Move the closing curly brace to the first position,
- Reduce indentation of the block to a single TAB, decreasing the need
for line breaks,
- Align backslashes for line continuation to the last TAB block where
possible,
Some instances of struct sh_pfc_soc_operations are called
"<soc>_pfc_ops", others are called "<soc>_pinmux_ops" or just
"pinmux_ops". Settle on the first variant, to avoid confusion with
"struct pinmux_ops" in the pinctrl core, and to increase consistency.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:41:11 +0000 (15:41 +0100)]
pinctrl: renesas: r8a77470: Reduce size for narrow VIN1 channel
The second video-in channel on RZ/G1C has only 12 data lanes, but the
pin control driver uses the vin_data union, which is meant for 24 data
lanes, thus wasting space.
Geert Uytterhoeven [Thu, 23 Dec 2021 14:28:20 +0000 (15:28 +0100)]
pinctrl: renesas: r8a7794: Add range checking to .pin_to_pocctrl()
The .pin_to_pocctrl() implementation for R-Car E2 does not perform a
full range check, unlike on all other SoCs. Add the range check, so the
checker can validate better the consistency of the pin control tables.
Samuel Holland [Wed, 16 Feb 2022 04:00:36 +0000 (22:00 -0600)]
pinctrl: sunxi: Use unique lockdep classes for IRQs
This driver, like several others, uses a chained IRQ for each GPIO bank,
and forwards .irq_set_wake to the GPIO bank's upstream IRQ. As a result,
a call to irq_set_irq_wake() needs to lock both the upstream and
downstream irq_desc's. Lockdep considers this to be a possible deadlock
when the irq_desc's share lockdep classes, which they do by default:
============================================
WARNING: possible recursive locking detected 5.17.0-rc3-00394-gc849047c2473 #1 Not tainted
--------------------------------------------
init/307 is trying to acquire lock: c2dfe27c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
but task is already holding lock: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
other info that might help us debug this:
Possible unsafe locking scenario:
stack backtrace:
CPU: 0 PID: 307 Comm: init Not tainted 5.17.0-rc3-00394-gc849047c2473 #1
Hardware name: Allwinner sun8i Family
unwind_backtrace from show_stack+0x10/0x14
show_stack from dump_stack_lvl+0x68/0x90
dump_stack_lvl from __lock_acquire+0x1680/0x31a0
__lock_acquire from lock_acquire+0x148/0x3dc
lock_acquire from _raw_spin_lock_irqsave+0x50/0x6c
_raw_spin_lock_irqsave from __irq_get_desc_lock+0x58/0xa0
__irq_get_desc_lock from irq_set_irq_wake+0x2c/0x19c
irq_set_irq_wake from irq_set_irq_wake+0x13c/0x19c
[tail call from sunxi_pinctrl_irq_set_wake]
irq_set_irq_wake from gpio_keys_suspend+0x80/0x1a4
gpio_keys_suspend from gpio_keys_shutdown+0x10/0x2c
gpio_keys_shutdown from device_shutdown+0x180/0x224
device_shutdown from __do_sys_reboot+0x134/0x23c
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
However, this can never deadlock because the upstream and downstream
IRQs are never the same (nor do they even involve the same irqchip).
Silence this erroneous lockdep splat by applying what appears to be the
usual fix of moving the GPIO IRQs to separate lockdep classes.
Fixes: a59c99d9eaf9 ("pinctrl: sunxi: Forward calls to irq_set_irq_wake") Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220216040037.22730-1-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mans Rullgard [Thu, 17 Feb 2022 13:17:37 +0000 (13:17 +0000)]
pinctrl: sunxi: do not print error message for EPROBE_DEFER
Avoid printing an error message if getting a regulator fails with
EPROBE_DEFER. This can happen if, for example, a regulator supplying
one of the main banks is controlled by a PL pin.
Linus Walleij [Sat, 19 Feb 2022 01:05:02 +0000 (02:05 +0100)]
Merge tag 'samsung-pinctrl-5.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v5.18
1. Fix OF reference leak in pinctrl driver probe error path.
2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks.
3. Accept devicetrees with GPIO pin bank definitions named with a
"-gpio-bank" suffix. This is necessary for later Samsung pinctrl
bindings dtschema.
4. Convert Samsung pinctrl bindings to dtschema.
5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts.
6. Add support for Tesla FSD SoC.
projects / users / willy / xarray.git / log