drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3846:6: warning: variable 'index' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
if (ring->is_mes_queue) {
^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3903:30: note: uninitialized use occurs here
amdgpu_device_wb_free(adev, index);
^~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3846:2: note: remove the 'if' if its condition is always false
if (ring->is_mes_queue) {
^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3839:16: note: initialize the variable 'index' to silence this warning
unsigned index;
^
= 0
Signed-off-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This was added a helper for amdgpu to workaround a runtime pm regression
caused by a runtime pm fix in efifb. We now have a better workaround
in amdgpu in
commit f95af4a9236695 ("drm/amdgpu: don't runtime suspend if there are displays attached (v3)")
so this workaround is no longer necessary. Since amdgpu was the only
user of this interface, we can remove it.
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This workaround is no longer necessary. We have a better workaround
in commit f95af4a9236695 ("drm/amdgpu: don't runtime suspend if there are displays attached (v3)").
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 5 May 2022 03:17:38 +0000 (23:17 -0400)]
drm/amdgpu/gfx11: remove some register fields that no longer exist
Some copy paste leftovers for older asics. They were protected
by __BIG_ENDIAN, so we didn't notice them initially.
Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Thu, 14 Apr 2022 14:19:13 +0000 (10:19 -0400)]
drm/amdgpu/jpeg: enable JPEG PG and CG for VCN4_0_0
Enable JPEG PG and CG for VCN4_0_0.
Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Sat, 9 Oct 2021 20:58:10 +0000 (16:58 -0400)]
drm/amdgpu/jpeg: add jpeg support for VCN4_0_0
Add jpeg support for VCN4_0_0.
Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 13 Apr 2022 15:45:03 +0000 (11:45 -0400)]
drm/amdgpu: add VCN4 ip block support
Add VCN 4.0 initialization and decoder/encoder ring functions.
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Sat, 4 Dec 2021 17:20:37 +0000 (12:20 -0500)]
drm/amdgpu: move out asic specific definition from common header
Move out asic specific definition from common header.
Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Sun, 26 Sep 2021 00:20:52 +0000 (20:20 -0400)]
drm/amdgpu: make software ring functions reuseable for newer VCN
Software ring will be supported only from VCN4
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 30 Dec 2021 11:34:16 +0000 (19:34 +0800)]
drm/amdgpu: add vcn 4_0_0 header files v7
Add VCN 4.0.0 registers
Signed-off-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley Yang [Fri, 12 Mar 2021 10:02:33 +0000 (18:02 +0800)]
drm/amdgpu/discovery: add SDMA v6_0 ip block
Add SDMA v6 ip block for asics which support it.
Signed-off-by: Stanley Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This version brings along following fixes:
- Have optc3 function accessible to newer DCN
- Add CM boot option for USB4 tunneling
- Fix system hang issue when game resolution is changed
- Remove outdated register for dcn3+
- Add new DSC interface to disconnect from pipe
- Clean up pixel format types in enum surface_pixel_format
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 23 Apr 2022 16:01:47 +0000 (12:01 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.115.0
- Add new cmd for querying HPD state
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Equate the first non-subsampled video surface format to
the enum SURFACE_PIXEL_FORMAT_SUBSAMPLE_END since it's
not a real format.
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Thu, 21 Apr 2022 20:19:34 +0000 (16:19 -0400)]
drm/amd/display: Add new DSC interface to disconnect from pipe
[Why & How]
Add new DSC interface to disconnect from pipe.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove outdated register for dcn3+
[Why & How]
Remove MPCC_OGAM_LUT_RAM_CONTROL register which is outdated.
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Tse Kaitlyn <Kaitlyn.Tse@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Commit d2069326d26c ("drm/amd/display: Reset cached PSR parameters after hibernate")
causes a system hang when game resolution is changed. Revert it.
Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Boot up behaviour may differ depending on the Connection Manager
handling USB4 tunneling.
[How]
Send boot option to firmware to indicate Connection Manager.
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Make OPTC3 function accessible to other DCN
[Why]
Newer DCN should use optc3
[How]
Declare optc3 vmin/vmax function in header.
Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add initial support for soc21 in KFD compute
driver (Mukul)
- Add new definition for soc21 device.
- Add new file for amdgpu-kfd interface for GFX11 family.
- Add new file for queue management, interrupt handling,
mqd management for GFX11 family in KFD driver.
- Related changes/updates for soc21 device in
KFD driver.
- Repurpose last 2 entries of SDMA MQD for driver use.
v2: Add an optional argument into update queue operation (Mukul)
v3: Switch to ip version check, replace kgd_dev with
amdgpu_device (Hawking)
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 13 Apr 2022 22:08:49 +0000 (18:08 -0400)]
drm/amdgpu/discovery: handle AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO in SMU
Handle SMU load ordering when firmware load type is
AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO. This works similarly
to AMDGPU_FW_LOAD_DIRECT where the SMU load order is
different from the standard ordering when front door
loading is enabled.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
For SDMA, if use the total size of SDMA TH0 and TH1 to allocate fw BO
may result to the ucode data overflow when copy ucode to BO as the PAGE
alignment.
IMU have the same issue.
Fix the above issue by alignment the fw size per fw ID.
Jack Xiao [Tue, 12 Apr 2022 20:17:41 +0000 (16:17 -0400)]
drm/amdgpu: correct cp doorbell range
1. move MES doorbell inside the mec doorbell range,
for mes belongs to mec block
2. setting the correct gfx/mec doorbell range, so that
fw can correctly detect gfx/compute work load to enter/exit
power saving state.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Tested-and-acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 31 May 2021 06:16:56 +0000 (14:16 +0800)]
drm/amdgpu/gfx: refine fw hdr check fuction
The return value of function amdgpu_ucode_hdr_version
doesn't make sense, so change it to return true when
fw header version is match with passed in parameters.
drm/amdgpu/mes: Update the doorbell function signatures
Update the function signatures for process doorbell allocations
with MES enabled to make them more generic. KFD would need to
access these functions to allocate/free doorbells when MES is
enabled.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Acked-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 26 Mar 2020 06:34:24 +0000 (14:34 +0800)]
drm/amdgpu/mes10.1: add mes self test in late init
Add MES self test in late init.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 16:23:34 +0000 (00:23 +0800)]
drm/amdgpu/mes: implement mes self test
Add mes self test to verify its fundamental functionality by
running ring test and ib test of mes kernel queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 16:18:26 +0000 (00:18 +0800)]
drm/amdgpu/mes: add ring/ib test for mes self test
Run the ring test and ib test for mes self test.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 13:38:42 +0000 (21:38 +0800)]
drm/amdgpu/mes: create gang and queues for mes self test
Create gang and queues for mes self test.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 13:36:43 +0000 (21:36 +0800)]
drm/amdgpu/mes: map ctx metadata for mes self test
Map ctx metadata for mes self test.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 16 Jun 2020 03:50:12 +0000 (11:50 +0800)]
drm/amdgpu: kiq takes charge of all queues
To make kgq/kcq and mes queue co-exist, kiq needs take charge
of all queues.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 20 Mar 2020 07:12:26 +0000 (15:12 +0800)]
drm/amdgpu: skip gds switch for mes queue
For mes manages gds allocation, skip gds switch.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 20 Mar 2020 07:07:27 +0000 (15:07 +0800)]
drm/amdgpu: skip kiq ib tests if mes enabled
For kiq conflicts with mes, skip kiq ib tests.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 20 Mar 2020 06:59:54 +0000 (14:59 +0800)]
drm/amdgpu: skip some checking for mes queue ib submission
Skip some checking for mes queue ib submission.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 31 Mar 2022 18:09:30 +0000 (14:09 -0400)]
drm/amdgpu: skip kfd routines when mes enabled
For kfd hasn't supported mes, skip kfd routines.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 10:11:15 +0000 (18:11 +0800)]
drm/amdgpu/mes: add helper functions to alloc/free ctx metadata
Add the helper functions to allocate/free context metadata.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 10:04:36 +0000 (18:04 +0800)]
drm/amdgpu/mes: implement removing mes ring
Remove the mes ring and its resources.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 09:30:00 +0000 (17:30 +0800)]
drm/amdgpu/mes: use ring for kernel queue submission
Use ring as the front end for kernel queue submission.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 09:42:01 +0000 (17:42 +0800)]
drm/amdgpu/mes: add helper function to get the ctx meta data offset
Add the helper function to get the corresponding ctx meta data offset.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 09:16:28 +0000 (17:16 +0800)]
drm/amdgpu/mes: add helper function to convert ring to queue property
Add the helper function to convert ring to queue property.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 09:08:40 +0000 (17:08 +0800)]
drm/amdgpu/mes: implement removing mes queue
Remove the MES queue from MES scheduling and free its resources.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 08:58:55 +0000 (16:58 +0800)]
drm/amdgpu/mes: implement adding mes queue
Allocate related resources for the queue and add it to mes
for scheduling.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 1 Jul 2020 06:58:46 +0000 (14:58 +0800)]
drm/amdgpu/mes: initialize mqd from queue properties
Add helper function to initialize mqd from queue properties.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 08:43:28 +0000 (16:43 +0800)]
drm/amdgpu/mes: implement resuming all gangs
Implement resuming all gangs.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 08:41:56 +0000 (16:41 +0800)]
drm/amdgpu/mes: implement suspending all gangs
Implement suspending all gangs.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 24 Mar 2022 03:35:29 +0000 (11:35 +0800)]
drm/amdgpu/mes: implement removing mes gang
Free the mes gang and its resources.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 07:27:48 +0000 (15:27 +0800)]
drm/amdgpu/mes: implement adding mes gang
Gang is a group of the same type queue, which is the scheduling
unit of mes hardware scheduler.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 07:10:55 +0000 (15:10 +0800)]
drm/amdgpu/mes: implement destroying mes process
Destroy the mes process, which free resources of the process.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 07:03:16 +0000 (15:03 +0800)]
drm/amdgpu/mes: implement creating mes process v2
Create a mes process which contains process-related resources,
like vm, doorbell bitmap, process ctx bo and etc.
v2: move the simple variable to the end
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 16 Jun 2020 07:34:57 +0000 (15:34 +0800)]
drm/amdgpu/mes10.1: implement the suspend/resume routine
Implement the suspend/resume routine of mes.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 4 Jun 2020 10:27:28 +0000 (18:27 +0800)]
drm/amdgpu/mes10.1: add delay after mes engine enable
Add delay after mes engine enable, for it needs more time
to complete engine initialising.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 25 Mar 2020 10:27:19 +0000 (18:27 +0800)]
drm/amdgpu/mes10.1: call general mes initialization
Call general mes initialization/finalization.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Move the status_fence slot allocation from ip specific function
to general mes function.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 27 Mar 2020 06:50:01 +0000 (14:50 +0800)]
drm/amdgpu/mes: initialize/finalize common mes structure v2
Initialize/finalize common mes structure.
v2: add mutex_init for adev->mes.mutex
Cc: Le Ma <le.ma@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 20 Mar 2020 06:09:54 +0000 (14:09 +0800)]
drm/amdgpu: add mes queue id mask v2
Add MES queue id mask.
v2: move queue id mask to amdgpu_mes_ctx.h
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 11 Apr 2022 20:46:13 +0000 (16:46 -0400)]
drm/amdgpu/mes: manage mes doorbell allocation
It is used to manage the doorbell allocation of mes processes and queues.
Driver calls into process doorbell allocation to get the slice doorbell
for the process, then the doorbell for a queue is allocated from the
process doorbell slice.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 14 Apr 2021 12:08:37 +0000 (20:08 +0800)]
drm/amdgpu: enable mes kiq N-1 test on sienna cichlid
Enable kiq support on gfx10.3, enable mes kiq (n-1)
test on sienna cichlid, so that mes kiq can be tested on
sienna cichlid. The patch can be dropped once mes kiq
is functional.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 26 Mar 2020 02:57:43 +0000 (10:57 +0800)]
drm/amdgpu/sdma5: add mes support for sdma ib test
Add MES support for sdma ib test.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 26 Mar 2020 02:56:11 +0000 (10:56 +0800)]
drm/amdgpu/sdma5: add mes support for sdma ring test
Add MES support for sdma ring test.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 26 Mar 2020 02:50:58 +0000 (10:50 +0800)]
drm/amdgpu/sdma5: add mes queue fence handling
From IH ring buffer look up the coresponding kernel queue and process.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 26 Mar 2020 02:53:16 +0000 (10:53 +0800)]
drm/amdgpu/sdma5: associate mes queue id with fence
Associate mes queue id with fence, so that EOP trap handler can look up
which queue issues the fence.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 26 Mar 2020 02:45:38 +0000 (10:45 +0800)]
drm/amdgpu/sdma5: initialize sdma mqd
Initialize sdma mqd according to ring settings.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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