Rob Herring [Fri, 30 Nov 2018 01:52:51 +0000 (19:52 -0600)]
ARM: dts: aspeed: add missing memory unit-address
The base aspeed-g5.dtsi already defines a '/memory@80000000' node, so
'/memory' in the board files create a duplicate node. We're probably
getting lucky that the bootloader fixes up the memory node that the
kernel ends up using. Add the unit-address so it's merged with the base
node.
Found with DT json-schema checks.
Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
There's a bug in dtc in checking for duplicate node names when there's
another section (e.g. "/ { };"). In this case, skeleton.dtsi provides
another section. Upon removal of skeleton.dtsi, the dtb fails to build
due to a duplicate node 'fixedregulator@0'. As both nodes were pretty
much the same 3.3V fixed regulator, it hasn't really mattered. Fix this
by renaming the nodes to something unique. In the process, drop the
unit-address which shouldn't be present wtihout reg property.
Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 30 Nov 2018 23:17:33 +0000 (15:17 -0800)]
Merge tag 'omap-for-v4.21/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Device tree changes for omaps for v4.21 merge window
These changes mostly configure pinctrl for am437x-gp-evm. There is
also non-critical fix for a comment for Clang, and we enable earlycon
for am3517-evm.
* tag 'omap-for-v4.21/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am437x-gp-evm: Add sleep state for beeper pins
ARM: dts: am437x-gp-evm: Add pinmux for gpio0 wake
ARM: dts: am437x-gp-evm: Add uart0 pinctrl default and sleep states
ARM: dts: am437x-gp-evm: Add pinctrl for debugss pins
ARM: dts: am437x-gp-evm: Add pinctrl for unused_pins
ARM: dts: am437x-gp-evm: Add state for ddr3 vtt toggle pin
ARM: dts: am3517-evm: Enable earlycon stdout path
ARM: dts: omap3-gta04: Fix comment block
Olof Johansson [Fri, 30 Nov 2018 23:16:42 +0000 (15:16 -0800)]
Merge tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Modernize the Vexpress PL111 integration
Lubomir Rintel [Wed, 28 Nov 2018 17:53:14 +0000 (18:53 +0100)]
ARM: dts: mmp2: Add SSP controllers
Despite Marvel keeps their base addresses secret there's a good chance
they're actually correct.
SSP1 and SSP3 bases were taken from OLPC 1.75: OpenFirmware and kernel
respectively. SSP2 and SSP4 addresses are from James Cameron who actually
has a copy of the data sheet.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
Lubomir Rintel [Wed, 28 Nov 2018 17:53:11 +0000 (18:53 +0100)]
ARM: dts: mmp2: add more TWSI controllers
I've gotten the base addresses, clocks and interrupts from an rusty and old
out-of-tree driver. I haven't actually checked against the datasheet, since
that one is reserved for the Marvell inner circle.
Tested with an accelerometer on TWSI6 on an OLPC XO 1.75 machine.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
Lubomir Rintel [Wed, 28 Nov 2018 17:53:10 +0000 (18:53 +0100)]
ARM: dts: mmp2: fix TWSI2
Marvell keeps their MMP2 datasheet secret, but there are good clues
that TWSI2 is not on 0xd4025000 on that platform, not does it use
IRQ 58. In fact, the IRQ 58 on MMP2 seems to be a signal processor:
arch/arm/mach-mmp/irqs.h:#define IRQ_MMP2_MSP 58
I'm taking a somewhat educated guess that is probably a copy & paste
error from PXA168 or PXA910 and that the real controller in fact hides
at address 0xd4031000 and uses an interrupt line multiplexed via IRQ 17.
I'm also copying some properties from TWSI1 that were missing or
incorrect.
Tested on a OLPC XO 1.75 machine, where the RTC is on TWSI2.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 30 Nov 2018 23:09:13 +0000 (15:09 -0800)]
Merge tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v5.0
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
* tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
ARM: dts: socfpga: use tabs for indentation
arm: dts: socfpga: remove dma-mask property
arm: dts: socfpga*.dts*: use SPDX-License-Identifier
* M3-W (r8a7796) SoC:
- Describe CMT (Compare Match Timer) devices in DT
- Describe I2C-DVFS device node in DT
* M3-N (r8a77965) SoC:
- Describe CAN, CANFD and LVDS in DT
* R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs:
- Describe CPU topology, capacity and cooling maps in DT
- Add SSIU support to R-Car audio
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs:
- Extend register range of HSUSB device to match documentation
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) based
Salvator-X, Salvator-XS and ULCB boards:
- Switch eMMC bus to 1V8
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) based
Salvator-X and Salvator-XS boards:
- Describe USB3.0 xHCI host and prerepheral devices as companions
* R-Car E3 (r8a77990) SoC:
- Add thermal support
- Add support for interupt controller for external devices (INTC-EX)
- Describe all SCIF devices and SYS-DMA for I2C and MSIOF devices
* R-Car E3 (r8a77990) based Ebisu board:
- Enable SDHI, CAN, CANFD, audio and USB3.0
- Describe serial console pins
* R-Car E3 (r8a77990) based Ebisu and
R-Car D3 (r8a77995) based Draak board:
- Enable USB2.0 peripheral device
* R-Car M3-N (r8a77965), E3 (r8a77990) and V3H (r8a77980) SoCs:
- Connect EtherAVB to IPMMU
* R-Car V3M (r8a77970) and V3H (r8a77980) SoCs:
- Describe TMU (timer unit), PWM timer controller and MSIOF devides in DT
- Add thermal support
* RZ/G2M (r8a774a1) SoC:
- Use clock and power index macros
- Describe VIN, CSI-2 and CAN devices in DT
* tag 'renesas-arm64-dt-for-v4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (40 commits)
arm64: dts: renesas: Add all CPUs in cooling maps
arm64: dts: renesas: r8a77990: add thermal device support
arm64: dts: renesas: r8a77990: Enable I2C DMA
arm64: dts: renesas: r8a7796: Add CMT device nodes
arm64: dts: renesas: r8a7796: add SSIU support for sound
arm64: dts: renesas: r8a77990: Add I2C-DVFS device node
arm64: dts: renesas: r8a77990: ebisu: Add and enable CAN,FD device nodes
arm64: dts: renesas: r8a77965: Add CAN and CANFD controller nodes
arm64: dts: renesas: r8a77990: ebisu: Add and enable PCIe device node
arm64: dts: renesas: Add CPU capacity-dmips-mhz
arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
arm64: dts: renesas: r8a774a1: Replace clock magic numbers
arm64: dts: renesas: r8a774a1: Replace power magic numbers
arm64: dts: renesas: r8a7795: add SSIU support for sound
arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering
arm64: dts: renesas: ebisu: Add and enable SDHI device nodes
arm64: dts: renesas: ebisu: Add serial console pins
arm64: dts: renesas: Switch eMMC bus to 1V8 on Salvator-X and ULCB
arm64: dts: renesas: r8a77990: Add all HSCIF nodes
arm64: dts: renesas: r8a779{7|8}0: add TMU support
...
Olof Johansson [Fri, 30 Nov 2018 23:04:01 +0000 (15:04 -0800)]
Merge tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New dts for Gru-Scarlet (tablet device), default backlight brightness
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.
* tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add all CPUs in cooling maps
arm64: dts: rockchip: add Gru Scarlet devicetrees
arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator
arm64: dts: rockchip: Use default brightness table for rk3399-gru
arm64: dts: rockchip: add chosen node on rk3399-sapphire
arm64: dts: rockchip: enable HS200 for eMMC on rock64
arm64: dts: rockchip: add fan on rk3399-sapphire board
arm64: dts: rockchip: add rk3399 SPI DMAs
Olof Johansson [Fri, 30 Nov 2018 19:45:47 +0000 (11:45 -0800)]
Merge tag 'vexpress-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
ARMv7 Vexpress updates for v4.20
Single patch to use updated coresight graph bindings thereby removing
loads of dtc warnings
* tag 'vexpress-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress/TC2: Update entries to match latest coresight bindings
The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
clock paths frequencies.
This patch adds the node in the top-level meson-gx dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Viresh Kumar [Fri, 16 Nov 2018 10:04:24 +0000 (15:34 +0530)]
arm64: dts: amlogic: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
He Yangxuan [Sat, 10 Nov 2018 03:39:02 +0000 (11:39 +0800)]
arm64: dts: meson-gxl: add support for phicomm n1
This patch adds support for the Phicomm N1. This device based on P230 reference design.
And this box doesn't have cvbs, so disable related section in device tree.
Signed-off-by: He Yangxuan <yangxuan8282@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Jerome Brunet [Fri, 9 Nov 2018 14:04:44 +0000 (15:04 +0100)]
arm64: dts: meson: consistently disable pin bias
On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.
As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.
The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.
There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Jerome Brunet [Fri, 9 Nov 2018 14:04:43 +0000 (15:04 +0100)]
arm64: dts: meson: disable pad bias for mmc pinmuxes
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Jerome Brunet [Fri, 9 Nov 2018 14:04:42 +0000 (15:04 +0100)]
arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
He Yangxuan [Fri, 9 Nov 2018 12:59:36 +0000 (20:59 +0800)]
arm64: dts: meson: p230: disable advertisement EEE for GbE.
This patch disable EEE advertisement for P230 board (DWMAC + RTL8211F).
If not disable it, the network connection is not stable, will got issues
like throughput drop or broken link.
Signed-off-by: He Yangxuan <yangxuan8282@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: 60795933b709 ("ARM64: dts: meson-gxl-khadas-vim: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: b03c7d6438bb ("ARM64: dts: meson-gxbb-odroidc2: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: 12ada0513d7a ("ARM64: dts: meson-gxbb-nanopi-k2: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: 47884c5c746e ("ARM64: dts: meson-gxl-libretech-cc: Add GPIO lines names") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Jerome Brunet [Thu, 8 Nov 2018 09:51:56 +0000 (10:51 +0100)]
arm64: dts: meson-axg: fix dtc warning about unit address
section 2.2.1 of the DT specs says: " If the node has no reg property,
the @unit-address must be omitted and the node-name alone differentiates
the node from other nodes at the same level in the tree"
Simply replace the '@' with a '-' to fix this warning.
Cc: Fabio Estevam <festevam@gmail.com> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Christian Hewitt [Sat, 13 Oct 2018 12:07:06 +0000 (16:07 +0400)]
arm64: dts: meson-gxl-s905x-khadas-vim enable Bluetooth
This enables Bluetooth support for the following models:
- Khadas VIM basic (AP6212) using firmware BCM43438A1.hcd
- Khadas VIM pro (AP6255) using firmware BCM4345C0.hcd
The AP6212 module used on the VIM basic has an ID clash with another
device. To get Bluetooth working you either need to apply a kernel
patch to drivers/bluetooth/btbcm.c so 0x2209 loads BCM43438A1 or the
BCM43438A1.hcd firmware must be renamed to BCM43430A1.hcd.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Linus Walleij [Thu, 15 Feb 2018 15:12:29 +0000 (16:12 +0100)]
ARM: dts: Modernize the Vexpress PL111 integration
The Versatile Express was submitted with the actual display
bridges unconnected (but defined in the device tree) and
mock "panels" encoded in the device tree node of the PL111
controller.
This doesn't even remotely describe the actual Versatile
Express hardware. Exploit the SiI9022 bridge by connecting
the PL111 pads to it, making it use EDID or fallback values
to drive the monitor.
The also has to use the reserved memory through the
CMA pool rather than by open coding a memory region and
remapping it explicitly in the driver. To achieve this,
a reserved-memory node must exist in the root of the
device tree, so we need to pull that out of the
motherboard .dtsi include files, and push it into each
top-level device tree instead.
We do the same manouver for all the Versatile Express
boards, taking into account the different location of the
video RAM depending on which chip select is used on
each platform.
This plays nicely with the new PL111 DRM driver and
follows the standard ways of assigning bridges and
memory pools for graphics.
Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Cc: Robin Murphy <robin.murphy@arm.com> Tested-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Fri, 16 Nov 2018 20:42:35 +0000 (21:42 +0100)]
ARM: dts: meson: add the clock inputs for the Meson timer
The Meson Timer IP block has two clock inputs:
- clk81 for using the system clock as timebase
- xtal for a timebase with 1us, 10us, 100us and 1ms resolution
The clocksource driver does not use these yet, but it's still a good
idea to add them as this describes how the hardware actually works
internally.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Fri, 16 Nov 2018 20:42:34 +0000 (21:42 +0100)]
ARM: dts: meson: add the TIMER B/C/D interrupts
The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events.
For each of these a separate interrupt exists.
Pass these interrupts to allow using the timers other than TIMER A.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Jerome Brunet [Fri, 9 Nov 2018 14:04:45 +0000 (15:04 +0100)]
ARM: dts: meson: consistently disable pin bias
On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.
As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.
The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.
There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Dinh Nguyen [Thu, 18 Oct 2018 18:57:01 +0000 (13:57 -0500)]
arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
SoCFPGA 32-bit platform.
The Stratix10 platform does not need any of the timers that in reset to
boot, thus we don't need to early reset driver. Therefore, use the
"altr,stratix10-rst-mgr" binding for the reset-simple platform driver on
the Stratix10 platform.
Also remove the "altr,modrst-offset" property because the driver no
longer needs it.
Phil Edworthy [Wed, 21 Nov 2018 10:08:44 +0000 (10:08 +0000)]
ARM: dts: r9a06g032: Correct the GIC DT node name
Harmless mistake, but it's incorrect. The DT spec provides recommendations
for the node names:
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model. If appropriate, the
name should be one of the following choices:
...
interrupt-controller"
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Fri, 26 Oct 2018 09:32:26 +0000 (10:32 +0100)]
ARM: dts: r8a77470: Add watchdog support to SoC dtsi
This patch adds watchdog support to the r8a77470 SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[simon: moved node to preserve sort order] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
are enabled in DT but have no device connected to their output. This
result in spurious messages being printed to the kernel log such as
rcar-du feb00000.display: no connector for encoder /soc/lvds@feb90000, skipping
Fix it by disabling the encoders.
Fixes: 15a1ff30d8f9 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings") Fixes: e5c3f4707f39 ("ARM: dts: r8a7791: Convert to new LVDS DT bindings") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Mon, 8 Oct 2018 08:51:51 +0000 (09:51 +0100)]
ARM: dts: r8a77470: Add SDHI1 support
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a.
r8a77470) is compatible with the R-Car Gen3 ones, its OF
compatibility is restricted to the SoC specific compatible
string to avoid confusion, as from a more generic perspective
the RZ/G1C is sharing the most similarities with the R-Car
Gen2 family of SoCs, and there is a combination of R-Car
Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP
on this specific chip.
This patch adds the SoC specific part of SDHI1 support, and
since SDHI1 comes with internal DMA, its DT node looks fairly
different from SDHI0 and SDHI2.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Mon, 8 Oct 2018 08:51:50 +0000 (09:51 +0100)]
ARM: dts: r8a77470: Add SDHI0 support
RZ/G1C comes with two different types of IP for the SDHI
interfaces, SDHI0 and SDHI2 share the same IP type, and
such an IP is also compatible with the one found in R-Car
Gen2. SDHI1 IP on the other hand is compatible with R-Car
Gen3 with internal DMA.
This patch completes the SDHI support of the R-Car Gen2
compatible IPs, including fixing the max-frequency
definition of SDHI2, as it turns out there is a bug in
Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev.
1.00 Oct. 2017).
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Viresh Kumar [Fri, 16 Nov 2018 10:04:31 +0000 (15:34 +0530)]
arm64: dts: renesas: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Kuninori Morimoto [Wed, 21 Nov 2018 01:07:11 +0000 (01:07 +0000)]
arm64: dts: renesas: r8a7796: add SSIU support for sound
rsnd driver supports SSIU now, let's use it.
Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are
no longer needed.
To avoid git merge timing issue / git bisect issue,
this patch doesn't remove it so far, but will be removed in
the future.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds I2C-DVFS device node for the R8A77990 SoC.
v2
* Drop aliases update as in upstream it is not required to configure the
BD9571 PMIC for DDR backup, nor is the use of i2c are aliases desired.
* Do not describe the device as compatible with "renesas,rcar-gen3-iic" or
"renesas,rmobile-iic" fallback compat strings. The absence of automatic
transmission registers leads us to declare the r8a77990 IIC controller as
incompatible.
v2.1
* Reduced register range to reflect documentation
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds CAN0,1 and CANFD device nodes for the r8a77990 SoC
and enables CANFD connected to CN10 on the E3 Ebisu board using the
R8A77990 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Dave Gerlach [Wed, 7 Nov 2018 05:04:19 +0000 (10:34 +0530)]
ARM: dts: am437x-gp-evm: Add pinmux for gpio0 wake
Add pinctrl settings so that gpio0 wake from suspend will be supported
using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954,
spi0_d0, which is an unused pin brought out to a header on the board
that in it's default state also connects to the gpio used for wakeup,
gpio0_3, which affects the state of the pin and prevents a working
wakeup unless we set the mux to a different state.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Dave Gerlach [Wed, 7 Nov 2018 05:04:17 +0000 (10:34 +0530)]
ARM: dts: am437x-gp-evm: Add pinctrl for debugss pins
The pins used by debugss are not configued by default, place pulldowns
on the pins for maximum power savings during sleep.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Dave Gerlach [Wed, 7 Nov 2018 05:04:16 +0000 (10:34 +0530)]
ARM: dts: am437x-gp-evm: Add pinctrl for unused_pins
There are several pins on this EVM that are not in use but they can
still draw power if misconfigured. Create a pinctrl entry for these pins
and configure each one for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Dave Gerlach [Wed, 7 Nov 2018 05:04:15 +0000 (10:34 +0530)]
ARM: dts: am437x-gp-evm: Add state for ddr3 vtt toggle pin
Add pinctrl data for ddr_vtt_toggle pin so that it is configured
for proper state during DeepSleep0. The pin should enter DS0 off mode
and hold the line low so VTT regulator is kept off while suspended.
It is also important for the PULLUP to be set on this pin so that
on removal of isolation, the VTT line is pulled high as a requirement
for bringing the DDR3 out of self-refresh.
This toggling is dependent on the IO isolation controlled by the
wkup_m3. Without placing the IOs into isolation the DS0 states set for
the pin will not be latched into effect during suspend.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Viresh Kumar [Fri, 16 Nov 2018 10:04:32 +0000 (15:34 +0530)]
arm64: dts: rockchip: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Viresh Kumar [Fri, 16 Nov 2018 10:01:13 +0000 (15:31 +0530)]
ARM: dts: rockchip: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Martin Blumenstingl [Sun, 28 Oct 2018 14:03:43 +0000 (15:03 +0100)]
ARM: dts: meson8b: mxq: add the /chosen/stdout-path property
Support for this board is currently very limited. To debug any potential
issues on this board the "earlycon" kernel parameter can be used (without
any arguments). However, this requires the board to define a
/chosen/stdout-path property in it's .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sun, 28 Oct 2018 14:03:42 +0000 (15:03 +0100)]
ARM: dts: meson8: minix-neo-x8: add the /chosen/stdout-path property
Support for this board is currently very limited. To debug any potential
issues on this board the "earlycon" kernel parameter can be used (without
any arguments). However, this requires the board to define a
/chosen/stdout-path property in it's .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sun, 28 Oct 2018 14:03:41 +0000 (15:03 +0100)]
ARM: dts: meson6: atv1200: add the /chosen/stdout-path property
Support for Meson6 SoCs is currently very limited. It's often unclear
why such a device does not boot. To debug this the "earlycon" kernel
parameter can be used (without any arguments). However, this requires
the board to define a /chosen/stdout-path property in it's .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
John Keeping [Tue, 13 Nov 2018 15:24:13 +0000 (15:24 +0000)]
ARM: dts: rockchip: Fix rk3288-rock2 vcc_flash name
There is no functional change from this, but it is confusing to find two
copies of vcc_sys and no vcc_flash when looking in
/sys/class/regulator/*/name.
Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Martin Blumenstingl [Sun, 28 Oct 2018 12:35:14 +0000 (13:35 +0100)]
dt-bindings: timer: meson6_timer: document the clock inputs
The Meson Timer IP has two clock inputs:
- pclk which is used as "system clock" timebase of Timer E
- xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer
A, B, C, D and E
The IP block has four internal dividers (XTAL is running at 24MHz):
- "xtal div 24" for 1us resolution
- "xtal div 240" for 10us resolution
- "xtal div 2400" for 100us resolution
- "xtal div 24000" for 1ms resolution
Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sun, 28 Oct 2018 12:35:13 +0000 (13:35 +0100)]
dt-bindings: timer: meson6_timer: document all interrupts
The meson6_timer IP block supports four timers - each of them has it's
own interrupt line. Update the documentation to reflect that all four
interrupts should be passed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
projects / users / jedix / linux-maple.git / log