Li Yang [Wed, 14 Sep 2022 21:46:55 +0000 (16:46 -0500)]
arm64: dts: ls1043a: use pcie aer/pme interrupts
After the binding has been updated to include more specific interrupt
definition, update the dts to use the more specific interrupt names.
Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arm64: dts: ls208x: remove NXP Erratum A008585 from LS2088A.
NXP Erratum A008585 affects A57 core cluster used in LS2085 rev1.
However this problem has been fixed in A72 core cluster used in LS2088.
Therefore remove the erratum from LS2088A. Keeping it only in LS2085.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Sandeep Malik <sandeep.malik@nxp.com> Acked-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Biwen Li [Wed, 14 Sep 2022 21:15:37 +0000 (16:15 -0500)]
arm64: dts: ls208xa-rdb: fix errata E-00013
Specify a channel zero in idle state to avoid enterring tri-stated state
for PCA9547.
Some information about E-00013:
- Description: I2C1 and I2C3 buses are missing pull-up.
- Impact: When the PCA954x device is tri-stated, the I2C bus will float.
This makes the I2C bus and its associated downstream devices
inaccessible.
- Hardware fix: Populate resistors R189 and R190 for I2C1 and resistors
R228 and R229 for I2C3.
- Software fix: Remove the tri-state option from the PCA954x
driver(PCA954x always on enable status, specify a channel zero in dts to
fix the errata E-00013).
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arm64: dts: ls2081a-rdb: Add DTS for NXP LS2081ARDB
This patch adds support for NXP LS2081ARDB board which has LS2081A SoC.
LS2081A SoC is 40-pin derivative of LS2088A SoC. From functional
perspective both are same. Hence, LS2088a SoC dtsi file is included
from LS2081ARDB dts.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Tao Yang <b31903@freescale.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shenwei Wang [Wed, 14 Sep 2022 13:58:48 +0000 (08:58 -0500)]
arm64: dts: freescale: add support for i.MX8DXL EVK board
This is to support the EVK (Evaluation Kit Board) for the i.MX8DXL.
The patch has enabled the serial console, SD/EMMC interface, and
the eqos and fec ethernet network.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shenwei Wang [Wed, 14 Sep 2022 13:58:47 +0000 (08:58 -0500)]
arm64: dts: freescale: add i.MX8DXL SoC support
i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.
This patch adds the basic support for i.MX8DXL SoC.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 12 Sep 2022 18:18:19 +0000 (11:18 -0700)]
arm64: dts: imx: Add i.mx8mm Gateworks gw7904 dts support
The GW7904 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- 2x RS232 off-board connectors
- PMIC
- 10x bi-color LED's
- 1x miniPCIe socket with PCIe and USB2.0
- 802.3at Class 4 PoE
- 10-30VDC input via barrel-jack
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Mon, 12 Sep 2022 18:08:36 +0000 (11:08 -0700)]
arm64: dts: imx8mp-venice-gw74xx: add WiFi/BT module support
The GW74xx supports an on-board Laird Connectivity Sterling LWB5+ module
which uses a Cypress CYW4373W chip to provide 1x1 802.11 a/b/g/n/ac +
Bluetooth 5.2.
Add the proper device-tree nodes for it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Tim Harvey [Thu, 8 Sep 2022 15:42:27 +0000 (08:42 -0700)]
arm64: dts: imx8mp-venice-gw74xx: add USB DR support
Add support for USB DR on USB1 interface. Host/Device detection is done
using the usb-role-switch connector with a GPIO as USB1_OTG_ID is not
connected internally.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Vladimir Oltean [Mon, 5 Sep 2022 21:24:58 +0000 (00:24 +0300)]
arm64: dts: ls1028a-rdb: add more ethernet aliases
Commit "arm64: dts: ls1028a: enable swp5 and eno3 for all boards" which
Shawn declared as applied, but for which I can't find a sha1sum, has
enabled a new Ethernet port on the LS1028A-RDB (&enetc_port3), but
U-Boot, which passes a MAC address to Linux' device tree through the
/aliases node, fails to do this for this newly enabled port.
Fix that by adding more ethernet aliases in the only
backwards-compatible way possible: at the end of the current list.
And since it is possible to very easily convert either swp4 or swp5 to
DSA user ports now (which have a MAC address of their own), using these
U-Boot commands:
it would be good if those DSA user ports (swp4, swp5) gained a valid MAC
address from U-Boot as well. In order for that to work properly,
provision two more ethernet aliases for &mscc_felix_port{4,5} as well.
The resulting ordering is slightly unusual, but to me looks more natural
than eno0, eno2, swp0, swp1, swp2, swp3, eno3, swp4, swp5.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Clark Wang [Wed, 31 Aug 2022 14:25:52 +0000 (22:25 +0800)]
arm64: dts: imx8ulp: increase the clock speed of LPSPI
LPSPI transfer max speed is half of the root clock.
Increase the root clock speed to support faster data transmission.
And update the parent clock of all i2c/spi with IMX8ULP_CLK_FROSC_DIV2
which could produce accurate clock for i2c/spi usage.
Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Properties are not documented so lead to the following error:
'#address-cells', '#size-cells', 'interrupts' do not match any of the regexes: 'pinctrl-[0-9]+'
Fix this by removing unneeded properties.
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Sebastian Krzyszkowiak [Fri, 2 Sep 2022 08:42:13 +0000 (10:42 +0200)]
arm64: dts: imx8mq-librem5: Add bq25895 as max17055's power supply
This allows the userspace to notice that there's not enough
current provided to charge the battery, and also fixes issues
with 0% SOC values being considered invalid.
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Describe the RGB notification leds on the Librem 5 phone.
Use the common defines so we're sure to adhere to the common patterns,
use predefined led colors and functions so we're being warned in case
of deprecations.
Martin Kepplinger [Fri, 2 Sep 2022 08:42:11 +0000 (10:42 +0200)]
arm64: dts: imx8mq-librem5: describe the voice coil motor for focus control
Describe the focus motor that will be used for the rear camera - even
though the rear camera sensor driver is not yet in the mainline. The
focus motor is a separate device and can be controlled already.
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Vladimir Oltean [Wed, 31 Aug 2022 16:01:24 +0000 (19:01 +0300)]
arm64: dts: ls1028a: enable swp5 and eno3 for all boards
In order for the LS1028A based boards to benefit from support for
multiple CPU ports, the second DSA master and its associated CPU port
must be enabled in the device trees. This does not change the default
CPU port from the current port 4.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Vladimir Oltean [Wed, 31 Aug 2022 16:01:22 +0000 (19:01 +0300)]
arm64: dts: ls1028a: move DSA CPU port property to the common SoC dtsi
Since the CPU port 4 of the switch is hardwired inside the SoC to go to
the enetc port 2, this shouldn't be something that the board files need
to set (but whether that CPU port is used or not is another discussion).
So move the DSA "ethernet" property to the common dtsi.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 2 Sep 2022 08:58:02 +0000 (16:58 +0800)]
arm64: dts: imx8mp-evk: Add PCIe support
Add PCIe support on i.MX8MP EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 2 Sep 2022 08:58:01 +0000 (16:58 +0800)]
arm64: dts: imx8mp: Add iMX8MP PCIe support
Add i.MX8MP PCIe support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Martyn Welch [Tue, 23 Aug 2022 14:01:22 +0000 (15:01 +0100)]
arm64: dts: imx8mp-msc-sm2s: Add device trees for MSC SM2S-IMX8PLUS SoM and carrier board
Add device trees for one of a number of MSC's (parent company, Avnet)
variants of the SM2S-IMX8PLUS system on module along with the compatible
SM2S-SK-AL-EP1 carrier board. As the name suggests, this family of SoMs use
the NXP i.MX8MP SoC and provide the SMARC module interface.
Frieder Schrempf [Mon, 22 Aug 2022 08:03:51 +0000 (10:03 +0200)]
arm64: dts: imx8mm-kontron: Remove low DDRC operating point
For some reason there is a problem with finding a DDR configuration
that works on all operating points and all LPDDR4 types used on the
SoM. Therefore the bootloader currently doesn't configure the lowest
of the three operating points. Let's also skip this in the kernel
devicetree to make sure it isn't used.
Frieder Schrempf [Mon, 22 Aug 2022 08:03:50 +0000 (10:03 +0200)]
arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltage
It turns out that it is not necessary to declare the VSELECT signal as
GPIO and let the PMIC driver set it to a fixed high level. This switches
the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5
accordingly.
Instead we can do it like other boards already do and simply mux the
VSELECT signal of the USDHC interface to the pin. This makes sure that
the correct voltage is selected by setting the PMIC's SD_VSEL input
to high or low accordingly.
Frieder Schrempf [Mon, 22 Aug 2022 08:03:49 +0000 (10:03 +0200)]
arm64: dts: imx8mm-kontron: Adjust compatibles, file names and model strings
The official naming includes "SL" (SoM-Line) or "BL" (Board-Line).
By updating we make sure, that we can maintain this more easily in
future and make sure that the proper devicetree can be selected for
the hardware.
Shenwei Wang [Wed, 14 Sep 2022 13:58:45 +0000 (08:58 -0500)]
dt-bindings: arm: imx: update fsl.yaml for imx8dxl
i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Martyn Welch [Tue, 23 Aug 2022 14:01:21 +0000 (15:01 +0100)]
dt-bindings: arm: fsl: Add MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier
Add DT compatible strings for a combination of the 14N0600E variant of
the Avnet (MSC branded) SM2S-IMX8PLUS SoM on it's own and in combination
with the SM2-MB-EP1 carrier board.
This updates the bindings in order to simplify the devicetree
structure and to add names for the boards that follow the latest
convention used by Kontron marketing.
It also gets rid of the N6xxx notation in the compatibles and
file names, as they are not really used anymore and often result
in confusion.
This is a breaking change, but the impact shouldn't be too big
and it makes usage and maintenance easier in the future.
Yury Norov [Fri, 12 Aug 2022 05:34:25 +0000 (22:34 -0700)]
radix-tree: replace gfp.h inclusion with gfp_types.h
Radix tree header includes gfp.h for __GFP_BITS_SHIFT only. Now we
have gfp_types.h for this.
Fixes powerpc allmodconfig build:
In file included from include/linux/nodemask.h:97,
from include/linux/mmzone.h:17,
from include/linux/gfp.h:7,
from include/linux/radix-tree.h:12,
from include/linux/idr.h:15,
from include/linux/kernfs.h:12,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/pci.h:35,
from arch/powerpc/kernel/prom_init.c:24:
include/linux/random.h: In function 'add_latent_entropy':
>> include/linux/random.h:25:46: error: 'latent_entropy' undeclared (first use in this function); did you mean 'add_latent_entropy'?
25 | add_device_randomness((const void *)&latent_entropy, sizeof(latent_entropy));
| ^~~~~~~~~~~~~~
| add_latent_entropy
include/linux/random.h:25:46: note: each undeclared identifier is reported only once for each function it appears in
Reported-by: kernel test robot <lkp@intel.com> CC: Andy Shevchenko <andriy.shevchenko@linux.intel.com> CC: Andrew Morton <akpm@linux-foundation.org> CC: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Yury Norov <yury.norov@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 14 Aug 2022 20:03:53 +0000 (13:03 -0700)]
Merge tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Pull vfs lseek fix from Al Viro:
"Fix proc_reg_llseek() breakage. Always had been possible if somebody
left NULL ->proc_lseek, became a practical issue now"
* tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
take care to handle NULL ->proc_lseek()
Linus Torvalds [Sun, 14 Aug 2022 16:22:11 +0000 (09:22 -0700)]
Merge tag 'perf-tools-fixes-for-v6.0-2022-08-13' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull more perf tool updates from Arnaldo Carvalho de Melo:
- 'perf c2c' now supports ARM64, adjust its output to cope with
differences with what is in x86_64. Now go find false sharing on
ARM64 (at least Neoverse) as well!
- Refactor the JSON processing, making the output more compact and thus
reducing the size of the resulting perf binary
- Improvements for 'perf offcpu' profiling, including tracking child
processes
- Update Intel JSON metrics and events files for broadwellde,
broadwellx, cascadelakex, haswellx, icelakex, ivytown, jaketown,
knightslanding, sapphirerapids, skylakex and snowridgex
- Add 'perf stat' JSON output and a 'perf test' entry for it
- Ignore memfd and anonymous mmap events if jitdump present
- Fix an error handling path in 'parse_perf_probe_command()'
- Fixes for the guest Intel PT tracing patchkit in the 1st batch of
this merge window
- Print debuginfod queries if -v option is used, to explain delays in
processing when debuginfo servers are enabled to fetch DSOs with
richer symbol tables
- Improve error message for 'perf record -p not_existing_pid'
- Fix openssl and libbpf feature detection
- Add PMU pai_crypto event description for IBM z16 on 'perf list'
- Fix typos and duplicated words on comments in various places
* tag 'perf-tools-fixes-for-v6.0-2022-08-13' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (81 commits)
perf test: Refactor shell tests allowing subdirs
perf vendor events: Update events for snowridgex
perf vendor events: Update events and metrics for skylakex
perf vendor events: Update metrics for sapphirerapids
perf vendor events: Update events for knightslanding
perf vendor events: Update metrics for jaketown
perf vendor events: Update metrics for ivytown
perf vendor events: Update events and metrics for icelakex
perf vendor events: Update events and metrics for haswellx
perf vendor events: Update events and metrics for cascadelakex
perf vendor events: Update events and metrics for broadwellx
perf vendor events: Update metrics for broadwellde
perf jevents: Fold strings optimization
perf jevents: Compress the pmu_events_table
perf metrics: Copy entire pmu_event in find metric
perf pmu-events: Hide the pmu_events
perf pmu-events: Don't assume pmu_event is an array
perf pmu-events: Move test events/metrics to JSON
perf test: Use full metric resolution
perf pmu-events: Hide pmu_events_map
...
Linus Torvalds [Sun, 14 Aug 2022 15:48:13 +0000 (08:48 -0700)]
Merge tag 'powerpc-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
- Ensure we never emit lwarx with EH=1 on 32-bit, because some 32-bit
CPUs trap on it rather than ignoring it as they should.
- Fix ftrace when building with clang, which was broken by some
refactoring.
- A couple of other minor fixes.
Thanks to Christophe Leroy, Naveen N. Rao, Nick Desaulniers, Ondrej
Mosnacek, Pali Rohár, Russell Currey, and Segher Boessenkool.
* tag 'powerpc-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/kexec: Fix build failure from uninitialised variable
powerpc/ppc-opcode: Fix PPC_RAW_TW()
powerpc64/ftrace: Fix ftrace for clang builds
powerpc: Make eh value more explicit when using lwarx
powerpc: Don't hide eh field of lwarx behind a macro
powerpc: Fix eh field when calling lwarx on PPC32
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