- Drop endpoint redundant masking of global IRQ events (Manivannan
Sadhasivam)
- Clarify unknown global IRQ message and only log it once to avoid a flood
(Manivannan Sadhasivam)
- Add Manivannan Sadhasivam as maintainer of qcom endpoint driver
(Manivannan Sadhasivam)
- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
Sadhasivam)
- Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam)
- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint
controller (Manivannan Sadhasivam)
- Add global SPI interrupt for PCIe link events to DT binding (Manivannan
Sadhasivam)
- Add global RC interrupt handler to handle 'Link up' events and
automatically enumerate hot-added devices (Manivannan Sadhasivam)
- Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR
MMIO space (Prudhvi Yarlagadda)
- Enable controller resources like PHY only after PERST# is deasserted to
partially avoid the problem that the endpoint SoC crashes when accessing
things when Refclk is absent (Manivannan Sadhasivam)
- Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan
Sadhasivam)
- Cache maximum link speed value in dw_pcie.max_link_speed for use by
vendor drivers (Manivannan Sadhasivam)
- Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu
Chinta Venkata)
- Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a
NULL pointer dereference (Manivannan Sadhasivam)
* pci/controller/qcom:
PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
PCI: qcom: Add RX lane margining settings for 16.0 GT/s
PCI: qcom: Add equalization settings for 16.0 GT/s
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
PCI: endpoint: Assign PCI domain number for endpoint controllers
dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property
dt-bindings: PCI: pci-ep: Update Maintainers
PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
PCI: qcom-ep: Drop the redundant masking of global IRQ events
- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the
ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli)
- Extract the cadence link setup from cdns_pcie_host_setup() so link setup
can be done separately during resume (Thomas Richard)
- Use dev_err_probe() to simplify j721e probe (Thomas Richard)
- Add T_PERST_CLK_US definition for the mandatory delay between Refclk
becoming stable and PERST# being deasserted (Thomas Richard)
- Add j721e suspend and resume support (Théo Lebrun)
* pci/controller/j721e:
PCI: j721e: Add suspend and resume support
PCI: j721e: Use T_PERST_CLK_US macro
PCI: Add T_PERST_CLK_US macro
PCI: j721e: Add reset GPIO to struct j721e_pcie
PCI: j721e: Use dev_err_probe() in the probe() function
PCI: cadence: Set cdns_pcie_host_init() global
PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists
dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
- Fix a code restructuring error that caused i.MX8MM and i.MX8MP Endpoints
to fail to establish link (Richard Zhu)
- Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing
outbound alignment requirement (Richard Zhu)
- Call phy_power_off() in the .probe() error path (Frank Li)
- Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also
supported (Frank Li)
- Manage Refclk by using SoC-specific callbacks instead of switch
statements (Frank Li)
- Manage core reset by using SoC-specific callbacks instead of switch
statements (Frank Li)
- Expand comments for erratum ERR010728 workaround (Frank Li)
- Use generic PHY APIs to configure mode, speed, and submode, which is
harmless for devices that implement their own internal PHY management and
don't set the generic imx_pcie->phy (Frank Li)
- Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver Root
Complex support (Richard Zhu)
* pci/controller/imx6:
PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
PCI: imx6: Call common PHY API to set mode, speed, and submode
dt-bindings: PCI: imx6q-pcie: Add i.MX8Q PCIe compatible string
PCI: imx6: Consolidate redundant if-checks
PCI: imx6: Improve comment for workaround ERR010728
PCI: imx6: Simplify switch-case logic by involve core_reset callback
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
PCI: imx6: Rename imx6_* with imx_*
PCI: imx6: Fix missing call to phy_power_off() in error handling
PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
PCI: imx6: Fix establish link failure in EP mode for i.MX8MM and i.MX8MP
* pci/controller/brcmstb:
PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings
PCI: brcmstb: Enable 7712 SoCs
PCI: brcmstb: Change field name from 'type' to 'soc_base'
PCI: brcmstb: Check return value of all reset_control_* calls
PCI: brcmstb: Refactor for chips with many regular inbound windows
PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl
PCI: brcmstb: Remove two unused constants from driver
PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific
PCI: brcmstb: Use swinit reset if available
PCI: brcmstb: Use bridge reset if available
PCI: brcmstb: Use common error handling code in brcm_pcie_probe()
dt-bindings: PCI: brcm,stb-pcie: Add 7712 SoC description
dt-bindings: PCI: brcm,stb-pcie: Use maxItems for reset controllers
dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanup
- Add MSI_FLAG_NO_AFFINITY flag for devices that mux MSIs onto a single IRQ
line and cannot set the affinity of each MSI to a specific CPU core
(Marek Vasut)
- Use MSI_FLAG_NO_AFFINITY and remove unnecessary .irq_set_affinity()
implementations in aardvark, altera, brcmstb, dwc, mediatek-gen3,
mediatek, mobiveil, plda, rcar, tegra, vmd, xilinx-nwl, xilinx-xdma, and
xilinx drivers to avoid "IRQ: set affinity failed" warnings (Marek Vasut)
- Initialize leds class earlier (with an unfortunate Makefile ordering
change) so the PCI NPEM driver can use it (Mariusz Tkaczyk)
- Add Native PCIe Enclosure Management (NPEM) support for sysfs control of
NVMe RAID storage indicators (ok/fail/locate/rebuild/etc) (Mariusz
Tkaczyk)
- Add support for the ACPI _DSM PCIe SSD status LED management, which is
functionally similar to NPEM but mediated by platform firmware (Mariusz
Tkaczyk)
* pci/npem:
PCI/NPEM: Add _DSM PCIe SSD status LED management
PCI/NPEM: Add Native PCIe Enclosure Management support
leds: Init leds class earlier
- Clear LBMS bit after a manual link retrain so we don't try to retrain a
link when there's no downstream device anymore (Maciej W. Rozycki)
- Revert to the original link speed after retraining fails instead of
leaving it restricted to 2.5GT/s, so a future device has a chance to use
higher speeds (Maciej W. Rozycki)
- Correct interpretation of pcie_retrain_link() return status and update it
to return 0/errno instead of true/false (Maciej W. Rozycki)
* pci/enumeration:
PCI: Use an error code with PCIe failed link retraining
PCI: Correct error reporting with PCIe failed link retraining
PCI: Revert to the original speed after PCIe failed link retraining
PCI: Clear the LBMS bit after a link retrain
- Export pcim_request_region(), a managed counterpart of
pci_request_region(), for use by drivers (Philipp Stanner)
- Request the PCI BAR used by xboxvideo (Philipp Stanner)
- Export pcim_iomap_region() and deprecate pcim_iomap_regions() (Philipp
Stanner)
- Request and map drm/ast BARs with pcim_iomap_region() (Philipp Stanner)
* pci/devres:
drm/ast: Request PCI BAR with devres
PCI: Deprecate pcim_iomap_regions() in favor of pcim_iomap_region()
drm/vboxvideo: Add PCI region request
PCI: Make pcim_request_region() a public function
- Wait for device readiness after reset by polling Vendor ID and looking
for Configuration RRS instead of polling the Command register and looking
for non-error completions (Bjorn Helgaas)
- Fix an aardvark issue with emulating Configuration RRS for two-byte reads
of Vendor ID; previously it only worked for four-byte reads (Bjorn
Helgaas)
- Rename CRS Completion Status to RRS to match spec usage (Bjorn Helgaas)
* pci/crs:
PCI: Rename CRS Completion Status to RRS
PCI: aardvark: Correct Configuration RRS checking
PCI: Wait for device readiness with Configuration RRS
Johan Hovold [Tue, 23 Jul 2024 15:13:28 +0000 (17:13 +0200)]
dt-bindings: PCI: qcom: Allow 'vddpe-3v3-supply' again
Commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to
dedicated schema") incorrectly removed 'vddpe-3v3-supply' from the
bindings, which results in DT checker warnings like:
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dtb: pcie@600000: Unevaluated properties are not allowed ('vddpe-3v3-supply' was unexpected)
from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
Note that this property has been part of the Qualcomm PCIe bindings since
2018 and would need to be deprecated rather than simply removed if there is
a desire to replace it with 'vpcie3v3' which is used for some non-Qualcomm
controllers.
PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
The pci_bus_release_domain_nr() API is supposed to free the domain
number allocated by pci_bus_find_domain_nr(). Most of the callers of
pci_bus_find_domain_nr(), store the domain number in pci_bus::domain_nr.
As such, the pci_bus_release_domain_nr() implicitly frees the domain
number by dereferencing 'struct pci_bus'. However, one of the callers
of this API, the PCI endpoint subsystem, doesn't have 'struct pci_bus',
so it only passes NULL. Due to this, the API will end up dereferencing
the NULL pointer.
To fix this issue, pass the domain number to this API explicitly. Since
'struct pci_bus' is not used for anything else other than extracting the
domain number, it makes sense to pass the domain number directly.
Fixes: 0328947c5032 ("PCI: endpoint: Assign PCI domain number for endpoint controllers") Closes: https://lore.kernel.org/linux-pci/c0c40ddb-bf64-4b22-9dd1-8dbb18aa2813@stanley.mountain Link: https://lore.kernel.org/linux-pci/20240912053025.25314-1-manivannan.sadhasivam@linaro.org Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Siddharth Vadapalli [Tue, 27 Aug 2024 12:24:22 +0000 (17:54 +0530)]
PCI: dra7xx: Fix error handling when IRQ request fails in probe
Commit d4c7d1a089d6 ("PCI: dwc: dra7xx: Push request_irq()
call to the bottom of probe") moved the IRQ request for
"dra7xx-pcie-main" towards the end of dra7xx_pcie_probe().
However, the error handling does not take into account the
initialization performed by either dra7xx_add_pcie_port() or
dra7xx_add_pcie_ep(), depending on the mode of operation.
Fix the error handling to address this.
Fixes: d4c7d1a089d6 ("PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe") Link: https://lore.kernel.org/linux-pci/20240827122422.985547-3-s-vadapalli@ti.com Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: stable@vger.kernel.org
Siddharth Vadapalli [Tue, 27 Aug 2024 12:24:21 +0000 (17:54 +0530)]
PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
Commit da87d35a6e51 ("PCI: dra7xx: Use threaded IRQ handler for
"dra7xx-pcie-main" IRQ") switched from devm_request_irq() to
devm_request_threaded_irq() for the "dra7xx-pcie-main" interrupt.
Since the primary handler was set to NULL, the "IRQF_ONESHOT" flag
should have also been set. Fix this.
Fixes: da87d35a6e51 ("PCI: dra7xx: Use threaded IRQ handler for "dra7xx-pcie-main" IRQ") Suggested-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/linux-pci/20240827122422.985547-2-s-vadapalli@ti.com Reported-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: stable@vger.kernel.org
PCI: qcom: Add equalization settings for 16.0 GT/s
During high data transmission rates such as 16.0 GT/s, there is an
increased risk of signal loss due to poor channel quality and
interference. This can impact receiver's ability to capture signals
accurately.
Hence, as signal compensation is achieved through appropriate lane
equalization, apply lane equalization settings at both transmitter
and receiver which results in an increase in the PCIe signal strength.
While at it, modify the pcie-tegra194 driver to make use of the
common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h.
Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
[mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
Currently, the dw_pcie::max_link_speed has a valid value only if the
controller driver restricts the maximum link speed in the driver or if
the platform does so in the devicetree using the 'max-link-speed'
property.
But having the maximum supported link speed of the platform would be
helpful for the vendor drivers to configure any link specific settings.
So in the case of non-valid value in dw_pcie::max_link_speed, just cache
the hardware default value from Link Capability register.
While at it, remove the 'max_link_speed' argument to the
dw_pcie_link_set_max_speed() function since the value can be
retrieved within the function.
Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-2-743f5c1fd027@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
The 'link_gen' field is now holding the maximum supported link speed set
either by the controller driver or by DT through 'max-link-speed'
property.
However, the name 'link_gen' sounds like the negotiated link speed of
the PCIe link.
So rename it to 'max_link_speed' to make it clear that it holds the
maximum supported link speed of the controller.
Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-1-743f5c1fd027@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Manivannan Sadhasivam [Fri, 30 Aug 2024 08:23:19 +0000 (13:53 +0530)]
PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
qcom_pcie_enable_resources() is called by qcom_pcie_ep_probe() and it
enables the controller resources like clocks, regulator, PHY. On one of the
new unreleased Qcom SoC, PHY enablement depends on the active refclk. And
on all of the supported Qcom endpoint SoCs, refclk comes from the host
(RC). So calling qcom_pcie_enable_resources() without refclk causes the
NoC (Network On Chip) error in the endpoint SoC and in turn results in a
whole SoC crash and rebooting into EDL (Emergency Download) mode which is
an unrecoverable state.
But qcom_pcie_enable_resources() is already called by
qcom_pcie_perst_deassert() when PERST# is deasserted, and refclk is
available at that time.
Hence, remove the unnecessary call to qcom_pcie_enable_resources() from
qcom_pcie_ep_probe() to prevent the above mentioned crash.
It should be noted that this commit prevents the crash only under normal
working condition (booting endpoint before host), but the crash may also
occur if PERST# assert happens at the wrong time. For avoiding the crash
completely, it is recommended to use SRIS mode which allows the endpoint
SoC to generate its own refclk. The driver is not supporting SRIS mode
currently, but will be added in the future.
Fixes: 869bc5253406 ("PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host") Link: https://lore.kernel.org/linux-pci/20240830082319.51387-1-manivannan.sadhasivam@linaro.org Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Alex Williamson [Thu, 12 Sep 2024 21:53:27 +0000 (15:53 -0600)]
PCI: Mark Creative Labs EMU20k2 INTx masking as broken
Per user reports, the Creative Labs EMU20k2 (Sound Blaster X-Fi
Titanium Series) generates spurious interrupts when used with
vfio-pci unless DisINTx masking support is disabled.
Thus, quirk the device to mark INTx masking as broken.
Closes: https://lore.kernel.org/all/VI1PR10MB8207C507DB5420AB4C7281E0DB9A2@VI1PR10MB8207.EURPRD10.PROD.OUTLOOK.COM Link: https://lore.kernel.org/linux-pci/20240912215331.839220-1-alex.williamson@redhat.com Reported-by: zdravko delineshev <delineshev@outlook.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Richard Zhu [Tue, 13 Aug 2024 07:42:20 +0000 (15:42 +0800)]
dt-bindings: PCI: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint
Add reg-name: "dbi2", "atu" for i.MX8M PCIe Endpoint.
For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the
driver. This method is not good.
In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"),
Frank suggests to fetch the dbi2 and atu from DT directly. This commit is
preparation to do that for i.MX8M PCIe EP.
These changes wouldn't break driver function. When "dbi2" and "atu"
properties are present, i.MX PCIe driver would fetch the according base
addresses from DT directly. If only two reg properties are provided, i.MX
PCIe driver would fall back to the old method.
Richard Zhu [Mon, 29 Jul 2024 20:18:18 +0000 (16:18 -0400)]
PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe Root Complex
(RC) support. While the controller resembles that of i.MX8MP, the PHY
differs significantly. Also, there's a distinction between PCI bus
addresses and CPU addresses.
Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver
need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus
address conversion according to "ranges" property.
Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-11-b68ee5ef2b4d@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: check resource_list_first_type() for NULL] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Bjorn Helgaas [Tue, 27 Aug 2024 23:48:48 +0000 (18:48 -0500)]
PCI: Rename CRS Completion Status to RRS
PCIe r6.0 changed the abbreviation for "Configuration Request Retry Status"
Completion Status from "CRS" to "RRS" and uses the terminology of
"Configuration RRS Software Visibility" instead of "CRS Software
Visibility".
Align the Linux usage with the r6.0 spec language. No functional change
intended.
It's confusing to make this change, but I think "RRS" *is* a better
abbreviation because it was easy to interpret "CRS" as "Completion Retry
Status", which really didn't make any sense.
Bjorn Helgaas [Tue, 27 Aug 2024 23:48:47 +0000 (18:48 -0500)]
PCI: aardvark: Correct Configuration RRS checking
Per PCIe r6.0, sec 2.3.2, when a Root Complex handles a Completion with
Request Retry Status for a Configuration Read Request that includes both
bytes of the Vendor ID field, it must complete the Request to the host by
returning 0001h for the Vendor ID and all 1's for any additional bytes.
Previously we only returned the 0001h Vendor ID value if we got an RRS
completion for reads of exactly 4 bytes. A read of 2 bytes would not
qualify, although the spec says it should.
Check for reads of 2 or more bytes including the Vendor ID.
I don't think this will fix any observable problems because RRS only
applies to the first config reads after reset, and those are all currently
dword (4-byte) reads.
Bjorn Helgaas [Tue, 27 Aug 2024 23:48:46 +0000 (18:48 -0500)]
PCI: Wait for device readiness with Configuration RRS
After a device reset, delays are required before the device can
successfully complete config accesses. PCIe r6.0, sec 6.6, specifies some
delays required before software can perform config accesses. Devices that
require more time after those delays may respond to config accesses with
Configuration Request Retry Status (RRS) completions.
Callers of pci_dev_wait() are responsible for delays until the device can
respond to config accesses. pci_dev_wait() waits any additional time until
the device can successfully complete config accesses.
Reading config space of devices that are not present or not ready typically
returns ~0 (PCI_ERROR_RESPONSE). Previously we polled the Command register
until we got a value other than ~0. This is sometimes a problem because
Root Complex handling of RRS completions may include several retries and
implementation-specific behavior that is invisible to software (see sec
2.3.2), so the exponential backoff in pci_dev_wait() may not work as
intended.
Linux enables Configuration RRS Software Visibility on all Root Ports that
support it. If it is enabled, read the Vendor ID instead of the Command
register. RRS completions cause immediate return of the 0x0001 reserved
Vendor ID value, so the pci_dev_wait() backoff works correctly.
When a read of Vendor ID eventually completes successfully by returning a
non-0x0001 value (the Vendor ID or 0xffff for VFs), the device should be
initialized and ready to respond to config requests.
For conventional PCI devices or devices below Root Ports that don't support
Configuration RRS Software Visibility, poll the Command register as before.
This was developed independently, but is very similar to Stanislav
Spassov's previous work at
https://lore.kernel.org/linux-pci/20200223122057.6504-1-stanspas@amazon.com
Rename pcie_offsets_bmips_7425[] to pcie_offsets_bcm7425[] to match BCM7425
pcie_soc_base enum, bcm7425_cfg, and "brcm,bcm7425-pcie" .compatible
string.
Rename pcie_offset_bcm7278[] to pcie_offsets_bcm7278[] to match other
"pcie_offsets" names.
Rename pcie_offset_bcm7712[] to pcie_offsets_bcm7712[] to match other
"pcie_offsets" names.
Sort pcie_offsets_*[] by SoC name, move them all together, indent values
for easy reading.
Frank Li [Mon, 29 Jul 2024 20:18:17 +0000 (16:18 -0400)]
PCI: imx6: Call common PHY API to set mode, speed, and submode
Invoke the common PHY API to configure mode, speed, and submode. While
these functions are optional in the PHY interface, they are necessary for
certain PHY drivers. Lack of support for these functions in a PHY driver
does not cause harm.
Frank Li [Mon, 29 Jul 2024 20:18:13 +0000 (16:18 -0400)]
PCI: imx6: Simplify switch-case logic by involve core_reset callback
Instead of using the switch case statement to assert/dassert the core
reset handled by this driver itself, let's introduce a new callback
core_reset() and define it for platforms that require it.
Frank Li [Mon, 29 Jul 2024 20:18:12 +0000 (16:18 -0400)]
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
Instead of using the switch case statement to enable/disable the
reference clock handled by this driver itself, let's introduce a new
callback enable_ref_clk() and define it for platforms that require it.
Frank Li [Mon, 29 Jul 2024 20:18:10 +0000 (16:18 -0400)]
PCI: imx6: Fix missing call to phy_power_off() in error handling
Fix missing call to phy_power_off() in the error path of
imx6_pcie_host_init(). Remove unnecessary check for imx6_pcie->phy
as the PHY API already handles NULL pointers.
Fixes: cbcf8722b523 ("phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()") Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-3-b68ee5ef2b4d@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: <stable@vger.kernel.org> # 6.1+
Correct occasional MSI triggering failures in i.MX8MP PCIe EP by applying
the correct hardware outbound alignment requirement.
The i.MX platform has a restriction about outbound address translation. The
pci-epc-mem uses page_size to manage it. Set the correct page_size for i.MX
platform to meet the hardware requirement, which is the same as inbound
address alignment.
Thus, align it with epc_features::align.
Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-2-b68ee5ef2b4d@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Jason Liu <jason.hui.liu@nxp.com> Cc: <stable@vger.kernel.org> # 6.9+
Richard Zhu [Mon, 29 Jul 2024 20:18:08 +0000 (16:18 -0400)]
PCI: imx6: Fix establish link failure in EP mode for i.MX8MM and i.MX8MP
Add IMX6_PCIE_FLAG_HAS_APP_RESET flag to IMX8MM_EP and IMX8MP_EP drvdata.
This flag was overlooked during code restructuring. It is crucial to
release the app-reset from the System Reset Controller before initiating
LTSSM to rectify the issue.
Fixes: 0c9651c21f2a ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET") Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-1-b68ee5ef2b4d@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: <stable@vger.kernel.org> # 6.9+
Maciej W. Rozycki [Fri, 9 Aug 2024 13:25:02 +0000 (14:25 +0100)]
PCI: Use an error code with PCIe failed link retraining
Given how the call place in pcie_wait_for_link_delay() got structured now,
and that pcie_retrain_link() returns a potentially useful error code,
convert pcie_failed_link_retrain() to return an error code rather than a
boolean status, fixing handling at the call site mentioned. Update the
other call site accordingly.
Maciej W. Rozycki [Fri, 9 Aug 2024 13:24:56 +0000 (14:24 +0100)]
PCI: Correct error reporting with PCIe failed link retraining
Only return successful completion status from pcie_failed_link_retrain() if
retraining has actually been done, preventing excessive delays from being
triggered at call sites in a hope that communication will finally be
established with the downstream device where in fact nothing has been done
about the link in question that would justify such a hope.
Maciej W. Rozycki [Fri, 9 Aug 2024 13:24:51 +0000 (14:24 +0100)]
PCI: Revert to the original speed after PCIe failed link retraining
When `pcie_failed_link_retrain' has failed to retrain the link by hand
it leaves the link speed restricted to 2.5GT/s, which will then affect
any device that has been plugged in later on, which may not suffer from
the problem that caused the speed restriction to have been attempted.
Consequently such a downstream device will suffer from an unnecessary
communication throughput limitation and therefore performance loss.
Remove the speed restriction then and revert the Link Control 2 register
to its original state if link retraining with the speed restriction in
place has failed. Retrain the link again afterwards so as to remove any
residual state, waiting on LT rather than DLLLA to avoid an excessive
delay and ignoring the result as this training is supposed to fail
anyway.
Maciej W. Rozycki [Fri, 9 Aug 2024 13:24:46 +0000 (14:24 +0100)]
PCI: Clear the LBMS bit after a link retrain
The LBMS bit, where implemented, is set by hardware either in response
to the completion of retraining caused by writing 1 to the Retrain Link
bit or whenever hardware has changed the link speed or width in attempt
to correct unreliable link operation. It is never cleared by hardware
other than by software writing 1 to the bit position in the Link Status
register and we never do such a write.
We currently have two places, namely apply_bad_link_workaround() and
pcie_failed_link_retrain() in drivers/pci/controller/dwc/pcie-tegra194.c
and drivers/pci/quirks.c respectively where we check the state of the LBMS
bit and neither is interested in the state of the bit resulting from the
completion of retraining, both check for a link fault.
And in particular pcie_failed_link_retrain() causes issues consequently, by
trying to retrain a link where there's no downstream device anymore and the
state of 1 in the LBMS bit has been retained from when there was a device
downstream that has since been removed.
Clear the LBMS bit then at the conclusion of pcie_retrain_link(), so that
we have a single place that controls it and that our code can track link
speed or width changes resulting from unreliable link operation.
Jim Quinlan [Thu, 15 Aug 2024 22:57:23 +0000 (18:57 -0400)]
PCI: brcmstb: Refactor for chips with many regular inbound windows
Provide support for new chips with multiple inbound windows while
keeping the legacy support for the older chips.
In existing chips there are three inbound windows with fixed purposes:
the first was for mapping SoC internal registers, the second was for
memory, and the third was for memory but with the endian swapped.
Typically, only one window was used.
Complicating the inbound window usage was the fact that the PCIe HW
would do a baroque internal mapping of system memory, and concatenate
the regions of multiple memory controllers.
Newer chips such as the 7712 and Cable Modem SoCs take a step forward
and drop the internal mapping while providing for multiple inbound
windows. This works in concert with the dma-ranges property, where each
provided range becomes an inbound window.
The PCIe SSD Status LED Management _DSM defined in PCI Firmware Spec r3.3
sec 4.7 provides a way to manage LEDs via ACPI.
The design is similar to NPEM defined in PCIe Base Specification r6.1 sec
6.28:
- Both standards are indication oriented,
- _DSM supported bits correspond to NPEM capability register bits,
- _DSM control bits correspond to NPEM control register bits.
_DSM does not support enclosure-specific indications or the special NPEM
commands NPEM_ENABLE and NPEM_RESET.
_DSM is implemented as a second backend in NPEM driver. The backend used is
logged with info priority. The same sysfs interface is used for both NPEM
and _DSM.
According to spec, _DSM has higher priority, and availability of _DSM in
not limited to devices with NPEM support.
The Dell implementation of DSM uses acpi ipmi, which may not be available
immediately (in fact it may take up to 10s for this interface to be
available). It can determine if DSM is supported (GET_SUPPORTED_STATES_DSM
is working) but it cannot serve GET_STATE_DSM or SET_STATE_DSM commands in
this time.
From userspace application perspective (primarily configured by systemd
service) it is better to have not working but configured interface rather
than have it available after few seconds.
For that reason, npem->active_indications cache is now loaded lazily, i.e.
any GET or SET request want cache to be updated if it is not done yet.
Link: https://lore.kernel.org/r/20240904104848.23480-4-mariusz.tkaczyk@linux.intel.com Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com> Signed-off-by: Mariusz Tkaczyk <mariusz.tkaczyk@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Stuart Hayes <stuart.w.hayes@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
The Qualcomm SA8775P root ports don't advertise an ACS capability, but they
do provide ACS-like features to disable peer transactions and validate bus
numbers in requests.
Alexandra Diupina [Tue, 3 Sep 2024 11:58:23 +0000 (14:58 +0300)]
PCI: kirin: Fix buffer overflow in kirin_pcie_parse_port()
Within kirin_pcie_parse_port(), the pcie->num_slots is compared to
pcie->gpio_id_reset size (MAX_PCI_SLOTS) which is correct and would lead
to an overflow.
Thus, fix condition to pcie->num_slots + 1 >= MAX_PCI_SLOTS and move
pcie->num_slots increment below the if-statement to avoid out-of-bounds
array access.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: b22dbbb24571 ("PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge") Link: https://lore.kernel.org/linux-pci/20240903115823.30647-1-adiupina@astralinux.ru Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
PCI/NPEM: Add Native PCIe Enclosure Management support
Native PCIe Enclosure Management (NPEM, PCIe r6.1 sec 6.28) allows managing
LEDs in storage enclosures. NPEM is indication oriented and it does not
give direct access to LEDs. Although each indication *could* represent an
individual LED, multiple indications could also be represented as a single,
multi-color LED or a single LED blinking in a specific interval. The
specification leaves that open.
Each enabled indication (capability register bit on) is represented as a
ledclass_dev which can be controlled through sysfs. For every ledclass
device only 2 brightness states are allowed: LED_ON (1) or LED_OFF (0).
This corresponds to the NPEM control register (Indication bit on/off).
Ledclass devices appear in sysfs as child devices (subdirectory) of PCI
device which has an NPEM Extended Capability and indication is enabled in
NPEM capability register. For example, these are LEDs created for pcieport
"10000:02:05.0" on my setup:
They can be also found in "/sys/class/leds" directory. The parent PCIe
device domain/bus/device/function address is used to guarantee uniqueness
across leds subsystem.
To enable/disable a "fail" indication, the "brightness" file can be edited:
PCIe r6.1, sec 7.9.19.2 defines the possible indications.
Multiple indications for same parent PCIe device can conflict and hardware
may update them when processing new request. To avoid issues, driver
refresh all indications by reading back control register.
This driver expects to be the exclusive NPEM extended capability manager.
It waits up to 1 second after imposing new request, it doesn't verify if
controller is busy before write, and it assumes the mutex lock gives
protection from concurrent updates.
If _DSM LED management is available, we assume the platform may be using
NPEM for its own purposes (see PCI Firmware Spec r3.3 sec 4.7), so the
driver does not use NPEM. A future patch will add _DSM support; an info
message notes whether NPEM or _DSM is being used.
NPEM is a PCIe extended capability so it should be registered in
pcie_init_capabilities() but it is not possible due to LED dependency. The
parent pci_device must be added earlier for led_classdev_register() to be
successful. NPEM does not require configuration on kernel side, so it is
safe to register LED devices later.
Link: https://lore.kernel.org/r/20240904104848.23480-3-mariusz.tkaczyk@linux.intel.com Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mariusz Tkaczyk <mariusz.tkaczyk@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Stuart Hayes <stuart.w.hayes@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
NPEM driver will require leds class, there is an init-order conflict.
Make sure that LEDs initialization happens first and add comment.
Link: https://lore.kernel.org/r/20240904104848.23480-2-mariusz.tkaczyk@linux.intel.com Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Mariusz Tkaczyk <mariusz.tkaczyk@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Stuart Hayes <stuart.w.hayes@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Previous commit to this bindings, commit 756485bfbb85 ("dt-bindings:
PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema"), updated the
bindings to specify one interrupt only, as the devicetree at that time
did not describe the hardware fully.
The devicetree for SC7280 now specifies eight interrupts, following the
commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI
interrupts").
Frank Li [Mon, 1 Jul 2024 22:16:12 +0000 (18:16 -0400)]
dt-bindings: PCI: layerscape-pci: Change property 'fsl,pcie-scfg' type
The fsl,pcie-scfg requires an argument when there are more than one PCIe
instances.
Thus, change it to the phandle-array type and use items to describe
what each field means.
This also fixes the following warning:
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: pcie@3400000: fsl,pcie-scfg:0: [22, 0] is too long from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".
Add missing top-level constraints for clock-names and reset-names.
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".
Add missing top-level constraints for clocks and clock-names.
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".
Add missing top-level constraints for clock-names and reset-names.
Théo Lebrun [Wed, 19 Jun 2024 10:15:15 +0000 (12:15 +0200)]
PCI: j721e: Add suspend and resume support
Add suspend and resume support. Only the Root Complex mode is supported.
During the suspend stage PERST# is asserted, then deasserted during the
resume stage.
Link: https://lore.kernel.org/linux-pci/20240102-j7200-pcie-s2r-v7-7-a2f9156da6c3@bootlin.com Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
[kwilczynski: commit log, update references to the PCI SIG specification] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Thomas Richard [Wed, 19 Jun 2024 10:15:13 +0000 (12:15 +0200)]
PCI: Add T_PERST_CLK_US macro
The "Power Sequencing and Reset Signal Timings" table of the PCI
Express Card Electromechanical Specification, Revision 5.1, Section
2.9.2, indicates PERST# should be deasserted after minimum of 100us
once REFCLK is stable (symbol T_PERST-CLK).
Add a macro so that PCIe controller drivers can use it.
Jim Quinlan [Thu, 15 Aug 2024 22:57:22 +0000 (18:57 -0400)]
PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl
Add a "has_phy" field indicating that the internal PHY has SW control
that requires configuration. Some previous chips only required the
firing of the "rescal" reset controller.
This change requires us to give the 7216 SoC its own cfg_data structure.
Jim Quinlan [Thu, 15 Aug 2024 22:57:17 +0000 (18:57 -0400)]
PCI: brcmstb: Use common error handling code in brcm_pcie_probe()
Refactor the error handling in the bottom half of the probe function
for readability.
The invocation of clk_prepare_enable() is moved lower in the function
and this simplifies a couple of return paths. The dev_err_probe() is
also used when it is apt.
Add description for the 7712 SoC, a Broadcom STB sibling chip
of the Raspberry Pi 5.
The 7712 uses three reset controllers: rescal, for PHY reset
calibration; bridge, for the bridge between the PCIe bus and
the memory bus; and swinit, which is a "soft" initialization
of the PCIe HW.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-4-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Jim Quinlan [Thu, 15 Aug 2024 22:57:14 +0000 (18:57 -0400)]
dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanup
Change maintainer: Nicolas has not been active for a while. It also
makes sense for a Broadcom employee to be the maintainer as many of the
details are privy to Broadcom.
Also, alphabetize the compatible strings.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-2-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
PCI: cadence: Drop excess cdns_pcie_rc.dev kerneldoc description
Struct cdns_pcie_rc once had a .dev member, but it was removed by bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library").
Drop the extra kerneldoc for it.
PCI: mediatek: Drop excess mtk_pcie.mem kerneldoc description
Struct mtk_pcie.mem was removed by 8a26f861b815 ("PCI: mediatek: Use
pci_parse_request_of_pci_ranges()"), but the kerneldoc was left. Remove
the extra kerneldoc.
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