Linus Walleij [Mon, 28 Nov 2022 20:23:20 +0000 (21:23 +0100)]
Merge tag 'intel-pinctrl-v6.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-2
* Enable PWM feature on Intel pin control IPs
The following is an automated git shortlog grouped by driver:
intel:
- Enumerate PWM device when community has a capability
pwm:
- lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
- lpss: Allow other drivers to enable PWM LPSS
- lpss: Include headers we are the direct user of
- lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
- Add a stub for devm_pwmchip_add()
Fabien Poussin [Sat, 26 Nov 2022 19:16:36 +0000 (13:16 -0600)]
pinctrl: sunxi: d1: Add CAN bus pinmuxes
The D1 pin controller contains muxes for two CAN buses. While the CAN
bus controllers are only documented for the T113 SoC, the pin controller
is the same across all SoC variants.
I think the problem is simply that the register base is defined
as void * __iomem instead of void __iomem * and this is because
of the way const correctness works with pointer infix order.
Andy Shevchenko [Thu, 17 Nov 2022 11:08:06 +0000 (13:08 +0200)]
pinctrl: intel: Enumerate PWM device when community has a capability
Some of the Communities may have PWM capability. In such cases,
enumerate the PWM device via respective driver. A user is still
responsible for setting correct pin muxing for the line that
needs to output the signal.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Andy Shevchenko [Thu, 17 Nov 2022 11:08:02 +0000 (13:08 +0200)]
pwm: lpss: Include headers we are the direct user of
For the sake of integrity, include headers we are the direct
user of.
Replace the inclusion of device.h by a forward declaration
of struct device plus a (cheaper) of types.h as device.h is
an expensive include (measured in compiler effort).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Andy Shevchenko [Thu, 17 Nov 2022 11:08:01 +0000 (13:08 +0200)]
pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
The MAX_PWMS definition is already being used by the PWM core.
Using the same name in the certain driver confuses people
and potentially can clash with it.
Hence, rename it by adding LPSS prefix.
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Andy Shevchenko [Thu, 17 Nov 2022 11:08:00 +0000 (13:08 +0200)]
pwm: Add a stub for devm_pwmchip_add()
The devm_pwmchip_add() can be called by a module that optionally
instantiates PWM chip. In the case of CONFIG_PWM=n, the compilation
can't be performed. Hence, add a necessary stub.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
ZhangPeng [Tue, 22 Nov 2022 07:58:53 +0000 (07:58 +0000)]
pinctrl: k210: call of_node_put()
Since for_each_available_child_of_node() will increase the refcount of
node, we need to call of_node_put() manually when breaking out of the
iteration.
If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set,
gcc complained about undefined reference:
drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all':
pinctrl-loongson2.c:(.text+0x1c4): undefined reference to
`pinconf_generic_dt_node_to_map'
To fix this error, add depends on OF to
config PINCTRL_LOONGSON2.
Linus Walleij [Fri, 18 Nov 2022 08:20:20 +0000 (09:20 +0100)]
Merge tag 'intel-pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-1
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
Geert Uytterhoeven [Wed, 9 Nov 2022 13:33:04 +0000 (14:33 +0100)]
pinctrl: renesas: gpio: Use dynamic GPIO base if no function GPIOs
Since commit 502df79b860563d7 ("gpiolib: Warn on drivers still using
static gpiobase allocation") in gpio/for-next, one or more warnings are
printed during boot on systems where the pin controller also provides
GPIO functionality:
gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
Fix this for ARM-based SH/R-Mobile SoCs by:
1. Taking into account a non-zero GPIO base in the various GPIO chip
callbacks,
2. Switching to dynamic allocation of the GPIO base when support for
legacy function GPIOs is not enabled.
On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO
controller and the GPIO function controller must not be changed, as all
board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided
by the various <cpu/sh*.h> header files.
Linus Walleij [Thu, 17 Nov 2022 09:11:10 +0000 (10:11 +0100)]
Merge tag 'qcom-pinctrl-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel
Qualcomm pinctrl Devicetree bindings changes for v6.2, part two
Continuation of refactoring and improving Qualcomm pin controller bindings:
1. Narrow compatible combinations in PMIC MPP.
2. Convert several bindings from TXT to DT schema format: QCS404,
IPQ8074, MSM8660, MSM8916, MSM8960 and MSM8976.
Neil Armstrong [Tue, 15 Nov 2022 10:06:47 +0000 (11:06 +0100)]
dt-bindings: pinctrl: convert semtech,sx150xq bindings to dt-schema
This converts the Semtech SX150Xq bindings to dt-schemas, add necessary
bindings documentation to cover all differences between HW variants
and current bindings usage.
Krzysztof Kozlowski [Thu, 10 Nov 2022 08:52:30 +0000 (09:52 +0100)]
dt-bindings: pinctrl: qcom,msm8976: convert to dtschema
Convert Qualcomm MSM8976 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Changes during conversion: update the list of non-mux pins (like sdc1)
to match Linux driver.
Thierry Reding [Fri, 4 Nov 2022 14:23:44 +0000 (15:23 +0100)]
pinctrl: tegra: Separate Tegra194 instances
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux
and GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Krzysztof Kozlowski [Wed, 9 Nov 2022 10:51:38 +0000 (11:51 +0100)]
dt-bindings: pinctrl: qcom,msm8960: convert to dtschema
Convert Qualcomm MSM8960 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Krzysztof Kozlowski [Tue, 8 Nov 2022 14:23:56 +0000 (15:23 +0100)]
dt-bindings: pinctrl: qcom,ipq8074: convert to dtschema
Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Krzysztof Kozlowski [Mon, 7 Nov 2022 18:59:30 +0000 (19:59 +0100)]
dt-bindings: pinctrl: qcom,msm8660: convert to dtschema
Convert Qualcomm MSM8660 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Sam Shih [Sun, 6 Nov 2022 08:01:13 +0000 (09:01 +0100)]
pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC
Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
add SoC specify 'pull_type' attribute for bias configuration.
This patch add pull_type attribute to pinctrl-mt7986.c, and make
bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sam Shih [Sun, 6 Nov 2022 08:01:12 +0000 (09:01 +0100)]
pinctrl: mediatek: extend pinctrl-moore to support new bias functions
Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
and mtk_pinconf_bias_get_combo, and make the functions able to support
almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
This patch enables pinctrl_moore to support these functions.
Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sam Shih [Sun, 6 Nov 2022 08:01:11 +0000 (09:01 +0100)]
pinctrl: mediatek: fix the pinconf register offset of some pins
Correct the bias-pull-up, bias-pull-down and bias-disable register
offset of mt7986 pin-42 to pin-49, in the original driver, the
relative offset value was erroneously decremented by 1.
Fixes: 360de6728064 ("pinctrl: mediatek: add support for MT7986 SoC") Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-5-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sam Shih [Sun, 6 Nov 2022 08:01:10 +0000 (09:01 +0100)]
dt-bindings: pinctrl: mt7986: add generic bias-pull* support
Since the bias-pull-{up,down} attribute already defines in pinctrl driver
of mediatek MT7986 SoC, this patch updates bindings to support mediatek
common bias-pull* function.
Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221106080114.7426-4-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Frank Wunderlich [Sun, 6 Nov 2022 08:01:09 +0000 (09:01 +0100)]
dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC
Fix mmc and uart pins after uart splitting.
Some pinmux pins of the mt7986 pinctrl driver is composed of multiple
pinctrl groups, the original binding only allows one pinctrl group
per dts node, this patch sets "maxItems" for these groups and add new
examples to the binding documentation.
Fixes: 65916a1ca90a ("dt-bindings: pinctrl: update bindings for MT7986 SoC") Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221106080114.7426-3-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jonathan Neuschäfer [Sat, 5 Nov 2022 18:59:05 +0000 (19:59 +0100)]
pinctrl: nuvoton: wpcm450: Fix handling of inverted MFSEL bits
SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0
selects the GPIO function and 1 selects the special function, in these
two fields, 0 selects the special function and 1 selects the GPIO
function.
In preparation for the next patch, which makes the logic around
setting/resetting bits in MFSEL a little more complicated, move that
code to a new function
The document currently states a maximum of 1 interrupt, but the DT
has 2 specified causing a dtbs_check error. Replace the maximum limit
with a minimum and add per-interrupt descriptions to pass the check.
Fixes: 81557a71564a ("dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings") Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221028153505.23741-6-y.oudjana@protonmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Combine MT6797 pin controller document into MT6779 one. reg and
reg-names property constraints are set using conditionals.
A conditional is also used to make interrupt-related properties
required on the MT6779 pin controller only, since the MT6797
controller doesn't support interrupts (or not yet, at least).
drive-strength and slew-rate properties which weren't described
in the MT6779 document before are brought in from the MT6797 one.
Both pin controllers share a common driver core so they should
both support these properties.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221028153505.23741-5-y.oudjana@protonmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Yassine Oudjana [Fri, 28 Oct 2022 15:34:55 +0000 (18:34 +0300)]
dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Make gpio-ranges optional
The pin controller can function without specifying gpio-ranges so remove
it from required properties. This is also done in preparation for adding
other pin controllers which currently don't have the gpio-ranges property
defined where they are used in DTS. This allows dtbs_check to pass on
those device trees.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221028153505.23741-4-y.oudjana@protonmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current description mentions having to put the pin controller
node under a syscon node, but this is not the case in the current
MT6779 device tree. This is not actually needed, so replace the
current description with something more generic that describes
the use of the hardware block.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221028153505.23741-3-y.oudjana@protonmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Shevchenko [Tue, 8 Nov 2022 14:09:31 +0000 (16:09 +0200)]
pinctrl: intel: Add Intel Moorefield pin controller support
This driver adds pinctrl support for Intel Moorefield. The IP block
which is called Family-Level Interface Shim is a separate entity in SoC.
The GPIO driver, which supports this pinctrl interface, will be
submitted separately.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Krzysztof Kozlowski [Fri, 4 Nov 2022 16:11:31 +0000 (12:11 -0400)]
dt-bindings: pinctrl: qcom,qcs404: convert to dtschema
Convert Qualcomm QCS404 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Changes during conversion: add sdc1_rclk pins (used in qcs404-evb.dtsi).
Krzysztof Kozlowski [Mon, 24 Oct 2022 00:23:55 +0000 (20:23 -0400)]
dt-bindings: pinctrl: qcom,msm8916: convert to dtschema
Convert Qualcomm MSM8916 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Shenwei Wang [Thu, 27 Oct 2022 13:08:59 +0000 (08:08 -0500)]
gpio: mxc: enable pad wakeup on i.MX8x platforms
On i.MX8QM/QXP/DXL SoCs, even a GPIO is selected as the wakeup source,
the GPIO block will be powered off when system enters into suspend
state. This can greatly reduce the power consumption of suspend state
because the whole partition can be shutdown. This is called PAD wakeup
feature on i.MX8x platform.
This patch adds the noirq suspend/resume hooks and uses the pad wakeup
feature as the default wakeup method for GPIO modules on
i.MX8QM/QXP/DXL platforms.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20221027130859.1444412-6-shenwei.wang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Balsam CHIHI [Fri, 21 Oct 2022 08:47:07 +0000 (10:47 +0200)]
pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes
On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Add mt8365_set_clr_mode() callback for such SoCs, so that instead of
using the SET/CLR register, use the main R/W register to
read/update/write the modes.
Andy Shevchenko [Thu, 27 Oct 2022 18:41:45 +0000 (21:41 +0300)]
pinctrl: qcom: lpass-lpi: Add missed bitfield.h
Previously the cleanup change dropped the bitfield.h from the
pinctrl-lpass-lpi.h, since it's not used there, but forgot to
re-instantiate it in the C-file, where users are located.
Fix this by adding missed bitfield.h to the C-file.
Fixes: aa9430f8a6de ("pinctrl: qcom: Add missing header(s)") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Andy Shevchenko [Fri, 7 Oct 2022 09:53:44 +0000 (12:53 +0300)]
pinctrl: Clean up headers
There is a few things done:
- include only the headers we are direct user of
- when pointer is in use, provide a forward declaration
- add missing headers
- group generic headers and subsystem headers
- sort each group alphabetically
While at it, fix some awkward indentations.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
projects / linux.git / log