runtime WARN_ONCE() is added to alarm IIO driver authors who make such
a mistake.
When an IIO driver allocates a new IIO trigger, it should register it
before calling the get() operation. In other words, each IIO driver
must abide by IIO trigger alloc()/register()/get() calls order.
iio: adc: qcom-spmi-rradc: introduce round robin adc
The Round Robin ADC is responsible for reading data about the rate of
charge from the USB or DC input ports, it can also read the battery
ID (resistence), skin temperature and the die temperature of the pmic.
It is found on the PMI8998 and PM660 Qualcomm PMICs.
mfd: qcom-spmi-pmic: expose the PMIC revid information to clients
Some PMIC functions such as the RRADC need to be aware of the PMIC
chip revision information to implement errata or otherwise adjust
behaviour, export the PMIC information to enable this.
This is specifically required to enable the RRADC to adjust
coefficients based on which chip fab the PMIC was produced in,
this can vary per unique device and therefore has to be read at
runtime.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220429220904.137297-3-caleb.connolly@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
spmi: add a helper to look up an SPMI device from a device node
The helper function spmi_device_from_of() takes a device node and
returns the SPMI device associated with it.
This is like of_find_device_by_node but for SPMI devices.
Joe Simmons-Talbott [Wed, 1 Jun 2022 18:54:14 +0000 (14:54 -0400)]
iio: Use octal permissions and DEVICE_ATTR_{RO,RW}.
As reported by checkpatch.pl. Where possible use DEVICE_ATTR_RO(),
DEVICE_ATTR_RW(), and __ATTR_RO(). Change function names to be
<var>_show() for read and <var>_store() for write.
Suggested-by: Joe Perches <joe@perches.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Joe Simmons-Talbott <joetalbott@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220601185414.251571-1-joetalbott@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
It feels wrong and actually inconsistent to attach managed resources
to the IIO device object, which is child of the physical device object.
The rest of the ->probe() calls do that against physical device.
Resolve this by reassigning managed resources to the physical device object.
Suggested-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20220603100004.70336-1-andriy.shevchenko@linux.intel.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Paul Cercueil [Mon, 17 Jan 2022 10:25:12 +0000 (10:25 +0000)]
iio: at91-sama5d2: Limit requested watermark value to hwfifo size
Instead of returning an error if the watermark value is too high, which
the core will silently ignore anyway, limit the value to the hardware
FIFO size; a lower-than-requested value is still better than using the
default, which is usually 1.
Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220117102512.31725-2-paul@crapouillou.net Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Paul Cercueil [Mon, 17 Jan 2022 10:25:11 +0000 (10:25 +0000)]
iio: imu: st_lsm6dsx: Limit requested watermark value to hwfifo size
Instead of returning an error if the watermark value is too high, which
the core will silently ignore anyway, limit the value to the hardware
FIFO size; a lower-than-requested value is still better than using the
default, which is usually 1.
Cc: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20220117102512.31725-1-paul@crapouillou.net Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Jonathan Cameron [Sat, 4 Jun 2022 16:12:23 +0000 (17:12 +0100)]
iio: imu: lsm6dsx: Move exported symbols to the IIO_LSM6DSX namespace
Avoid unnecessary pollution of the global symbol namespace by
moving library functions in to a specific namespace and import
that into the drivers that make use of the functions.
Jonathan Cameron [Sat, 4 Jun 2022 16:12:22 +0000 (17:12 +0100)]
iio: imu: lsm6dsx: Use new pm_sleep_ptr() and EXPORT_SIMPLE_DEV_PM_OPS()
These new functions move the burden of removing unused code when
CONFIG_PM_SLEEP is not defined onto the compiler rather than requiring
the use of CONFIG_PM guards and similar.
Jonathan Cameron [Sat, 4 Jun 2022 16:12:21 +0000 (17:12 +0100)]
iio: humidity: hts221: Move symbol exports into IIO_HTS221 namespace
Avoid unnecessary pollution of the global symbol namespace by
moving library functions in to a specific namespace and import
that into the drivers that make use of the functions.
Jonathan Cameron [Sat, 4 Jun 2022 16:12:20 +0000 (17:12 +0100)]
iio: humidity: hts221: Use EXPORT_SIMPLE_DEV_PM_OPS() to allow compiler to remove dead code.
If CONFIG_PM_SLEEP is not defined using EXPORT_SIMPLE_DEV_PM_OPS()
in conjunction with pm_sleep_ptr() allows the compiler to remove
the unused code and data. This removes the need for __maybe_unused
markings etc.
Jonathan Cameron [Sat, 4 Jun 2022 16:12:19 +0000 (17:12 +0100)]
iio:accel:kxsd9: Switch from CONFIG_PM guards to pm_ptr() etc
Letting the compiler remove these functions when the kernel is built
without CONFIG_PM support is simpler and less error prone than the
use of #ifdef based config guards.
Removing instances of this approach from IIO also stops them being
copied into new drivers.
Nuno Sá [Fri, 10 Jun 2022 08:45:30 +0000 (10:45 +0200)]
iio: core: drop of.h from iio.h
There is no reason to include OF as we only need to forward declare
'of_phandle_args'. Previously, some drivers were actually relying on
this for some headers (those were already fixed).
Jonathan Cameron [Sun, 8 May 2022 17:57:12 +0000 (18:57 +0100)]
iio: temp: maxim_thermocouple: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition
Fixes: 1f25ca11d84a ("iio: temperature: add support for Maxim thermocouple chips") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Matt Ranostay <mranostay@gmail.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-93-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:57:11 +0000 (18:57 +0100)]
iio: temp: max31865: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition
Jonathan Cameron [Sun, 8 May 2022 17:57:10 +0000 (18:57 +0100)]
iio: temp: ltc2983: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:57:09 +0000 (18:57 +0100)]
iio: resolver: ad2s90: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is probably not where the issue was first introduced, but
is likely to be far beyond the point where anyone considers
backporting this fix.
Jonathan Cameron [Sun, 8 May 2022 17:57:08 +0000 (18:57 +0100)]
iio: resolver: ad2s1200: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is probably not where the issue was first introduced, but
is likely to be as far as anyone considers backporting this fix.
Jonathan Cameron [Sun, 8 May 2022 17:57:06 +0000 (18:57 +0100)]
iio: proximity: as3935: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 24ddb0e4bba4 ("iio: Add AS3935 lightning sensor support") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Matt Ranostay <mranostay@gmail.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-87-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:57:04 +0000 (18:57 +0100)]
iio: potentiometer: mcp4131: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 22d199a53910 ("iio: potentiometer: add driver for Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-85-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:57:03 +0000 (18:57 +0100)]
iio: potentiometer: mcp41010: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:57:02 +0000 (18:57 +0100)]
iio: potentiometer: max5481: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:57:01 +0000 (18:57 +0100)]
iio: potentiometer: ad5272: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 79e8a32d2aa9 ("iio: ad5272: Add support for Analog Devices digital potentiometers") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Phil Reid <preid@electromag.com.au> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-82-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:57:00 +0000 (18:57 +0100)]
iio: potentiometer: ad5110: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: d03a74bfacce ("iio: potentiometer: Add driver support for AD5110") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Mugilraj Dhavachelvan <dmugil2000@gmail.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-81-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:59 +0000 (18:56 +0100)]
iio: imu: mpu6050: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 6b0cc5dce072 ("iio:imu:inv_mpu6050 Fix dma and ts alignment and data leak issues.") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-80-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:58 +0000 (18:56 +0100)]
iio: imu: inv_icm42600: Fix alignment for DMA safety in buffer code.
Second fix for this driver due to different introducing patches.
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 7f85e42a6c54 ("iio: imu: inv_icm42600: add buffer support in iio devices") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-79-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:57 +0000 (18:56 +0100)]
iio: imu: inv_icm42600: Fix alignment for DMA safety
Partial fix for this driver as a second instance was introduced in
a later patch.
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:56 +0000 (18:56 +0100)]
iio: imu: fxos8700: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 84e5ddd5c46e ("iio: imu: Add support for the FXOS8700 IMU") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Robert Jones <rjones@gateworks.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-77-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:55 +0000 (18:56 +0100)]
iio: gyro: fxas210002c: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Updated the comment to 'may' require.
Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-76-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:54 +0000 (18:56 +0100)]
iio: gyro: adxrs450: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is inaccurate but unlikely anyone will be interested in
backporting beyond that point.
Jonathan Cameron [Sun, 8 May 2022 17:56:53 +0000 (18:56 +0100)]
iio: gyro: adis16130: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:52 +0000 (18:56 +0100)]
iio: gyro: adis16080: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is inaccurate but unlikely anyone will backport this
beyond that point so I haven't chased the history futher than 2013.
Jonathan Cameron [Sun, 8 May 2022 17:56:51 +0000 (18:56 +0100)]
iio: frequency: adrf6780: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 63aaf6d06d87 ("iio: frequency: adrf6780: add support for ADRF6780") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-72-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:50 +0000 (18:56 +0100)]
iio: frequency: admv4420: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:49 +0000 (18:56 +0100)]
iio: frequency: admv1014: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: f4eb9ac7842f ("iio: frequency: admv1014: add support for ADMV1014") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-70-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:48 +0000 (18:56 +0100)]
iio: frequency: admv1013: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: da35a7b526d9 ("iio: frequency: admv1013: add support for ADMV1013") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-69-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:47 +0000 (18:56 +0100)]
iio: frequency: adf4371: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:46 +0000 (18:56 +0100)]
iio: frequency: adf4350: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Updated help text to 'may' require buffers to be in their own cacheline.
Fixes: e31166f0fd48 ("iio: frequency: New driver for Analog Devices ADF4350/ADF4351 Wideband Synthesizers") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-67-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:45 +0000 (18:56 +0100)]
iio: frequency: ad9523: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Updated help text to 'may' require buffers to be in their own cacheline.
Jonathan Cameron [Sun, 8 May 2022 17:56:44 +0000 (18:56 +0100)]
iio: dac: ti-dac7612: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Updated help text to 'may' require buffers to be in their own cacheline.
Fixes: 977724d20584 ("iio:dac:ti-dac7612: Add driver for Texas Instruments DAC7612") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Ricardo Ribalda <ribalda@kernel.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-65-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:43 +0000 (18:56 +0100)]
iio: dac: ti-dac7311: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 7a02ef7907d8 ("iio:dac:ti-dac7311 Add driver for Texas Instrument DAC7311") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Charles-Antoine Couret <charles-antoine.couret@essensium.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-64-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:42 +0000 (18:56 +0100)]
iio: dac: ti-dac5571: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: df38a4a72a3b ("iio: dac: add TI DAC5571 family support") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-63-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:41 +0000 (18:56 +0100)]
iio: dac: ti-dac082s085: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:40 +0000 (18:56 +0100)]
iio: dac: mcp4922: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 1b791fadf3a1 ("iio: dac: mcp4902/mcp4912/mcp4922 dac driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Michael Welling <mwelling@ieee.org> Link: https://lore.kernel.org/r/20220508175712.647246-61-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:39 +0000 (18:56 +0100)]
iio: dac: ltc2688: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:38 +0000 (18:56 +0100)]
iio: dac: ad8801: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:37 +0000 (18:56 +0100)]
iio: dac: ad7303: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:36 +0000 (18:56 +0100)]
iio: dac: ad7293: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 0bb12606c05f ("iio:dac:ad7293: add support for AD7293") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-57-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:35 +0000 (18:56 +0100)]
iio: dac: ad5791: Fix alignment for DMA saftey
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:34 +0000 (18:56 +0100)]
iio: dac: ad5770r: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: cbbb819837f6 ("iio: dac: ad5770r: Add AD5770R support") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Alexandru Tachici <alexandru.tachici@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-55-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:33 +0000 (18:56 +0100)]
iio: dac: ad5766: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:32 +0000 (18:56 +0100)]
iio: dac: ad5764: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:31 +0000 (18:56 +0100)]
iio: dac: ad5761: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:30 +0000 (18:56 +0100)]
iio: dac: ad5755: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:29 +0000 (18:56 +0100)]
iio: dac: ad5686: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:28 +0000 (18:56 +0100)]
iio: dac: ad5592r: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 56ca9db862bf ("iio: dac: Add support for the AD5592R/AD5593R ADCs/DACs") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Paul Cercueil <paul@crapouillou.net> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-49-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:27 +0000 (18:56 +0100)]
iio: dac: ad5504: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 0dbe59c7a788 ("iio:ad5504: Do not store transfer buffers on the stack") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-48-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:26 +0000 (18:56 +0100)]
iio: dac: ad5449: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 8341dc04dfb3 ("iio:dac: Add support for the ad5449") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-47-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:25 +0000 (18:56 +0100)]
iio: dac: ad5421: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 5691b23489db ("staging:iio:dac: Add AD5421 driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-46-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:24 +0000 (18:56 +0100)]
iio: dac: ad5360: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: a3e2940c24d3 ("staging:iio:dac: Add AD5360 driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-45-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:23 +0000 (18:56 +0100)]
iio: dac: ad5064: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 6a17a0768f77 ("iio:dac:ad5064: Add support for the ad5629r and ad5669r") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-44-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:22 +0000 (18:56 +0100)]
iio: common: ssp: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:21 +0000 (18:56 +0100)]
iio: amplifiers: ad8366: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: e71d42e03c60 ("iio: amplifiers: New driver for AD8366 Dual-Digital Variable Gain Amplifier") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-42-jic23@kernel.org
Jonathan Cameron [Sun, 8 May 2022 17:56:20 +0000 (18:56 +0100)]
iio: addac: ad74413r: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:19 +0000 (18:56 +0100)]
iio: adc: ti-tlc4541: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:18 +0000 (18:56 +0100)]
iio: adc: ti-ads8688: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:17 +0000 (18:56 +0100)]
iio: adc: ti-ads8344: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Jonathan Cameron [Sun, 8 May 2022 17:56:16 +0000 (18:56 +0100)]
iio: adc: ti-ads7950: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 902c4b2446d4 ("iio: adc: New driver for TI ADS7950 chips") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: David Lechner <david@lechnology.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-37-jic23@kernel.org