Stephen Boyd [Tue, 25 Apr 2023 18:50:08 +0000 (11:50 -0700)]
Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Converted most Mediatek clock drivers to struct platform_driver
- MediaTek clock drivers can be built as modules
- Mediatek MT8188 SoC clk drivers
- Clock driver for Sunplus SP7021 SoC
- Reimplement Loongson-1 clk driver with DT support
- Clk driver support for Loongson-2 SoCs
- Migrate socfpga clk driver to of_clk_add_hw_provider()
* clk-mediatek: (84 commits)
clk: mediatek: fhctl: Mark local variables static
clk: mediatek: Use right match table, include mod_devicetable
clk: mediatek: Add MT8188 adsp clock support
clk: mediatek: Add MT8188 imp i2c wrapper clock support
clk: mediatek: Add MT8188 wpesys clock support
clk: mediatek: Add MT8188 vppsys1 clock support
clk: mediatek: Add MT8188 vppsys0 clock support
clk: mediatek: Add MT8188 vencsys clock support
clk: mediatek: Add MT8188 vdosys1 clock support
clk: mediatek: Add MT8188 vdosys0 clock support
clk: mediatek: Add MT8188 vdecsys clock support
clk: mediatek: Add MT8188 mfgcfg clock support
clk: mediatek: Add MT8188 ipesys clock support
clk: mediatek: Add MT8188 imgsys clock support
clk: mediatek: Add MT8188 ccusys clock support
clk: mediatek: Add MT8188 camsys clock support
clk: mediatek: Add MT8188 infrastructure clock support
clk: mediatek: Add MT8188 peripheral clock support
clk: mediatek: Add MT8188 topckgen clock support
clk: mediatek: Add MT8188 apmixedsys clock support
...
* clk-loongson:
clk: clk-loongson2: add clock controller driver support
dt-bindings: clock: add loongson-2 boot clock index
MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
MIPS: loongson32: Update the clock initialization
clk: loongson1: Re-implement the clock driver
clk: loongson1: Remove the outdated driver
dt-bindings: clock: Add Loongson-1 clock
* clk-socfpga:
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: microchip: fix potential UAF in auxdev release callback
Similar to commit 1c11289b34ab ("peci: cpu: Fix use-after-free in
adev_release()"), the auxiliary device is not torn down in the correct
order. If auxiliary_device_add() fails, the release callback will be
called twice, resulting in a UAF. Due to timing, the auxdev code in this
driver "took inspiration" from the aforementioned commit, and thus its
bugs too!
Moving auxiliary_device_uninit() to the unregister callback instead
avoids the issue.
Tom Rix [Thu, 6 Apr 2023 01:09:35 +0000 (21:09 -0400)]
clk: mediatek: fhctl: Mark local variables static
smatch reports
drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol
'fhctl_offset_v1' was not declared. Should it be static?
drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol
'fhctl_offset_v2' was not declared. Should it be static?
These variables are only used in one file so should be static.
clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert the SiFive clk
drivers to use the new symbol.
Stephen Boyd [Tue, 4 Apr 2023 20:45:53 +0000 (13:45 -0700)]
clk: mediatek: Use right match table, include mod_devicetable
This is copy/pasta that breaks modular builds. Fix the match table to
use the right pointer, or the right device table type. And while we're
including the header, fix the order to be linux, dt-bindings, and
finally local.
Garmin.Chang [Fri, 31 Mar 2023 12:36:15 +0000 (20:36 +0800)]
clk: mediatek: Add MT8188 vdosys1 clock support
Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Garmin.Chang [Fri, 31 Mar 2023 12:36:14 +0000 (20:36 +0800)]
clk: mediatek: Add MT8188 vdosys0 clock support
Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Arnd Bergmann [Mon, 27 Feb 2023 08:59:10 +0000 (09:59 +0100)]
clk: tegra20: fix gcc-7 constant overflow warning
Older gcc versions get confused by comparing a u32 value to a negative
constant in a switch()/case block:
drivers/clk/tegra/clk-tegra20.c: In function 'tegra20_clk_measure_input_freq':
drivers/clk/tegra/clk-tegra20.c:581:2: error: case label does not reduce to an integer constant
case OSC_CTRL_OSC_FREQ_12MHZ:
^~~~
drivers/clk/tegra/clk-tegra20.c:593:2: error: case label does not reduce to an integer constant
case OSC_CTRL_OSC_FREQ_26MHZ:
Minghao Chi [Fri, 11 Nov 2022 06:39:35 +0000 (14:39 +0800)]
clock: milbeaut: use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Konrad Dybcio [Tue, 7 Mar 2023 13:29:28 +0000 (14:29 +0100)]
clk: Print an info line before disabling unused clocks
Currently, the regulator framework informs us before calling into
their unused cleanup paths, which eases at least some debugging. The
same could be beneficial for clocks, so that random shutdowns shortly
after most initcalls are done can be less of a guess.
Add a pr_info before disabling unused clocks to do so.
Yinbo Zhu [Thu, 23 Mar 2023 02:52:29 +0000 (10:52 +0800)]
clk: clk-loongson2: add clock controller driver support
This driver provides support for clock controller on Loongson-2 SoC,
the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock,
there are five independent PLLs inside, each of which PLL can
provide up to three sets of frequency dependent clock outputs.
Alexander Stein [Fri, 10 Mar 2023 07:55:34 +0000 (08:55 +0100)]
clk: rs9: Support device specific dif bit calculation
The calculation DIFx is BIT(n) +1 is only true for 9FGV0241. With
additional devices this is getting more complicated.
Support a base bit for the DIF calculation, currently only devices
with consecutive bits are supported, e.g. the 6-channel device needs
additional logic.
Add driver for the Skyworks Si521xx PCIe clock generators. Supported models
are Si52144/Si52146/Si52147, tested model is Si52144. It should be possible
to add Si5213x series as well.
Add binding for Skyworks Si521xx PCIe clock generators. This binding
is designed to support Si52144/Si52146/Si52147 series I2C PCIe clock
generators, tested model is Si52144. It should be possible to add
Si5213x series as well.
Lukas Bulwahn [Thu, 23 Mar 2023 12:14:37 +0000 (13:14 +0100)]
MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
Commit c46496119ed0 ("clk: loongson1: Remove the outdated driver") removes
all files matching the pattern drivers/*/*/*loongson1*, but misses to
adjust the file entry for MIPS/LOONGSON1 ARCHITECTURE in MAINTAINERS.
Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a
broken reference.
Remove this file entry in MIPS/LOONGSON1 ARCHITECTURE.
Stephen Boyd [Mon, 27 Mar 2023 16:39:40 +0000 (09:39 -0700)]
Merge tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel
Selector (ISPCS), and video capture (VIN) clocks on R-Car V4H
- Add video capture (VIN) clocks on R-Car V3H
- Add Cortex-A53 System CPU (Z2) clocks on R-Car V3M and V3H
- Miscellaneous fixes and improvements
Marco Pagani [Fri, 9 Dec 2022 15:29:13 +0000 (16:29 +0100)]
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
The function of_clk_add_provider() has been deprecated, so use its
suggested replacement of_clk_add_hw_provider() instead.
Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(),
check its return value and do the error handling.
The return type of the init function has been changed to void since
the return value was not used, and the indentation of the parameters has
been aligned to match open parenthesis, as suggested by checkpatch.
Marco Pagani [Fri, 9 Dec 2022 15:29:12 +0000 (16:29 +0100)]
clk: socfpga: use of_clk_add_hw_provider and improve error handling
The function of_clk_add_provider() has been deprecated, so use its
suggested replacement of_clk_add_hw_provider() instead.
Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(),
check its return value and do the error handling.
The return type of the init function has been changed to void since
the return value was not used, and the indentation of the parameters has
been aligned to match open parenthesis, as suggested by checkpatch.
The err variable has been renamed rc for consistency.
Marco Pagani [Fri, 9 Dec 2022 15:29:09 +0000 (16:29 +0100)]
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
The function of_clk_add_provider() has been deprecated, so use its
suggested replacement of_clk_add_hw_provider() instead.
Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(),
check its return value and do the error handling.
The indentation of the init function parameters has been aligned
to match open parenthesis, as suggested by checkpatch, and the __init
macro moved before the function name, as specified in init.h.
Marco Pagani [Fri, 9 Dec 2022 15:29:08 +0000 (16:29 +0100)]
clk: socfpga: use of_clk_add_hw_provider and improve error handling
The function of_clk_add_provider() has been deprecated, so use its
suggested replacement of_clk_add_hw_provider() instead.
Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(),
check its return value and do the error handling.
The indentation of the init function parameters has been aligned
to match open parenthesis, as suggested by checkpatch, and the __init
macro moved before the function name, as specified in init.h.
Keguang Zhang [Tue, 21 Mar 2023 11:18:17 +0000 (19:18 +0800)]
MIPS: loongson32: Update the clock initialization
The Loongson-1 clock driver is under re-implementation
to add DT support. As a result, ls1x_clk_init() will be dropped soon.
Therefore, call of_clk_init() for clock initialization instead.
Keguang Zhang [Tue, 21 Mar 2023 11:18:15 +0000 (19:18 +0800)]
clk: loongson1: Remove the outdated driver
Remove the outdated driver due to the following aspects.
- no DT support
- duplicate code across LS1B and LS1C
- does not fit into the current clock framework
Arnd Bergmann [Mon, 20 Mar 2023 09:13:42 +0000 (10:13 +0100)]
clk: mediatek: mt81xx: Ensure fhctl code is available
Just like in commit eddc63094855 ("clk: mediatek: Ensure fhctl code is
available for COMMON_CLK_MT6795"), these three need the shared driver
code, otherwise they run into link errors such as:
aarch64-linux/bin/aarch64-linux-ld: drivers/clk/mediatek/clk-mt8192-apmixedsys.o: in function `clk_mt8192_apmixed_probe':
clk-mt8192-apmixedsys.c:(.text+0x134): undefined reference to `fhctl_parse_dt'
Fixes: 45a5cbe05d1f ("clk: mediatek: mt8173: Add support for frequency hopping through FHCTL") Fixes: 4d586e10c428 ("clk: mediatek: mt8192: Add support for frequency hopping through FHCTL") Fixes: da4a82dc67b0 ("clk: mediatek: mt8195: Add support for frequency hopping through FHCTL") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230320091353.1918439-1-arnd@kernel.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Thu, 16 Mar 2023 23:11:18 +0000 (16:11 -0700)]
clk: mediatek: Ensure fhctl code is available for COMMON_CLK_MT6795
Without this select we get linker errors when linking
clk-mt6795-apmixedsys
arm-linux-gnueabi-ld: drivers/clk/mediatek/clk-mt6795-apmixedsys.o: in function `clk_mt6795_apmixed_remove':
clk-mt6795-apmixedsys.c:(.text+0x34): undefined reference to `mtk_clk_unregister_pllfhs'
arm-linux-gnueabi-ld: drivers/clk/mediatek/clk-mt6795-apmixedsys.o: in function `clk_mt6795_apmixed_probe':
clk-mt6795-apmixedsys.c:(.text+0x98): undefined reference to `fhctl_parse_dt'
arm-linux-gnueabi-ld: clk-mt6795-apmixedsys.c:(.text+0xb8): undefined reference to `mtk_clk_register_pllfhs'
arm-linux-gnueabi-ld: clk-mt6795-apmixedsys.c:(.text+0x1c4): undefined reference to `mtk_clk_unregister_pllfhs'
Fixes: f222a1baec5f ("clk: mediatek: mt6795: Add support for frequency hopping through FHCTL") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230316231118.2579242-1-sboyd@kernel.org
Uwe Kleine-König [Sun, 12 Mar 2023 16:15:05 +0000 (17:15 +0100)]
clk: renesas: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Yang Yingliang [Thu, 29 Dec 2022 09:29:46 +0000 (17:29 +0800)]
clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt()
The device_node pointer returned by of_find_compatible_node() with
refcount incremented, when finish using it, the refcount need be
decreased.
Fixes: d7964de8a8ea ("clk: mediatek: Add new clock driver to handle FHCTL hardware") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20221229092946.4162345-1-yangyingliang@huawei.com
[sboyd@kernel.org: Also unmap on error] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Rob Herring [Fri, 10 Mar 2023 14:47:01 +0000 (08:47 -0600)]
clk: Use of_property_present() for testing DT property presence
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties. As
part of this, convert of_get_property/of_find_property calls to the
recently added of_property_present() helper when we just want to test
for presence of a property and nothing more.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:43 +0000 (15:05 +0100)]
clk: mediatek: mt8135: Convert to simple probe and enable module build
Convert the MT8135 clock drivers to platform_driver using the common
simple probe mechanism; special note goes to the introduction of
dummy clocks with ID 0 (where 0 is the first entry of a clock array)
for each clock controller: this was necessary because of a mistake
in the bindings for all MT8135 clock controllers, where the first
clock has ID 1 (hence, array would start from element 1) instead of
zero.
Now that all of the MT8135 clock drivers (including apmixedsys) can
be compiled as modules, change the COMMON_CLK_MT8135 configuration
option to tristate to enable module build.
While at it, also remove the __initconst annotation from all of the
clock arrays as they are not only used during init anymore, but also
during runtime.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:41 +0000 (15:05 +0100)]
clk: mediatek: mt8135-apmixedsys: Convert to platform_driver and module
Convert apmixedsys clocks to be a platform driver; while at it, also
add necessary error handling to the probe function, add a remove
callback and provide a MODULE_DESCRIPTION().
This driver is now compatible with an eventual module build.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:37 +0000 (15:05 +0100)]
clk: mediatek: Kconfig: Allow module build for core mt8192 clocks
Bootloaders must in a way setup the SoC to boot Linux: this means
that it will be possible to decompress a ramdisk and eventually
insert the core clock driver module from there.
Allow module build for all MT8192 clocks by switching to tristate.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-49-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:36 +0000 (15:05 +0100)]
clk: mediatek: mt8192: Move apmixedsys clock driver to its own file
This is the last man standing in clk-mt8192.c that won't allow us to
use the module_platform_driver() macro, and for *no* good reason.
Move it to clk-mt8192-apmixedsys.c and while at it, also add a
.remove() callback for it.
Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was
just due to them being in the same file and probing different clocks,
and since now there's just one platform_driver struct per file, it
seemed natural to rename the `-simple` variant to just "clk-mt8192".
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:35 +0000 (15:05 +0100)]
clk: mediatek: Split configuration options for MT8186 clock drivers
When building clock drivers for MT8186, some may want to build in only
some of them to, for example, get CPUFreq up faster, and some may want
to leave out some clock drivers entirely as a machine may not need the
Warp Engine or the camera ISP (hence, their clock drivers).
Split the various clock drivers in their own configuration options,
keeping MT8186 configuration options consistent with other MediaTek
SoCs.
While at it, also allow building the remaining clock drivers as modules
by switching COMMON_CLK_MT8186 to tristate.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:31 +0000 (15:05 +0100)]
clk: mediatek: Allow all MT8167 clocks to be built as modules
Almost all MT8167 clocks have been converted to use the common probe
mechanism, moreover, now all of them are platform drivers: allow
building as modules.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:28 +0000 (15:05 +0100)]
clk: mediatek: Split MT8195 clock drivers and allow module build
MT8195 clock drivers were encapsulated in one single (and big) Kconfig
option: there's no reason to do that, as it is totally unnecessary to
build in all or none of them.
Split them out: keep boot-critical clocks as bool and allow choosing
non critical clocks as tristate.
As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS
are not for build-time but rather for runtime, as clocks registered
by those have runtime dependencies on either or both VPP and IMGSYS.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:27 +0000 (15:05 +0100)]
clk: mediatek: mt2712: Change Kconfig options to allow module build
All of the mt2712 drivers have been converted to platform drivers!
Change the Kconfig options for all MT2712 clocks to tristate to allow
building all clock drivers as modules.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:26 +0000 (15:05 +0100)]
clk: mediatek: Add MODULE_LICENSE() where missing
In order to successfully build clock drivers as modules it is required
to declare a module license: add it where missing.
While at it, also change the MODULE_LICENSE text from "GPL v2" to
"GPL" (which means the same) on clk-mt7981-eth.c.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-38-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:25 +0000 (15:05 +0100)]
clk: mediatek: Switch to module_platform_driver() where possible
Lots of clock drivers have got both .probe() and a .remove() callbacks:
switch from builtin_platform_driver() to module_platform_driver() so
that we actually register the .remove() callback.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-37-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:23 +0000 (15:05 +0100)]
clk: mediatek: mt7986-eth: Migrate to common probe mechanism
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also remove __initconst annotations (as these structures
are used also at runtime).
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:22 +0000 (15:05 +0100)]
clk: mediatek: mt7986-infracfg: Migrate to common probe mechanism
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also use module_platform_driver() instead, as this driver
just gained a .remove() callback during the conversion.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:17 +0000 (15:05 +0100)]
clk: mediatek: mt8516: Move apmixedsys clock driver to its own file
In preparation for migrating mt8516 clocks to the common simple
probe mechanism, convert the apmixedsys to be a separated
platform driver and move it to clk-mt8516-apmixedsys.c.
While at it, also fix some indentation issues.
During the conversion, error handling was added to the apmixedsys
probe function.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:16 +0000 (15:05 +0100)]
clk: mediatek: mt7622: Convert to platform driver and simple probe
Convert the MT7622 topckgen and pericfg clock drivers to platform
drivers and use the simple probe mechanism. This also allows to
build these clocks as modules.
Thanks to the conversion, more error handling was added to the clocks
registration.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:15 +0000 (15:05 +0100)]
clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c
The infracfg driver cannot be converted to clk_mtk_simple_probe() as
it registers cpumuxes, which is not supported on the common probing
mechanism: for this reason, move it to its own file.
While at it, also convert it to be a platform driver instead; to do
so, also add a .remove() callback for this driver.
During the conversion, error handling was added to the infracfg
probe function.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:14 +0000 (15:05 +0100)]
clk: mediatek: mt7622-apmixedsys: Add .remove() callback for module build
Add a .remove() callback to the apmixedsys driver to allow full module
build; while at it, also change the usage of builtin_platform_driver()
to module_platform_driver() to actually make use of the new callback.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:13 +0000 (15:05 +0100)]
clk: mediatek: mt7622: Move apmixedsys clock driver to its own file
In preparation for migrating mt7622 clocks to the common simple
probe mechanism, move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it.
During the conversion, error handling was added to the apmixedsys
probe function.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:11 +0000 (15:05 +0100)]
clk: mediatek: Consistently use GATE_MTK() macro
All the various MediaTek clock drivers are, in a way or another,
redefining the GATE_MTK() macro with different names: while some
are doing that by actually using GATE_MTK(), others are copying
it entirely (hence, entirely redefining it).
Change all clock drivers to always and consistently use this macro.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:10 +0000 (15:05 +0100)]
clk: mediatek: mt8183: Convert all remaining clocks to common probe
Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen
clocks on MT8183 to allow full module build for clock drivers.
Differently from other MediaTek clock drivers, it was necessary to
change the name of the `clk13m` clock, as that is already declared
in the SoC's devicetree as a "fixed-factor-clock" (with the same
name) and redeclaring it here would obviously fail to register the
entire clock controller; this clock wasn't dropped only to retain
compatibility with older devicetrees
As a note, the `clk13m` clock is not mentioned in any parent names
array(s) as the correct one (csw_f26m_d2) is already used in place
of that.
Thanks to the conversion, more error handling was added to the clocks
registration.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:08 +0000 (15:05 +0100)]
clk: mediatek: mt8183: Move apmixedsys clock driver to its own file
In preparation for migrating all other mt8183 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it and fix
some indentation issues in the PLLs table.
During the conversion, error handling was added to the apmixedsys
probe function.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:07 +0000 (15:05 +0100)]
clk: mediatek: mt8167: Convert to mtk_clk_simple_{probe,remove}()
Convert topckgen and infracfg clock drivers to use the common
mtk_clk_simple_probe() mechanism and change this from the old
"static" CLK_OF_DECLARE to be a platform driver, allowing it
to eventually be built as a module.
Thanks to the conversion, more error handling was added to the clocks
registration.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:06 +0000 (15:05 +0100)]
clk: mediatek: mt8167: Remove __initconst annotation from arrays
In preparation for converting the MT8167 clock drivers to be proper
platform_driver(s), drop the __initconst annotation from all of the
clock arrays since they will be used not only during init but also
during runtime.
AngeloGioacchino Del Regno [Mon, 6 Mar 2023 14:05:05 +0000 (15:05 +0100)]
clk: mediatek: mt8167: Move apmixedsys as platform_driver in new file
In preparation for migrating all other MT8167 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, also migrate away from the legacy CLK_OF_DECLARE and
convert this clock driver to be a platform_driver instead.
During the conversion, error handling was added to the apmixedsys
probe function.
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