Stephen Boyd [Sat, 21 Sep 2024 21:10:42 +0000 (14:10 -0700)]
Merge branches 'clk-kunit', 'clk-mediatek', 'clk-cleanup' and 'clk-bindings' into clk-next
- KUnit tests for clk registration and fixed rate basic clk type
* clk-kunit:
clk: Add KUnit tests for clks registered with struct clk_parent_data
clk: Add KUnit tests for clk fixed rate basic type
clk: Add test managed clk provider/consumer APIs
platform: Add test managed platform_device/driver APIs
of: Add a KUnit test for overlays and test managed APIs
dt-bindings: vendor-prefixes: Add "test" vendor for KUnit and friends
of: Add test managed wrappers for of_overlay_apply()/of_node_put()
of/platform: Allow overlays to create platform devices from the root node
* clk-cleanup:
clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
clk: ti: dra7-atl: Fix leak of of_nodes
clk:davinci: make use of dev_err_cast_probe()
clk: bcm: bcm53573: fix OF node leak in init
clk: lmk04832: Use devm_clk_get_enabled() helpers
clk: visconti: Switch to use kmemdup_array()
clk: mmp: Switch to use kmemdup_array()
clk: hisilicon: Remove unnecessary local variable
clk: use clk_core_unlink_consumer() helper
clk: Use of_property_present()
clk: at91: Use of_property_count_u32_elems() to get property length
da8xx-cfgchip.c: replace of_node_put with __free improves cleanup
Stephen Boyd [Thu, 5 Sep 2024 18:18:55 +0000 (11:18 -0700)]
Merge tag 'clk-imx-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx2
Pull i.MX clk driver updates from Abel Vesa:
- Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel clocks
on i.MX8Q as parents in ACM provider
- Add i.MX95 NETCMIX support to the block control provider
- Fix parents for ENETx_REF_SEL clocks on i.MX6UL
* tag 'clk-imx-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
clk: imx95: enable the clock of NETCMIX block control
dt-bindings: clock: add RMII clock selection
dt-bindings: clock: add i.MX95 NETCMIX block control
clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL,
the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct
parent and shall be used instead.
Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M
is the correct parent.
Stephen Boyd [Tue, 3 Sep 2024 21:00:29 +0000 (14:00 -0700)]
Merge tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add USB clocks, resets and power domains on RZ/G3S
- Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host
Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on
RZ/V2H
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
clk: renesas: rzv2h: Add support for dynamic switching divider clocks
clk: renesas: r9a08g045: Add clocks, resets and power domains for USB
dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints
Stephen Boyd [Tue, 3 Sep 2024 20:03:10 +0000 (13:03 -0700)]
Merge tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Claudiu Beznea:
- support for the Microchip SAM9X7 SoC as follows:
- updates on the PLL drivers
- a new clock driver was added for SAM9X7
- dt-binding documentation updates (for the new clock driver and for
the slow clock controller that SAM9X7 is using)
- a fix for the Microchip SAMA7G5 clock driver to avoid allocating mode
than necessary memory
* tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
clk: at91: sam9x7: add sam9x7 pmc driver
dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
clk: at91: sama7g5: move mux table macros to header file
clk: at91: sam9x7: add support for HW PLL freq dividers
clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7
Wei Fang [Thu, 29 Aug 2024 01:18:48 +0000 (09:18 +0800)]
clk: imx95: enable the clock of NETCMIX block control
The NETCMIX block control consists of registers for configuration of
peripherals in the NETC domain, so enable the clock of NETCMIX to
support the configuration.
Shengjiu Wang [Wed, 10 Jul 2024 08:41:00 +0000 (16:41 +0800)]
clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
"acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM
driver, but they are the parent clocks for other clocks, in order to
use assigned-clock-parents in device tree, the ".fw_name" can't be used,
need to assign the clk_hw pointer for the imx8qm_mclk_sels[],
imx8qxp_mclk_sels[], imx8dxl_mclk_sels[].
David Lechner [Mon, 26 Aug 2024 15:35:29 +0000 (10:35 -0500)]
clk: ti: dra7-atl: Fix leak of of_nodes
This fix leaking the of_node references in of_dra7_atl_clk_probe().
The docs for of_parse_phandle_with_args() say that the caller must call
of_node_put() on the returned node. This adds the missing of_node_put()
to fix the leak.
Krzysztof Kozlowski [Mon, 26 Aug 2024 06:58:01 +0000 (08:58 +0200)]
clk: bcm: bcm53573: fix OF node leak in init
Driver code is leaking OF node reference from of_get_parent() in
bcm53573_ilp_init(). Usage of of_get_parent() is not needed in the
first place, because the parent node will not be freed while we are
processing given node (triggered by CLK_OF_DECLARE()). Thus fix the
leak by accessing parent directly, instead of of_get_parent().
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks and clock-names.
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks. Drop also redundant assigned-clocks properties, because
core dtschema allows them if clocks are provided.
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks and clock-names.
Huan Yang [Tue, 20 Aug 2024 10:21:19 +0000 (18:21 +0800)]
clk: lmk04832: Use devm_clk_get_enabled() helpers
The devm_clk_get_enabled() helpers:
- call devm_clk_get()
- call clk_prepare_enable() and register what is needed in order to
call clk_disable_unprepare() when needed, as a managed resource.
This simplifies the code and avoids the calls to clk_disable_unprepare().
Peng Fan [Tue, 6 Aug 2024 14:56:01 +0000 (22:56 +0800)]
clk: scmi: add is_prepared hook
Some clocks maybe default enabled by hardware. For clocks that don't
have users, that will be left in hardware default state, because prepare
count and enable count is zero,if there is no is_prepared hook to get
the hardware state. So add is_prepared hook to detect the hardware
state. Then when disabling the unused clocks, they can be simply
turned OFF to save power during kernel boot.
Stephen Boyd [Tue, 27 Aug 2024 17:20:46 +0000 (10:20 -0700)]
Merge tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven
- Add PCIe, PWM, and CAN-FD clocks on R-Car V4M
- Add LCD controller clocks and resets on RZ/G2UL
- Add DMA clocks and resets on RZ/G3S
- Add fractional multiplication PLL support on R-Car Gen4
- Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC
- Add support for the RZ/V2H(P) (R9A09G057) SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (30 commits)
clk: renesas: r8a779h0: Add CANFD clock
clk: renesas: Add RZ/V2H(P) CPG driver
clk: renesas: Add family-specific clock driver for RZ/V2H(P)
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
clk: renesas: r8a779h0: Add PWM clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock
clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
clk: renesas: r8a779a0: Use defines for PLL control registers
clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
clk: renesas: rcar-gen4: Add support for fixed variable PLLs
clk: renesas: rcar-gen4: Add support for variable fractional PLLs
clk: renesas: rcar-gen4: Add support for fractional multiplication
clk: renesas: rcar-gen4: Use defines for common CPG registers
clk: renesas: rcar-gen4: Use FIELD_GET()
clk: renesas: rcar-gen4: Clarify custom PLL clock support
...
clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
The maximum number of PLL components on SAMA7G5 is 3 (one fractional
part and 2 dividers). Allocate the needed amount of memory for
sama7g5_plls 2d array. Previous code used to allocate 7 array entries for
each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which
parses the sama7g5_plls 2d array.
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks and clock-output-names.
Peng Fan [Sun, 4 Aug 2024 12:32:56 +0000 (20:32 +0800)]
clk: clk-conf: support assigned-clock-rates-u64
i.MX95 System Management Control Firmware(SCMI) manages the clock
function, it exposes PLL VCO which could support up to 5GHz rate that
exceeds UINT32_MAX. So add assigned-clock-rates-u64 support
to set rate that exceeds UINT32_MAX.
Rob Herring (Arm) [Wed, 7 Aug 2024 16:58:55 +0000 (10:58 -0600)]
dt-bindings: clock: mediatek: Convert MediaTek clock syscons to schema
Convert the various MediaTek syscon bindings which are a clock provider
into DT schema format. As they are all the same other than compatible
string, combine them into a single schema file.
Rob Herring (Arm) [Wed, 7 Aug 2024 16:58:54 +0000 (10:58 -0600)]
dt-bindings: Move Mediatek clock controllers to "clock" directory
The "arm" binding directory is for architecture specific and top-level
board bindings. Move all the MediaTek bindings implementing clock
providers from "arm/mediatek/" to "clock/" binding directories.
Thorsten Blum [Thu, 1 Aug 2024 10:36:16 +0000 (12:36 +0200)]
clk: hisilicon: Remove unnecessary local variable
The local u64 variable refdiv_val has the same value as the local u32
variable val and can be removed. Remove it and use val directly as the
divisor to also remove the following Coccinelle/coccicheck warning
reported by do_div.cocci:
WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead
Use the preferred div_u64() function instead of the do_div() macro.
clk: at91: sama7g5: move mux table macros to header file
Move the mux table init and fill macro function definitions from the
sama7g5 pmc driver to the pmc.h header file since they will be used
by other SoC's pmc drivers as well like sam9x7.
clk: at91: sam9x7: add support for HW PLL freq dividers
Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system
PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and
4 respectively, both have a hardware divider /2. This has to be taken into
account in the software to obtain the right frequencies. Support for the
same is added in the PLL driver.
fcorepllack -----> HW Div = 2 -+--> fpllack
|
+--> HW Div = 2 ---> fplladiv2ck
In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz
after the hardware divider and the plladiv2 freq is 400 MHz after the
hardware divider (given that the DIVPMC is 0).
clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
SAM9X7 SoC family supports different core output frequencies for
different PLL IDs. To handle the same in the PLL driver, a separate
parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers
are aligned to the PLL driver by adding the core output freq range in
the PLL characteristics configurations.
Use of_property_present() to test for property presence rather than
of_(find|get)_property(). This is part of a larger effort to remove
callers of of_find_property() and similar functions.
of_(find|get)_property() leak the DT struct property and data pointers
which is a problem for dynamically allocated nodes which may be freed.
clk: at91: Use of_property_count_u32_elems() to get property length
Replace of_get_property() with the type specific
of_property_count_u32_elems() to get the property length.
This is part of a larger effort to remove callers of of_get_property()
and similar functions. of_get_property() leaks the DT property data
pointer which is a problem for dynamically allocated nodes which may
be freed.
Document the device tree bindings for the Renesas RZ/V2H(P) SoC
Clock Pulse Generator (CPG).
CPG block handles the below operations:
- Generation and control of clock signals for the IP modules
- Generation and control of resets
- Control over booting
- Low power consumption and power supply domains
Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
core clocks are a subset of the ones which are listed as part of section
4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.
Add binding documentation for Renesas RZ/G2M v3.0 (a.k.a r8a774a3) Clock
Pulse Generator driver. The r8a774a3 cpg is similar to the r8a774a1 cpg
however, it lacks some modules such as the FCPCI.
Signed-off-by: Oliver Rhodes <oliver.rhodes.aj@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20240725100534.5374-4-oliver.rhodes.aj@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
Currently, all PLLs are modelled as fixed divider clocks, based on the
state of the mode pins. However, the boot loader stack may have changed
the actual PLL configuration from the default, leading to incorrect
clock frequencies.
Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4,
and PLL6 as variable fractional PLLs.
clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
Currently, all PLLs but PLL2 are modelled as fixed divider clocks, based
on the state of the mode pins. However, the boot loader stack may have
changed the actual PLL configuration from the default, leading to
incorrect clock frequencies.
Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4,
and PLL6 as variable fractional PLLs.
Reformat nearby lines to retain a consistent layout.
clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
Currently, all PLLs are modelled as fixed divider clocks, based on the
state of the mode pins. However, the boot loader stack may have changed
the actual PLL configuration from the default, leading to incorrect
clock frequencies.
Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, and
PLL6 as variable fractional PLLs. Note that the R-Car Gen4 clock driver
does not support variable 9.24 PLLs yet, so the driver will downgrade
them to fixed fractional PLLs, too.
Reformat nearby lines to retain a consistent layout.
clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
The custom clock driver that models the PLL clocks on R-Car Gen4
supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M.
R-Car S4-8 uses integer and fractional multiplication fields that are
one bit larger resp. smaller, and a slightly different formula.
Extend the existing support to fractional 9.24 PLL, and introduce new
clock types and helper macros to describe these PLLs.
Note that there is no use case for variable fractional 9.24 PLLs yet, as
the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode.
Hence the PLL is always modeled as a fixed PLL, regardless of the
description,
clk: renesas: rcar-gen4: Add support for fixed variable PLLs
The custom clock driver that models PLL clocks on R-Car Gen4 supports
variable clocks, while PLL1 uses a similar control register layout, but
is read-only.
Extend the existing support to fixed clocks and PLL1, and introduce a
new clock type and helper macro to describe a fixed PLL.
clk: renesas: rcar-gen4: Add support for variable fractional PLLs
The custom clock driver that models PLL clocks on R-Car Gen4 supports
PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same
control register layout.
Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new
clock type and helper macro to describe these PLLs.
clk: renesas: rcar-gen4: Add support for fractional multiplication
R-Car Gen4 PLLs support fractional multiplication, which can improve
accuracy when configuring a specific frequency.
Add support for fractional multiplication to the custom clock driver
for PLLs, which is currently used only for PLL2 on R-Car V4H.
While at it, add the missing blank line after the function.
Note that Fractional Multiplication is not enabled by the driver,
but used only if the boot loaded enabled it before.
Improve readability by using the FIELD_GET() helper instead of
open-coding the same operation, and by adding field definitions to get
rid of hardcoded values.
While at it, move register definitions that are only used inside the
rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file.
Add a "CPG_" prefix to SD0CKCR1. Add comments where appropriate.
clk: renesas: rcar-gen4: Clarify custom PLL clock support
The custom clock driver that models the PLL clocks on R-Car Gen4 assumes
the integer and fractional[*] multiplication field sizes as used on
R-Car V4H and V4M, representing a fractional 8.25 number.
Rename the related definitions, functions, and structures to clarify
this, and to prepare for the advent of support for the different field
sizes on R-Car S4-8.
clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock register functions
Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and
`base` parameters in various clock registration functions. These values
are now accessed directly from the `priv` structure.
While at it, drop masking of parent clocks with 0xffff as nothing is ever
stored in the high bits.
clk: renesas: r8a779h0: Initial clock descriptions should be __initconst
r8a779h0_core_clks[], r8a779h0_mod_clks[], and cpg_pll_configs[] are
only used during initialization. Hence make them __initconst, so they
will be freed later.
David Hunter [Sat, 20 Jul 2024 15:24:47 +0000 (11:24 -0400)]
da8xx-cfgchip.c: replace of_node_put with __free improves cleanup
The use of the __free function allows the cleanup to be based on scope
instead of on another function called later. This makes the cleanup
automatic and less susceptible to errors later.
This code was compiled without errors or warnings.
Now that all clock controllers have been migrated to the new
mtk_register_reset_controller_with_dev() function, the one taking
struct device node is now unused: remove it.
Stephen Boyd [Thu, 18 Jul 2024 21:05:05 +0000 (14:05 -0700)]
clk: Add test managed clk provider/consumer APIs
Unit tests are more ergonomic and simpler to understand if they don't
have to hoist a bunch of code into the test harness init and exit
functions. Add some test managed wrappers for the clk APIs so that clk
unit tests can write more code in the actual test and less code in the
harness.
Only add APIs that are used for now. More wrappers can be added in the
future as necessary.
Stephen Boyd [Thu, 18 Jul 2024 21:05:04 +0000 (14:05 -0700)]
platform: Add test managed platform_device/driver APIs
Introduce KUnit resource wrappers around platform_driver_register(),
platform_device_alloc(), and platform_device_add() so that test authors
can register platform drivers/devices from their tests and have the
drivers/devices automatically be unregistered when the test is done.
This makes test setup code simpler when a platform driver or platform
device is needed. Add a few test cases at the same time to make sure the
APIs work as intended.
Cc: Brendan Higgins <brendan.higgins@linux.dev> Reviewed-by: David Gow <davidgow@google.com> Cc: Rae Moar <rmoar@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-6-sboyd@kernel.org
Stephen Boyd [Thu, 18 Jul 2024 21:05:03 +0000 (14:05 -0700)]
of: Add a KUnit test for overlays and test managed APIs
Test the KUnit test managed overlay APIs. Confirm that platform devices
are created and destroyed properly. This provides us confidence that the
test managed APIs work correctly and can be relied upon to provide tests
with fake platform devices and device nodes via overlays compiled into
the kernel image.
Cc: Rob Herring <robh@kernel.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Daniel Latypov <dlatypov@google.com> Cc: Brendan Higgins <brendan.higgins@linux.dev> Reviewed-by: David Gow <davidgow@google.com> Cc: Rae Moar <rmoar@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-5-sboyd@kernel.org
Stephen Boyd [Thu, 18 Jul 2024 21:05:02 +0000 (14:05 -0700)]
dt-bindings: vendor-prefixes: Add "test" vendor for KUnit and friends
Add the vendor prefix "test" to reserve a vendor prefix for bindings
that are purely for testing device tree code. This allows test code to
write bindings that can be checked by the schema validator.
Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: David Gow <davidgow@google.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Conor Dooley <conor+dt@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-4-sboyd@kernel.org
Stephen Boyd [Thu, 18 Jul 2024 21:05:01 +0000 (14:05 -0700)]
of: Add test managed wrappers for of_overlay_apply()/of_node_put()
Add test managed wrappers for of_overlay_apply() that automatically
removes the overlay when the test is finished. This API is intended for
use by KUnit tests that test code which relies on 'struct device_node's
and of_*() APIs.
KUnit tests will call of_overlay_apply_kunit() to load an overlay that's
been built into the kernel image. When the test is complete, the overlay
will be removed.
This has a few benefits:
1) It keeps the tests hermetic because the overlay is removed when the
test is complete. Tests won't even be aware that an overlay was
loaded in another test.
2) The overlay code can live right next to the unit test that loads it.
The overlay and the unit test can be compiled into one kernel module
if desired.
3) We can test different device tree configurations by loading
different overlays. The overlays can be written for a specific test,
and there can be many of them loaded per-test without needing to jam
all possible combinations into one DTB.
4) It also allows KUnit to test device tree dependent code on any
architecture, not just UML. This allows KUnit tests to test
architecture specific device tree code.
There are some potential pitfalls though. Test authors need to be
careful to not overwrite properties in the live tree. The easiest way to
do this is to add and remove nodes with a 'kunit-' prefix, almost
guaranteeing that the same node won't be present in the tree loaded at
boot.
Suggested-by: Rob Herring <robh@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Saravana Kannan <saravanak@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: David Gow <davidgow@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-3-sboyd@kernel.org
Stephen Boyd [Thu, 18 Jul 2024 21:05:00 +0000 (14:05 -0700)]
of/platform: Allow overlays to create platform devices from the root node
We'd like to apply overlays to the root node in KUnit so we can test
platform devices created as children of the root node.
On some architectures (powerpc), the root node isn't marked with
OF_POPULATED_BUS. If an overlay tries to modify the root node on these
platforms it will fail, while on other platforms, such as ARM, it will
succeed. This is because the root node is marked with OF_POPULATED_BUS
by of_platform_default_populate_init() calling
of_platform_default_populate() with NULL as the first argument.
Loosen the requirement here so that platform devices can be created for
nodes created as children of the root node via DT overlays even if the
platform bus wasn't populated for the root node.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Cc: Saravana Kannan <saravanak@google.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[sboyd@kernel.org: Folded in condition fix] Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-2-sboyd@kernel.org
clk: meson: introduce symbol namespace for amlogic clocks
Symbols exported by the Amlogic clock modules are only meant to be used by
Amlogic clock controller drivers. Using a dedicated symbols namespace make
that clear and help clean the global namespace of symbols other modules do
no need.
clk: meson: axg-audio: setup regmap max_register based on the SoC
The register region of axg-audio tends to grow with the addition of
new supported SoC. Mapping slightly more has not been causing problem
so far but it is not viable to continue like this long term.
Setup the max register based on what is necessary on the related SoC.
Merge tag 'kbuild-fixes-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild
Pull Kbuild fixes from Masahiro Yamada:
- Fix RPM package build error caused by an incorrect locale setup
- Mark modules.weakdep as ghost in RPM package
- Fix the odd combination of -S and -c in stack protector scripts,
which is an error with the latest Clang
* tag 'kbuild-fixes-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild:
kbuild: Fix '-S -c' in x86 stack protector scripts
kbuild: rpm-pkg: ghost modules.weakdep file
kbuild: rpm-pkg: Fix C locale setup
minmax: simplify and clarify min_t()/max_t() implementation
This simplifies the min_t() and max_t() macros by no longer making them
work in the context of a C constant expression.
That means that you can no longer use them for static initializers or
for array sizes in type definitions, but there were only a couple of
such uses, and all of them were converted (famous last words) to use
MIN_T/MAX_T instead.
Cc: David Laight <David.Laight@aculab.com> Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Commit 3a7e02c040b1 ("minmax: avoid overly complicated constant
expressions in VM code") added the simpler MIN_T/MAX_T macros in order
to avoid some excessive expansion from the rather complicated regular
min/max macros.
The complexity of those macros stems from two issues:
(a) trying to use them in situations that require a C constant
expression (in static initializers and for array sizes)
(b) the type sanity checking
and MIN_T/MAX_T avoids both of these issues.
Now, in the whole (long) discussion about all this, it was pointed out
that the whole type sanity checking is entirely unnecessary for
min_t/max_t which get a fixed type that the comparison is done in.
But that still leaves min_t/max_t unnecessarily complicated due to
worries about the C constant expression case.
However, it turns out that there really aren't very many cases that use
min_t/max_t for this, and we can just force-convert those.
This does exactly that.
Which in turn will then allow for much simpler implementations of
min_t()/max_t(). All the usual "macros in all upper case will evaluate
the arguments multiple times" rules apply.
We should do all the same things for the regular min/max() vs MIN/MAX()
cases, but that has the added complexity of various drivers defining
their own local versions of MIN/MAX, so that needs another level of
fixes first.
kbuild: Fix '-S -c' in x86 stack protector scripts
After a recent change in clang to stop consuming all instances of '-S'
and '-c' [1], the stack protector scripts break due to the kernel's use
of -Werror=unused-command-line-argument to catch cases where flags are
not being properly consumed by the compiler driver:
$ echo | clang -o - -x c - -S -c -Werror=unused-command-line-argument
clang: error: argument unused during compilation: '-c' [-Werror,-Wunused-command-line-argument]
This results in CONFIG_STACKPROTECTOR getting disabled because
CONFIG_CC_HAS_SANE_STACKPROTECTOR is no longer set.
'-c' and '-S' both instruct the compiler to stop at different stages of
the pipeline ('-S' after compiling, '-c' after assembling), so having
them present together in the same command makes little sense. In this
case, the test wants to stop before assembling because it is looking at
the textual assembly output of the compiler for either '%fs' or '%gs',
so remove '-c' from the list of arguments to resolve the error.
All versions of GCC continue to work after this change, along with
versions of clang that do or do not contain the change mentioned above.
Cc: stable@vger.kernel.org Fixes: 4f7fd4d7a791 ("[PATCH] Add the -fstack-protector option to the CFLAGS") Fixes: 60a5317ff0f4 ("x86: implement x86_32 stack protector") Link: https://github.com/llvm/llvm-project/commit/6461e537815f7fa68cef06842505353cf5600e9c Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
projects / users / hch / misc.git / log