Stephen Boyd [Tue, 20 Oct 2020 18:47:07 +0000 (11:47 -0700)]
Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next
- Support qcom SM8150/SM8250 video and display clks
- Change how qcom's display port clks work
* clk-ingenic:
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks
* clk-at91:
clk: at91: sam9x60: support only two programmable clocks
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name
* clk-kconfig:
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
* clk-imx:
clk: imx8mq: Fix usdhc parents order
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
* clk-qcom:
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: qcom: Add display clock controller driver for SM8150 and SM8250
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: add video clock controller driver for SM8250
clk: qcom: add video clock controller driver for SM8150
dt-bindings: clock: add SM8250 QCOM video clock bindings
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
clk/qcom: fix spelling typo
clk: qcom: gcc-sdm660: Fix wrong parent_map
clk: qcom: dispcc: Update DP clk ops for phy design
clk: qcom: gcc-msm8939: remove defined but not used variables
clk: qcom: ipq8074: make pcie0_rchng_clk_src static
* clk-prima2:
clk: clk-prima2: fix return value check in prima2_clk_init()
* clk-bcm:
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: bcm: rpi: Add register to control pixel bvb clk
Stephen Boyd [Tue, 20 Oct 2020 18:47:02 +0000 (11:47 -0700)]
Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', 'clk-const' and 'clk-mmp2' into clk-next
* clk-semicolon:
clk: meson: use semicolons rather than commas to separate statements
clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements
clk: uniphier: use semicolons rather than commas to separate statements
* clk-axi-clkgen:
clk: axi-clkgen: Set power bits for fractional mode
clk: axi-clkgen: Add support for fractional dividers
* clk-qoriq:
clk: qoriq: modify MAX_PLL_DIV to 32
* clk-baikal:
clk: baikal-t1: Mark Ethernet PLL as critical
Stephen Boyd [Tue, 20 Oct 2020 18:46:47 +0000 (11:46 -0700)]
Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-mediatek' into clk-next
- Small non-critical fixes for TI clk driver
- Support Mediatek MT8167 clks
* clk-simplify:
clk: mediatek: fix platform_no_drv_owner.cocci warnings
clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init
clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init
* clk-ti:
clk: ti: dra7: add missing clkctrl register for SHA2 instance
clk: ti: clockdomain: fix static checker warning
clk: ti: autoidle: add checks against NULL pointer reference
clk: keystone: sci-clk: add 10% slack to set_rate
clk: keystone: sci-clk: cache results of last query rate operation
clk: keystone: sci-clk: fix parsing assigned-clock data during probe
* clk-tegra:
clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()
* clk-rockchip:
clk: rockchip: Initialize hw to error to avoid undefined behavior
clk: rockchip: rk3399: Support module build
clk: rockchip: fix the clk config to support module build
clk: rockchip: Export some clock common APIs for module drivers
clk: rockchip: Export rockchip_register_softrst()
clk: rockchip: Export rockchip_clk_register_ddrclk()
clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk: rockchip: rk3308: drop unused mux_timer_src_p
* clk-mediatek:
clk: mediatek: Add MT8167 clock support
dt-bindings: clock: mediatek: add bindings for MT8167 clocks
clk: mediatek: add UART0 clock support
Stephen Boyd [Tue, 20 Oct 2020 18:46:34 +0000 (11:46 -0700)]
Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner', 'clk-samsung', 'clk-doc' and 'clk-unused' into clk-next
- Remove various unused variables in clk drivers
* clk-renesas:
clk: renesas: rcar-gen3: Update description for RZ/G2
clk: renesas: cpg-mssr: Add support for R-Car V3U
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
clk: renesas: r8a7742: Add clk entry for VSPR
* clk-amlogic:
clk: meson: make shipped controller configurable
clk: meson: g12a: mark fclk_div2 as critical
clk: meson: axg-audio: fix g12a tdmout sclk inverter
clk: meson: axg-audio: separate axg and g12a regmap tables
clk: meson: add sclk-ws driver
* clk-allwinner:
clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
clk: sunxi-ng: add support for the Allwinner A100 CCU
dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
* clk-samsung:
clk: s2mps11: initialize driver via module_platform_driver
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
clk: samsung: Add clk ID definitions for the CPU parent clocks
clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
clk: samsung: Keep top BPLL mux on Exynos542x enabled
Stephen Boyd [Sat, 17 Oct 2020 02:01:37 +0000 (19:01 -0700)]
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
If the GDSC is enabled out of boot but doesn't have the retain ff bit
set we will get confusing results where the registers that are powered
by the GDSC lose their contents on the first power off of the GDSC but
thereafter they retain their contents. This is because gdsc_init() fails
to make sure the RETAIN_FF bit is set when it probes the GDSC the first
time and thus powering off the GDSC causes the register contents to be
reset. We do set the RETAIN_FF bit the next time we power on the GDSC,
see gdsc_enable(), so that subsequent GDSC power off's don't lose
register contents state.
Forcibly set the bit at device probe time so that the kernel's assumed
view of the GDSC is consistent with the state of the hardware. This
fixes a problem where the audio PLL doesn't work on sc7180 when the
bootloader leaves the lpass_core_hm GDSC enabled at boot (e.g. to make a
noise) but critically doesn't set the RETAIN_FF bit.
Cc: Douglas Anderson <dianders@chromium.org> Cc: Taniya Das <tdas@codeaurora.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201017020137.1251319-1-sboyd@kernel.org Reviewed-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
Geert Uytterhoeven [Fri, 7 Aug 2020 09:43:51 +0000 (11:43 +0200)]
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
The HSDK PLL driver is only useful when building for an ARC HSDK
platform.
As ARC selects OF, the dependency on OF can just be replaced by a
dependency on ARC_SOC_HSDK.
Paul Cercueil [Thu, 3 Sep 2020 01:50:48 +0000 (03:50 +0200)]
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().
Paul Cercueil [Thu, 3 Sep 2020 01:50:44 +0000 (03:50 +0200)]
clk: ingenic: Use to_clk_info() macro for all clocks
The to_clk_info() previously had a BUG_ON() to check that it was only
called for PLL clocks. Yet, all the other clocks were doing the exact
same thing the macro does, in-line.
Move the to_clk_info() macro to the top of the file, remove the
hardcoded BUG_ON(), and use it everywhere it makes sense.
Navid Emamdoost [Sun, 9 Aug 2020 23:11:58 +0000 (18:11 -0500)]
clk: bcm2835: add missing release if devm_clk_hw_register fails
In the implementation of bcm2835_register_pll(), the allocated pll is
leaked if devm_clk_hw_register() fails to register hw. Release pll if
devm_clk_hw_register() fails.
Claudiu Beznea [Tue, 25 Aug 2020 06:59:10 +0000 (09:59 +0300)]
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
Main Oscillator Register) that writing any value other than
0x37 on KEY field aborts the write operation. Use the key when
selecting main clock parent.
Claudiu Beznea [Tue, 25 Aug 2020 06:59:09 +0000 (09:59 +0300)]
clk: at91: remove the checking of parent_name
There is no need to check parent_name variable while assigning it to
init.parent_names. parent_name variable is already checked at
the beginning of at91_clk_register_peripheral() function.
Xu Wang [Mon, 21 Sep 2020 03:45:22 +0000 (03:45 +0000)]
clk: clk-prima2: fix return value check in prima2_clk_init()
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
The LCD clock dividers are apparently based on one. No datasheet,
determined empirically, but seems to be confirmed by line 19 of lcd.fth in
OLPC laptop's Open Firmware [1]:
Constify a couple of static struct clk_ops that are not modified. Their
only usage is inside the macros and their address is passed to
clk_register_composite() which takes pointers to const struct clk_ops.
This allows the compiler to put them in read-only memory.
We've discovered that disabling the so called Ethernet PLL causes reset of
the devices consuming its outgoing clock. The resets happen automatically
even if each underlying clock gate is turned off. Due to that we can't
disable the Ethernet PLL until the kernel is prepared for the corresponding
resets. So for now just mark the PLL clock provider as critical.
Lars-Peter Clausen [Thu, 1 Oct 2020 08:59:48 +0000 (11:59 +0300)]
clk: axi-clkgen: Set power bits for fractional mode
Using the fractional dividers requires some additional power bits to be
set.
The fractional power bits are not documented and the current heuristic
for setting them seems be insufficient for some cases. Just always set all
the fractional power bits when in fractional mode.
Lars-Peter Clausen [Thu, 1 Oct 2020 08:59:47 +0000 (11:59 +0300)]
clk: axi-clkgen: Add support for fractional dividers
The axi-clkgen has (optional) fractional dividers on the output clock
divider and feedback clock divider path. Utilizing the fractional dividers
allows for a better resolution of the output clock, being able to
synthesize more frequencies.
Rework the driver support to support the fractional register fields, both
for setting a new rate as well as reading back the current rate from the
hardware.
For setting the rate if no perfect divider settings were found in
non-fractional mode try again in fractional mode and see if better settings
can be found. This appears to be the recommended mode of operation.
Jonathan Marek [Sun, 27 Sep 2020 19:06:50 +0000 (15:06 -0400)]
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-2-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Konrad Dybcio [Mon, 5 Oct 2020 14:58:55 +0000 (16:58 +0200)]
clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
This change adds GDSCs, resets and most of the missing
clocks to the msm8994 GCC driver. The remaining ones
are of local_vote_clk and gate_clk type, which are not
yet supported upstream. Also reorder them to match the
original downstream driver.
Stephen Boyd [Thu, 24 Sep 2020 00:41:44 +0000 (17:41 -0700)]
clk: rockchip: Initialize hw to error to avoid undefined behavior
We can get down to this return value from ERR_CAST() without
initializing hw. Set it to -ENOMEM so that we always return something
sane.
Fixes the following smatch warning:
drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'.
drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST'
Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Fixes: 956060a52795 ("clk: rockchip: add support for half divider") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Thu, 24 Sep 2020 00:00:33 +0000 (17:00 -0700)]
Merge tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
Ability to build the clock driver as module and removal
of an unused parent-names struct.
* tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3399: Support module build
clk: rockchip: fix the clk config to support module build
clk: rockchip: Export some clock common APIs for module drivers
clk: rockchip: Export rockchip_register_softrst()
clk: rockchip: Export rockchip_clk_register_ddrclk()
clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk: rockchip: rk3308: drop unused mux_timer_src_p
Tero Kristo [Mon, 7 Sep 2020 08:57:40 +0000 (11:57 +0300)]
clk: keystone: sci-clk: add 10% slack to set_rate
Currently, we request exact clock rates from the firmware to be set with
set_rate. Due to some rounding errors and internal functionality of the
firmware itself, this can fail. Thus, add some slack to the set_rate
functionality so that we are always guaranteed to pass. The firmware
always attempts to use frequency as close to the target freq as
possible despite the slack given here.
Tero Kristo [Mon, 7 Sep 2020 08:57:39 +0000 (11:57 +0300)]
clk: keystone: sci-clk: cache results of last query rate operation
Cache results of the latest query rate operation. This optimizes the
firmware interface a bit, avoiding unnecessary calls to firmware if we
know the result already; the firmware interface is pretty expensive
to use for query rate functionality.
Tero Kristo [Mon, 7 Sep 2020 08:57:38 +0000 (11:57 +0300)]
clk: keystone: sci-clk: fix parsing assigned-clock data during probe
The DT clock probe loop incorrectly terminates after processing "clocks"
only, fix this by re-starting the loop when all entries for current
DT property have been parsed.
Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware") Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-2-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=]
static const struct clk_parent_data cntr_mux[] = {
^~~~~~~~
Krzysztof Kozlowski [Wed, 16 Sep 2020 16:17:39 +0000 (18:17 +0200)]
clk: si5341: drop unused 'err' variable
'err' is assigned but never read:
/drivers/clk/clk-si5341.c: In function ‘si5341_output_get_parent’:
drivers/clk/clk-si5341.c:886:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable]
Krzysztof Kozlowski [Wed, 16 Sep 2020 16:17:38 +0000 (18:17 +0200)]
clk: mmp: pxa1928: drop unused 'clk' variable
'clk' is assigned but never read:
drivers/clk/mmp/clk-of-pxa1928.c: In function ‘pxa1928_pll_init’:
drivers/clk/mmp/clk-of-pxa1928.c:71:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable]
Krzysztof Kozlowski [Mon, 21 Sep 2020 20:35:57 +0000 (22:35 +0200)]
clk: s2mps11: initialize driver via module_platform_driver
The driver was using subsys_initcall() because in old times deferred
probe was not supported everywhere and specific ordering was needed.
Since probe deferral works fine and specific ordering is discouraged
(hides dependencies between drivers and couples their boot order), the
driver can be converted to regular module_platform_driver.
Stephen Boyd [Tue, 22 Sep 2020 19:23:34 +0000 (12:23 -0700)]
Merge tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
Minor refactoring removing most of the __clk_lookup() calls.
* tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
clk: samsung: Add clk ID definitions for the CPU parent clocks
clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
clk: samsung: Keep top BPLL mux on Exynos542x enabled
Stephen Boyd [Tue, 22 Sep 2020 19:18:57 +0000 (12:18 -0700)]
Merge tag 'clk-imx-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk driver updates from Shawn Guo:
- A series from Anson Huang to support building i.MX ARMv8 platforms clock driver as module
- Remove i.MX21 clock driver, as i.MX21 platform support is being dropped
- A couple of minor imx8mp clock correction from Jacky Bai
- Add clock for CRC block found on vf610 SoC
- A couple of clock flag fix-up from Peng Fan
- Minor kerneldoc fix-up for i.MX clock drivers
* tag 'clk-imx-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
Stephen Boyd [Wed, 16 Sep 2020 23:12:01 +0000 (16:12 -0700)]
clk: qcom: dispcc: Update DP clk ops for phy design
The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk.
This function should return the rate that can be achieved by the pixel
clk in 'struct clk_rate_request::rate' and match the logic similar to
what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead
the code merely bubbles the rate request up to the parent of the pixel
clk and doesn't try to do a rational approximation of the rate that
would be achieved by picking some m/n value for the RCG.
Let's change this logic so that we can assume the parent clk frequency
is fixed (it is because it's the VCO of the DP PLL that is configured
based on the link rate) and so that we can calculate what the m/n value
will be and adjust the req->rate appropriately.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-10-swboyd@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jason Yan [Fri, 11 Sep 2020 01:37:22 +0000 (09:37 +0800)]
clk: qcom: gcc-msm8939: remove defined but not used variables
This addresses the following gcc warning with "make W=1":
drivers/clk/qcom/gcc-msm8939.c:610:32: warning:
‘gcc_xo_gpll6_gpll0a_map’ defined but not used
[-Wunused-const-variable=]
static const struct parent_map gcc_xo_gpll6_gpll0a_map[] = {
^~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/qcom/gcc-msm8939.c:598:32: warning: ‘gcc_xo_gpll6_gpll0_map’
defined but not used [-Wunused-const-variable=]
static const struct parent_map gcc_xo_gpll6_gpll0_map[] = {
^~~~~~~~~~~~~~~~~~~~~~
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
clk: rockchip: fix the clk config to support module build
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
to support building Rk3399 SoC clock driver as module.
Krzysztof Kozlowski [Wed, 16 Sep 2020 16:17:40 +0000 (18:17 +0200)]
clk: rockchip: rk3308: drop unused mux_timer_src_p
The parent names 'mux_timer_src_p' is not used:
In file included from drivers/clk/rockchip/clk-rk3308.c:13:0:
drivers/clk/rockchip/clk-rk3308.c:136:7: warning: ‘mux_timer_src_p’ defined but not used [-Wunused-const-variable=]
Stephen Boyd [Mon, 21 Sep 2020 20:55:22 +0000 (13:55 -0700)]
Merge tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard:
Our usual PR for the Allwinner SoCs, this time adding support for the
Allwinner A100 SoC, and adding support for the sigma-delta modulation on
the audio PLL for the R40.
* tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
clk: sunxi-ng: add support for the Allwinner A100 CCU
dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
Stephen Boyd [Mon, 21 Sep 2020 20:49:11 +0000 (13:49 -0700)]
Merge tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the new R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on RZ/G1H,
- Fix VSP clock names to match corrected hardware documentation.
- Minor fixes and improvements
* tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3: Update description for RZ/G2
clk: renesas: cpg-mssr: Add support for R-Car V3U
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
clk: renesas: r8a7742: Add clk entry for VSPR
Initial support for R-Car V3U (r8a779a0), including core, module
clocks, resets, and register access, because register specification
differs from R-Car Gen2/3.
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv.
After that, we can remove unused macros like MSTPSR(). No behavioral
changes.
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
Geert suggested defining multiple register layout variants using an enum
[1] to support further devices like R-Car V3U. So, use enum
clk_reg_layout instead of a boolean .stbyctrl flag. No behavioral
change.
Sylwester Nawrocki [Wed, 26 Aug 2020 17:15:29 +0000 (19:15 +0200)]
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
For the CPU clock registration two parent clocks are required, these
are now being passed as struct clk_hw pointers, rather than by the
global scope names. That allows us to avoid __clk_lookup() calls
and simplifies a bit the CPU clock registration function.
While at it drop unneeded extern keyword in the function declaration.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20200826171529.23618-3-s.nawrocki@samsung.com Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Wed, 26 Aug 2020 17:15:28 +0000 (19:15 +0200)]
clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
Use non-zero clock IDs in definitions of the CPU parent clocks
for exynos5420, exynos5250 SoCs. This will allow us to reference
the parent clocks directly in the driver by cached struct clk_hw
pointers, rather than doing clk lookup by name.
Sylwester Nawrocki [Wed, 26 Aug 2020 17:15:27 +0000 (19:15 +0200)]
clk: samsung: Add clk ID definitions for the CPU parent clocks
Add clock ID definitions for the CPU parent clocks for SoCs
which don't have such definitions yet. This will allow us to
reference the parent clocks directly by cached struct clk_hw
pointers in the clock provider, rather than doing clk lookup
by name.
Sylwester Nawrocki [Tue, 11 Aug 2020 15:12:51 +0000 (17:12 +0200)]
clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related
clk pointer gets cached in the driver's private data and can be used
later instead of a __clk_lookup() call.
With that we have all clocks used in the clk_prepare_enable() calls in the
clk provider init callback cached in clk_data.hws[] and we can reference
the clk pointers directly rather than using __clk_lookup() with global names.
Sylwester Nawrocki [Tue, 11 Aug 2020 15:12:50 +0000 (17:12 +0200)]
clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
This patch adds ID for the mout_sw_aclk_g3d (SW_CLKMUX_ACLK_G3D) clock,
mostly for internal use in the CMU driver. It will allow to avoid the
__clk_lookup() call when setting up the clock during the clock provider
initialization.
Marek Szyprowski [Fri, 7 Aug 2020 13:31:43 +0000 (15:31 +0200)]
clk: samsung: Keep top BPLL mux on Exynos542x enabled
BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred
the clock might get disabled what causes board hang. Fix this by calling
clk_prepare_enable() directly from the clock provider driver.
Cc: stable@vger.kernel.org Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Tested-by: Lukasz Luba <lukasz.luba@arm.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@samsung.com Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Krzysztof Kozlowski [Wed, 2 Sep 2020 15:02:44 +0000 (17:02 +0200)]
clk: imx: Fix and update kerneldoc
Fix and add missing kerneldoc to fix compile warnings like:
drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw' not described in 'clk_pfd'
drivers/clk/imx/clk-pllv3.c:53: warning: Function parameter or member 'ref_clock' not described in 'clk_pllv3'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lad Prabhakar [Mon, 31 Aug 2020 18:37:22 +0000 (19:37 +0100)]
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which
stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and
"vsp1-rt". The clock section in the SoC datasheets misunderstood the
abbreviations as meaning VSP System and VSP Realtime, and named the
corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been
carried over to the kernel code.
This patch fixes this by renaming the clock names to "vsps" and "vspr".
Inspired from commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename
VSP1_(SY|RT) clocks to VSP1_(S|R)")
Jacky Bai [Mon, 24 Aug 2020 07:37:02 +0000 (15:37 +0800)]
clk: imx: Correct the memrepair clock on imx8mp
The root clock slice at offset 0xbf80 should be memrepair
clock, so correct it. And this clock should be always on
to make sure the memory repair function can works well.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefan Agner [Fri, 28 Aug 2020 15:52:05 +0000 (17:52 +0200)]
clk: meson: g12a: mark fclk_div2 as critical
On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2
seems to be necessary for the system to operate correctly as well.
Typically, the clock also gets chosen by the eMMC peripheral. This
probably masked the problem so far. However, when booting from a SD
card the clock seems to get disabled which leads to a system freeze.
Let's mark this clock as critical, fixing boot from SD card on G12b
platforms.
projects / users / jedix / linux-maple.git / log