Bjorn Helgaas [Sat, 28 Oct 2023 18:31:05 +0000 (13:31 -0500)]
Merge branch 'pci/field-get'
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
Järvinen, Bjorn Helgaas)
- Rework DPC control programming for clarity (Ilpo Järvinen)
* pci/field-get:
PCI/portdrv: Use FIELD_GET()
PCI/VC: Use FIELD_GET()
PCI/PTM: Use FIELD_GET()
PCI/PME: Use FIELD_GET()
PCI/ATS: Use FIELD_GET()
PCI/ATS: Show PASID Capability register width in bitmasks
PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
PCI: Use FIELD_GET()
PCI/MSI: Use FIELD_GET/PREP()
PCI/DPC: Use defines with DPC reason fields
PCI/DPC: Use defined fields with DPC_CTL register
PCI/DPC: Use FIELD_GET()
PCI: hotplug: Use FIELD_GET/PREP()
PCI: dwc: Use FIELD_GET/PREP()
PCI: cadence: Use FIELD_GET()
PCI: Use FIELD_GET() to extract Link Width
PCI: mvebu: Use FIELD_PREP() with Link Width
PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields
* pci/config-errs:
scsi: ipr: Do PCI error checks on own line
PCI: xgene: Do PCI error check on own line & keep return value
PCI: Do error check on own line to split long "if" conditions
atm: iphase: Do PCI error checks on own line
sh: pci: Do PCI error check on own line
alpha: Streamline convoluted PCI error handling
Bjorn Helgaas [Sat, 28 Oct 2023 18:31:02 +0000 (13:31 -0500)]
Merge branch 'pci/controller/xilinx-ecam'
- Drop xilinx-nwl updates of bridge bus number fields, since PCI core
already does that (Thippeswamy Havalige)
- Update xilinx-nwl driver and ECAM size in devicetree example to allow up
to 256 buses (Thippeswamy Havalige)
* pci/controller/xilinx-ecam:
PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro
dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example
PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields
Bjorn Helgaas [Sat, 28 Oct 2023 18:31:02 +0000 (13:31 -0500)]
Merge branch 'pci/controller/speed'
- Use PCIE_SPEED2MBS_ENC() macro in qcom host and endpoint to encode link
speed instead of hard-coding the link speed in MBps (Manivannan
Sadhasivam)
- Use Mbps_to_icc() (not MBps_to_icc()) in tegra194 instead of explicitly
doing the bytes-to-bits conversion (Manivannan Sadhasivam)
* pci/controller/speed:
PCI: tegra194: Use Mbps_to_icc() macro for setting icc speed
PCI: qcom-ep: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
PCI: qcom: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
Bjorn Helgaas [Sat, 28 Oct 2023 18:31:01 +0000 (13:31 -0500)]
Merge branch 'pci/controller/rcar'
- Add generic T_PVPERL macro for the required interval between power being
stable and PERST# being inactive (Yoshihiro Shimoda)
- Factor out dw_pcie_link_set_max_link_width() (Yoshihiro Shimoda)
- Update PCI_EXP_LNKCAP_MLW so Link Capabilities shows the correct max link
width (Yoshihiro Shimoda)
- Drop tegra194 PCI_EXP_LNKCAP_MLW setting since dw_pcie_setup() already
does it (Yoshihiro Shimoda)
- Add dwc support for different dbi and dbi2 register offsets, to be used
for R-Car Gen4 controllers (Yoshihiro Shimoda)
- Add EDMA_UNROLL capability flag for R-Car Gen4 controllers that don't
correctly advertise unrolled mapping via their eDMA CTRL register
(Yoshihiro Shimoda)
- Export dw_pcie_ep_exit() for use by the modular R-Car Gen4 driver
(Yoshihiro Shimoda)
- Add .pre_init() and .deinit() hooks for use by R-Car Gen4 controllers
(Yoshihiro Shimoda)
- Increase snps,dw-pcie DT reg and reg-names maxItems for R-Car Gen4
controllers (Yoshihiro Shimoda)
- Add rcar-gen4-pci host and endpoint DT bindings and drivers (Yoshihiro
Shimoda)
- Add Renesas R8A779F0 Device ID to pci_endpoint_test to allow testing on
R-Car S4-8 (Yoshihiro Shimoda)
* pci/controller/rcar:
misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
PCI: rcar-gen4: Add endpoint mode support
PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode
dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
PCI: dwc: Expose dw_pcie_write_dbi2() to module
PCI: dwc: Expose dw_pcie_ep_exit() to module
PCI: dwc: Add EDMA_UNROLL capability flag
PCI: dwc: endpoint: Add multiple PFs support for dbi2
PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
PCI: dwc: Add dw_pcie_link_set_max_link_width()
PCI: Add T_PVPERL macro
Bjorn Helgaas [Sat, 28 Oct 2023 18:31:00 +0000 (13:31 -0500)]
Merge branch 'pci/vga'
- Add pci_is_vga() helper, which checks for both PCI_CLASS_DISPLAY_VGA and
PCI_CLASS_NOT_DEFINED_VGA (which catches ancient devices built before
Class Codes were defined) (Sui Jingfeng)
- Use the new pci_is_vga() to identify devices for the VGA arbiter, the
sysfs "boot_vga" attribute, and the virtio and qxl drivers (SUi Jingfeng)
* pci/vga:
drm/qxl: Use pci_is_vga() to identify VGA devices
drm/virtio: Use pci_is_vga() to identify VGA devices
PCI/sysfs: Enable 'boot_vga' attribute via pci_is_vga()
PCI/VGA: Select VGA devices earlier
PCI/VGA: Use pci_is_vga() to identify VGA devices
PCI: Add pci_is_vga() helper
Bjorn Helgaas [Sat, 28 Oct 2023 18:30:59 +0000 (13:30 -0500)]
Merge branch 'pci/p2pdma'
- Move struct dev_pagemap (a flexible structure) to end of struct
pci_p2pdma_pagemap to avoid overwriting things after dev_pagemap
(Gustavo A. R. Silva)
Bjorn Helgaas [Sat, 28 Oct 2023 18:30:57 +0000 (13:30 -0500)]
Merge branch 'pci/aspm'
* pci/aspm:
PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common()
Revert "PCI/ASPM: Disable only ASPM_STATE_L1 when driver, disables L1"
PCI/ASPM: Convert printk() to pr_*() and add include
PCI/ASPM: Remove unnecessary includes
PCI/ASPM: Use FIELD_MAX() instead of literals
PCI/ASPM: Use time constants
PCI/ASPM: Return U32_MAX instead of bit magic construct
PCI/ASPM: Use FIELD_GET/PREP() to access PCIe capability fields
PCI: Add PCI_L1SS_CTL2 fields
Thippeswamy Havalige [Mon, 16 Oct 2023 05:11:02 +0000 (10:41 +0530)]
PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
The PCIe Root Port controller expects ECAM size to be set through software.
As such, update the value of the NWL_ECAM_VALUE_DEFAULT macro to 16 to
allow the controller to address the 256 MB ECAM region and, as such,
enable support for detecting up to 256 buses.
D Scott Phillips [Sat, 30 Sep 2023 00:20:36 +0000 (17:20 -0700)]
PCI: hotplug: Add Ampere Altra Attention Indicator extension driver
On Ampere Altra, PCIe hotplug is handled through ACPI. A side interface is
also present to request system firmware control of the hotplug Attention
Indicators. Add an ACPI PCI Hotplug companion driver to support Attention
Indicator control.
D Scott Phillips [Sat, 30 Sep 2023 00:20:35 +0000 (17:20 -0700)]
PCI: acpiphp: Allow built-in drivers for Attention Indicators
Since the introduction of the attention callback in acpiphp, a non-zero
struct module *owner has been required in acpiphp_register_attention(). The
intent seemed to be that the core code could hold a refcount on the module
while invoking a callback.
This check accidentally precludes the possibility of attention callbacks to
built-in drivers.
Remove the check on `struct module *owner` in acpiphp_register_attention()
so attention callbacks can also be registered from built-in drivers.
Bjorn Helgaas [Tue, 10 Oct 2023 20:44:30 +0000 (15:44 -0500)]
PCI/ATS: Show PASID Capability register width in bitmasks
The PASID Capability and Control registers are both 16 bits wide. Use
16-bit wide constants in field names to match the register width. No
functional change intended.
Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Heiner Kallweit [Wed, 11 Oct 2023 07:46:45 +0000 (09:46 +0200)]
PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common()
aspm_attr_store_common(), which handles sysfs control of ASPM, has the same
problem as fb097dcd5a28 ("PCI/ASPM: Disable only ASPM_STATE_L1 when driver
disables L1"): disabling L1 adds only ASPM_L1 (but not any of the L1.x
substates) to the "aspm_disable" mask.
Enabling one substate, e.g., L1.1, via sysfs removes ASPM_L1 from the
disable mask. Since disabling L1 via sysfs doesn't add any of the
substates to the disable mask, enabling L1.1 actually enables *all* the
substates.
In this scenario:
- Write 0 to "l1_aspm" to disable L1
- Write 1 to "l1_1_aspm" to enable L1.1
the intention is to disable L1 and all L1.x substates, then enable just
L1.1, but in fact, *all* L1.x substates are enabled.
Fix this by explicitly disabling all the L1.x substates when disabling L1.
After fb097dcd5a28 ("PCI/ASPM: Disable only ASPM_STATE_L1 when driver
disables L1"), disabling L1 via pci_disable_link_state(PCIE_LINK_STATE_L1),
then enabling one substate, e.g., L1.1, via sysfs actually enables *all*
the substates.
For example, r8169 disables L1 because of hardware issues on a number of
systems, which implicitly disables the L1.1 and L1.2 substates.
On some systems, L1 and L1.1 work fine, but L1.2 causes missed rx packets.
Enabling L1.1 via the sysfs "aspm_l1_1" attribute unexpectedly enables L1.2
as well as L1.1.
After fb097dcd5a28, pci_disable_link_state(PCIE_LINK_STATE_L1) adds only
ASPM_L1 (but not any of the L1.x substates) to the "aspm_disable" mask:
Enabling an L1.x substate removes the substate and L1 from the
"aspm_disable" mask. After fb097dcd5a28, the substates were not added to
the mask when disabling L1, so enabling one substate implicitly enables all
of them.
Revert fb097dcd5a28 so enabling one substate doesn't enable the others.
Ilpo Järvinen [Tue, 24 Oct 2023 11:03:36 +0000 (14:03 +0300)]
PCI: dwc: Use FIELD_GET/PREP()
Convert open-coded variants of PCI field access into FIELD_GET/PREP()
to make the code easier to understand.
Add two missing defines into pci_regs.h. Logically, the Max No-Snoop
Latency Register is a separate word sized register in the PCIe spec,
but the pre-existing LTR defines in pci_regs.h with dword long values
seem to consider the registers together (the same goes for the only
user). Thus, follow the custom and make the new values also take both
word long LTR registers as a joint dword register.
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:28 +0000 (17:56 +0900)]
PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode
Add R-Car Gen4 PCIe controller support for host mode.
This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code like mode setting and retraining and
so on.
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:24 +0000 (17:56 +0900)]
PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
Renesas R-Car Gen4 PCIe controllers require vendor-specific
initialization before .init().
To use dw->dbi and dw->num-lanes in the initialization code,
introduce .pre_init() into struct dw_pcie_ep_ops. While at it,
also introduce .deinit() to disable the controller by using
vendor-specific de-initialization.
Note that the ep_init in the struct dw_pcie_ep_ops should be
renamed to init later.
Since no PCIe controller drivers call this, this change is not required
for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
and if the controller driver is built as a kernel module, the following
build error happens:
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:23 +0000 (17:56 +0900)]
PCI: dwc: Expose dw_pcie_ep_exit() to module
Since no PCIe controller drivers call this, this change is not required
for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
and if the controller driver is built as a kernel module, the following
build error happens:
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:21 +0000 (17:56 +0900)]
PCI: dwc: endpoint: Add multiple PFs support for dbi2
The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
for DWC") added .func_conf_select() to get the configuration space of
different PFs and assumed that the offsets between dbi and dbi2 would
be the same.
However, Renesas R-Car Gen4 PCIe controllers have different offsets of
function 1: dbi (+0x1000) and dbi2 (+0x800). To get the offset for dbi2,
add .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset().
Note:
- .func_conf_select() should be renamed later.
- dw_pcie_ep_get_dbi2_offset() will call .func_conf_select()
if .get_dbi2_offset() doesn't exist for backward compatibility.
- dw_pcie_writeX_{dbi/dbi2} APIs accepted the func_no argument,
so that these offset calculations are contained in the API
definitions itself as it should.
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:19 +0000 (17:56 +0900)]
PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
field there is another one which needs to be updated.
It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
the very least the maximum link-width capability CSR won't expose the
actual maximum capability.
[1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.60a, March 2015, p.1032
[2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.70a, March 2016, p.1065
[3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.90a, March 2016, p.1057
...
[X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
Version 5.40a, March 2019, p.1396
[X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 5.40a, March 2019, p.1266
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:18 +0000 (17:56 +0900)]
PCI: dwc: Add dw_pcie_link_set_max_link_width()
This is a preparation before adding the Max-Link-width capability
setup which would in its turn complete the max-link-width setup
procedure defined by Synopsys in the HW-manual.
Seeing there is a max-link-speed setup method defined in the DW PCIe
core driver it would be good to have a similar function for the link
width setup.
That's why we need to define a dedicated function first from already
implemented but incomplete link-width setting up code.
Yoshihiro Shimoda [Wed, 18 Oct 2023 08:56:17 +0000 (17:56 +0900)]
PCI: Add T_PVPERL macro
According to the PCIe CEM r5.0, sec 2.9.2, Power stable to PERST#
inactive interval is 100 ms as minimum. Add a macro so that the PCIe
controller drivers can make use of it.
PCI: Disable ATS for specific Intel IPU E2000 devices
Due to a hardware issue in A and B steppings of Intel IPU E2000, it expects
wrong endianness in ATS invalidation message body. This problem can lead to
outdated translations being returned as valid and finally cause system
instability.
To prevent such issues, add quirk_intel_e2000_no_ats() to disable ATS for
vulnerable IPU E2000 devices.
Link: https://lore.kernel.org/r/20230908143606.685930-3-bartosz.pawlowski@intel.com Signed-off-by: Bartosz Pawlowski <bartosz.pawlowski@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Alexander Lobakin <aleksander.lobakin@intel.com>
Ilpo Järvinen [Tue, 19 Sep 2023 12:56:46 +0000 (15:56 +0300)]
PCI: Use FIELD_GET() to extract Link Width
Use FIELD_GET() to extract PCIe Negotiated and Maximum Link Width fields
instead of custom masking and shifting.
Link: https://lore.kernel.org/r/20230919125648.1920-7-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
[bhelgaas: drop duplicate include of <linux/bitfield.h>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
PCI: hv: Annotate struct hv_dr_state with __counted_by
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
As found with Coccinelle[1], add __counted_by for struct hv_dr_state.
Manivannan Sadhasivam [Tue, 10 Oct 2023 15:59:14 +0000 (21:29 +0530)]
PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops
ASPM is supported by Qcom host controllers/bridges on most of the recent
platforms and so the devices tested so far. But for enabling ASPM by
default (without using Kconfig, kernel command-line or sysfs), BIOS has
to enable ASPM on both host bridge and downstream devices during boot.
Unfortunately, none of the BIOS available on Qcom platforms enables
ASPM. Due to this, the platforms making use of Qcom SoCs draw high power
during runtime.
To fix this power draw issue, users have to enable ASPM using Kconfig,
kernel command-line, sysfs or the BIOS has to start enabling ASPM.
The latter may happen in the future, but that won't address the issue on
current platforms. Also, asking users to enable a feature to get the power
management right would provide an unpleasant out-of-the-box experience.
So the apt solution is to enable ASPM in the controller driver itself. And
this is being accomplished by calling pci_enable_link_state() in the newly
introduced host_post_init() callback for all the devices connected to the
bus. This function enables all supported link low power states for both
host bridge and the downstream devices.
Due to limited testing, ASPM is only enabled for platforms making use of
ops_1_9_0 callbacks.
Manivannan Sadhasivam [Tue, 10 Oct 2023 15:59:13 +0000 (21:29 +0530)]
PCI: dwc: Add host_post_init() callback
This callback can be used by the platform drivers to do configuration
once all the devices are scanned. Like changing LNKCTL of all downstream
devices to enable ASPM etc...
Manivannan Sadhasivam [Wed, 4 Oct 2023 16:44:30 +0000 (22:14 +0530)]
PCI: tegra194: Use Mbps_to_icc() macro for setting icc speed
PCIe speed returned by the PCIE_SPEED2MBS_ENC() macro is in Mbps. So
instead of converting it to MBps explicitly and using the MBps_to_icc()
macro, let's use the Mbps_to_icc() macro to pass the value directly.
Manivannan Sadhasivam [Wed, 4 Oct 2023 16:44:29 +0000 (22:14 +0530)]
PCI: qcom-ep: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
Instead of hardcoding the link speed in MBps, use existing
PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for
us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do
the conversion to ICC speed.
This eliminates the need for a switch case in qcom_pcie_icc_update() and
also works for future Gen speeds without any code modifications.
Manivannan Sadhasivam [Wed, 4 Oct 2023 16:44:28 +0000 (22:14 +0530)]
PCI: qcom: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
Instead of hardcoding the link speed in MBps, use existing
PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for
us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do
the conversion to ICC speed.
This eliminates the need for a switch case in qcom_pcie_icc_update() and
also works for future Gen speeds without any code modifications.
Ilpo Järvinen [Mon, 11 Sep 2023 12:53:53 +0000 (15:53 +0300)]
PCI: xgene: Do PCI error check on own line & keep return value
Instead of an "if" condition with a line split, use the usual error
handling pattern with a separate variable to improve readability.
pci_generic_config_read32() already returns either PCIBIOS_SUCCESSFUL or
PCIBIOS_DEVICE_NOT_FOUND so it is enough to simply return its return value
when ret != PCIBIOS_SUCCESSFUL.
Ilpo Järvinen [Mon, 11 Sep 2023 12:53:52 +0000 (15:53 +0300)]
PCI: Do error check on own line to split long "if" conditions
Placing PCI error code check inside "if" condition usually results in need
to split lines. Combined with additional conditions the "if" condition
becomes messy.
Convert to the usual error handling pattern with an additional variable to
improve code readability. In addition, reverse the logic in
pci_find_vsec_capability() to get rid of &&.
Ilpo Järvinen [Mon, 11 Sep 2023 12:53:51 +0000 (15:53 +0300)]
atm: iphase: Do PCI error checks on own line
In get_esi() PCI errors are checked inside line-split "if" conditions (in
addition to the file not following the coding style). To make the code in
get_esi() more readable, fix the coding style and use the usual error
handling pattern with a separate variable.
In addition, initialization of 'error' variable at declaration is not
needed.
Ilpo Järvinen [Tue, 19 Sep 2023 12:56:45 +0000 (15:56 +0300)]
PCI: mvebu: Use FIELD_PREP() with Link Width
mvebu_pcie_setup_hw() setups the Maximum Link Width field in the Link
Capabilities registers using an open-coded variant of FIELD_PREP() with
a literal in shift. Improve readability by using
FIELD_PREP(PCI_EXP_LNKCAP_MLW, ...).
Ilpo Järvinen [Tue, 19 Sep 2023 12:56:44 +0000 (15:56 +0300)]
PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields
Use FIELD_GET() to extract PCIe Negotiated Link Width field instead of
custom masking and shifting.
Similarly, change custom code that misleadingly used
PCI_EXP_LNKSTA_NLW_SHIFT to prepare value for PCI_EXP_LNKCAP write
to use FIELD_PREP() with correct field define (PCI_EXP_LNKCAP_MLW).
Uwe Kleine-König [Sun, 1 Oct 2023 17:02:54 +0000 (19:02 +0200)]
PCI: keystone: Don't discard .probe() callback
The __init annotation makes the ks_pcie_probe() function disappear after
booting completes. However a device can also be bound later. In that case,
we try to call ks_pcie_probe(), but the backing memory is likely already
overwritten.
The right thing to do is do always have the probe callback available. Note
that the (wrong) __refdata annotation prevented this issue to be noticed by
modpost.
Uwe Kleine-König [Sun, 1 Oct 2023 17:02:53 +0000 (19:02 +0200)]
PCI: keystone: Don't discard .remove() callback
With CONFIG_PCIE_KEYSTONE=y and ks_pcie_remove() marked with __exit, the
function is discarded from the driver. In this case a bound device can
still get unbound, e.g via sysfs. Then no cleanup code is run resulting in
resource leaks or worse.
The right thing to do is do always have the remove callback available.
Note that this driver cannot be compiled as a module, so ks_pcie_remove()
was always discarded before this change and modpost couldn't warn about
this issue. Furthermore the __ref annotation also prevents a warning.
Uwe Kleine-König [Sun, 1 Oct 2023 17:02:52 +0000 (19:02 +0200)]
PCI: kirin: Don't discard .remove() callback
With CONFIG_PCIE_KIRIN=y and kirin_pcie_remove() marked with __exit, the
function is discarded from the driver. In this case a bound device can
still get unbound, e.g via sysfs. Then no cleanup code is run resulting in
resource leaks or worse.
The right thing to do is do always have the remove callback available.
This fixes the following warning by modpost:
Uwe Kleine-König [Sun, 1 Oct 2023 17:02:51 +0000 (19:02 +0200)]
PCI: exynos: Don't discard .remove() callback
With CONFIG_PCI_EXYNOS=y and exynos_pcie_remove() marked with __exit, the
function is discarded from the driver. In this case a bound device can
still get unbound, e.g via sysfs. Then no cleanup code is run resulting in
resource leaks or worse.
The right thing to do is do always have the remove callback available.
This fixes the following warning by modpost:
Sui Jingfeng [Wed, 30 Aug 2023 11:15:32 +0000 (19:15 +0800)]
drm/qxl: Use pci_is_vga() to identify VGA devices
Use pci_is_vga() to identify VGA devices instead of a private is_vga()
function.
This means qxl will use the VGA arbiter for old PCI_CLASS_NOT_DEFINED_VGA
(0x0001) devices as well as the PCI_CLASS_DISPLAY_VGA (0x0300) devices it
recognized previously.
This probably doesn't make a difference because qxl_pci_driver doesn't
claim PCI_CLASS_NOT_DEFINED_VGA devices by default, so it's mainly a code
simplification.
Link: https://lore.kernel.org/r/20230830111532.444535-6-sui.jingfeng@linux.dev Signed-off-by: Sui Jingfeng <suijingfeng@loongson.cn>
[bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch>
Sui Jingfeng [Wed, 30 Aug 2023 11:15:31 +0000 (19:15 +0800)]
drm/virtio: Use pci_is_vga() to identify VGA devices
Use pci_is_vga() to identify VGA devices instead of open-coding the class
test.
This means virtio_gpu_pci_quirk() will apply to old
PCI_CLASS_NOT_DEFINED_VGA (0x0001) devices as well as the
PCI_CLASS_DISPLAY_VGA (0x0300) devices it did previously.
Sui Jingfeng [Wed, 30 Aug 2023 11:15:30 +0000 (19:15 +0800)]
PCI/sysfs: Enable 'boot_vga' attribute via pci_is_vga()
Enable the 'boot_vga' sysfs attribute via pci_is_vga().
This exposes 'boot_vga' for old PCI_CLASS_NOT_DEFINED_VGA (0x0001) devices
as well as for the PCI_CLASS_DISPLAY_VGA (0x0300) devices where it was
previously exposed.
Sui Jingfeng [Fri, 6 Oct 2023 21:48:38 +0000 (16:48 -0500)]
PCI/VGA: Select VGA devices earlier
Select VGA devices in vga_arb_device_init() and pci_notify() instead of in
vga_arbiter_add_pci_device().
This is a trivial optimization for adding devices. It's a bigger
optimization for the removal case because pci_notify() won't call
vga_arbiter_del_pci_device() for non-VGA devices, so it won't have to
search the vga_list for them.
https://lore.kernel.org/r/20230830111532.444535-3-sui.jingfeng@linux.dev Signed-off-by: Sui Jingfeng <suijingfeng@loongson.cn>
[bhelgaas: commit log, split from functional change] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
projects / linux.git / log