Hawking Zhang [Thu, 31 Dec 2020 04:50:56 +0000 (12:50 +0800)]
drm/amdgpu: switch to cached noretry setting for aldebaran
global noretry setting now is cached to gmc.noretry
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Laurent Morichetti [Tue, 22 Dec 2020 19:42:46 +0000 (11:42 -0800)]
drm/amdkfd: Fix saving the ACC vgprs for Aldebaran
get_num_acc_vgprs does not set status.scc if the number of acc vgprs
is 0, so use an and instruction to set the condition code.
The Aldebaran handler binary was not based on the latest version of
the sources, so this update to the binary is the minimal change only
adding two instructions to set the condition code.
A newer version of the handler should be generated and tested in
another commit.
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Tue, 15 Dec 2020 00:15:42 +0000 (18:15 -0600)]
drm/amdgpu: UTLC1 RB SDMA timeout on Aldebaran
[Why]
This causes infinite retries on the UTCL1 RB, preventing
higher priority RB such as paging RB.
[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs.
Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Sat, 28 Nov 2020 09:31:08 +0000 (17:31 +0800)]
drm/amd/pm: Add support to override pptable id for aldebaran
Temporarily force to use BU PPTable defined in VBIOS. Add support to
override PPTable defined by module parameter.Add FW reported version to
kernel log.
Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Sun, 22 Nov 2020 03:13:19 +0000 (21:13 -0600)]
drm/amdgpu: Don't do FB resize under A+A config
Disable PCIe BAR resizing on A+A config. It's not needed because we won't use the
PCIe BAR, but it breaks the PCI BAR configuration with the current SBIOS.
Error message of FB BAR resize failure under A+A:
[ 154.913731] [drm:amdgpu_device_resize_fb_bar [amdgpu]] *ERROR* Problem resizing BAR0 (-22).
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.kuehling@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Sat, 21 Nov 2020 04:18:10 +0000 (22:18 -0600)]
drm/amdgpu: pre-map device buffer as cached for A+A config
For A+A configuration, device memory is supposed to be mapped as
cachable from CPU side. For kernel pre-map gpu device memory using
ioremap_cache
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 16:20:35 +0000 (00:20 +0800)]
drm/amdgpu: switch to vega20 ih block for aldebaran
replace vega10 ih block with vega20 ih block for
aldebaran.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:50:51 +0000 (23:50 +0800)]
drm/amdgpu: correct IH_CHICKEN programming for aldebaran
For aldebaran, psp firmware won't program IH_CHICKEN.
it now depends on driver to program it properly so
either bus address or gpu virtual address is just
working for ih ring.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 18 Nov 2020 10:28:08 +0000 (18:28 +0800)]
drm/amdgpu: apply sdma golden settings for aldebaran
perform one-time initialization for sdma registers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 17 Nov 2020 07:51:29 +0000 (15:51 +0800)]
drm/amdgpu: use physical_node_id to calculate aper_base
Similar as xgmi connected gpu nodes, physical_node_id
* segment_size should be used to calculate the offset
of aper_base.
The asic type check is redundant. once physical_node_id
and segment_size are initialized, it should be count
on.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 16 Nov 2020 07:54:36 +0000 (15:54 +0800)]
drm/amdgpu: init gds for aldebaran
aldebaran removed gds internal memory for atomic usage.
it only supports gws opcode in kernel like barrier,
semaphore.etc. there won't be usage of gds in either
kernel or pm4 packet. max_wave_id should also be marked
as deprecated for aldebaran.
Feifei Xu [Thu, 19 Nov 2020 10:12:26 +0000 (18:12 +0800)]
drm/amdgpu:add smu mode1/2 support for aldebaran
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.
Hawking Zhang [Thu, 12 Nov 2020 02:34:58 +0000 (10:34 +0800)]
drm/amdgpu: initialize external rev_id for aldebaran
add exteranal rev_id for aldebaran
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 9 Sep 2020 05:56:44 +0000 (13:56 +0800)]
drm/amdgpu: declare sdma firmware binary file for aldebaran
declare sdma firmware binary file for aldebaran
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 21 Aug 2020 14:12:50 +0000 (22:12 +0800)]
drm/amdgpu: comments out vcn/jpeg ip blocks for aldebaran
vcn fw front door loading is not functional. comments
out vcn/jpeg ip blocks so people can load amdgpu driver
without specify ip_mask module parameter.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 21 Aug 2020 14:09:06 +0000 (22:09 +0800)]
drm/amdgpu: initialize ta firmware for aldebaran
only xgmi ta is supported at this stage
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 8 Sep 2020 08:45:59 +0000 (16:45 +0800)]
drm/amdgpu: switch to use reg distance member for mmhub v1_7
switch to use register distance member for mmhub v1_7
instead of hardcode
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Tue, 11 Aug 2020 20:02:38 +0000 (15:02 -0500)]
drm/amdgpu: Clean up mmhub functions for aldebaran
Add more function pointers to amdgpu_mmhub_funcs. ASIC specific
implementation of most mmhub functions are called from a general
function pointer, instead of calling different function for
different ASIC.
V2: Split patch into upstreamable and aldebaran
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Feb 2021 21:38:22 +0000 (16:38 -0500)]
drm/amdgpu: skip MEC2_JT initialization for aldebaran
MEC2_JT is not supported
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Currently host-gpu io link is always reported as PCIe however, on some
A+A systems, there could be one xgmi link available. This change exposes
xgmi link via sysfs when it is present.
v2: fix includes (Alex)
Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support get xgmi information for Aldebaran
Aldebaran uses registers defined in header gc_9_4_2 but much of the xgmi
related functionality can be obtained by reusing the exisitng definition
from gfxhub_v1_1_get_xgmi_info. While adding support for Aldebaran, also
refactored code to better handle the new scenario.
Rajneesh Bhardwaj [Wed, 21 Oct 2020 06:12:11 +0000 (14:12 +0800)]
drm/amdgpu: define address map for host xgmi link (v3)
This applies to AMD Accelerated Processing Platforms that support host
gpu interconnect throguh a special link (xgmi). Aldebaran systems will
support this special feature for utilizing the benefits of host-gpu
cache coherence. This change outlines the basic framework for mapping
the GPU VRAM (HBM) to system address space making it accesible to the
host but managed by the amdgpu driver since this region is marked as
reserved memory in host address space by the underlying system firmware.
v2: switch to smuio callback function to check the type
of host-gpu interface (Hawking)
v3: use hub callbacks rather than direct function calls (Alex)
Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Like its predecessors Aldebran also supports advanced high bandwidth
GPU-GPU communication interface known as xgmi. This enables the basic
xgmi support while refactoring the code slightly.
Detection of xgmi link between host cpu and gpu will be introduced in a
different patch.
Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add psp v13 ip block to soc ip init list for aldebaran
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 26 May 2020 07:21:43 +0000 (15:21 +0800)]
drm/amdgpu: bypass gc_9_x_common golden settings
ALDEBARAN doesn't need these golden settings.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 25 May 2020 08:20:35 +0000 (16:20 +0800)]
drm/amdgpu: detect sriov capability for aldebaran
SRIOV pf/vf function identifier regsiter in aldebaran
is the same as the one in arcturus
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 25 May 2020 07:27:18 +0000 (15:27 +0800)]
drm/amdgpu: load pmfw prior to other non-psp fw for aldebaran
PMFW should be loaded before any operation that
may toggling DF-Cstate. otherwsie, tOS has no
choice but to locally toggle DF Cstate (i.e.
disable DF-Cstate even it already enabled by VBIOS)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 25 May 2020 07:08:38 +0000 (15:08 +0800)]
drm/amdgpu: fix incorrect EP_STRAP reg offset for aldebaran
mmRCC_DEV0_EPF0_STRAP0 offset in aldebaran is changed
from arcturus
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add callback function to support trusted os
loading for psp v13
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add sys_drv loading support for psp v13
Add callback function to support sys_drv firmware
loading for psp v13
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 16 Oct 2020 07:50:16 +0000 (15:50 +0800)]
drm/amdgpu: add kdb loading support for psp v13
Add callback function to support key database firmware
loading for psp v13
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Fri, 6 Mar 2020 17:42:21 +0000 (11:42 -0600)]
drm/amdkfd: Add aldebaran trap handler support
Similar to arcturus, but ARCH/ACC VGPRs may now be split unevenly.
A new field in SQ_WAVE_GPR_ALLOC tracks the boundary between the two
sets of VGPRs.
Squash below patches:
drm/amdkfd: Use preprocessor for IP-specific trap handler code
drm/amdkfd: Fix VGPR restore race in gfx8/gfx9 trap handler
drm/amdkfd: Remove duplicated code in gfx9 trap handler
drm/amdkfd: Separate ARCH/ACC VGPR restore in trap handler
drm/amdkfd: Reverse order of ARCH/ACC VGPR restore in trap handler
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 5 Mar 2020 13:33:41 +0000 (21:33 +0800)]
drm/amdgpu: add aldebaran sdma firmware support (v2)
add sdma firmware load support for soc model
v2: drop some emulator leftovers (Alex)
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 07:44:49 +0000 (15:44 +0800)]
drm/amdgpu: set ip blocks for aldebaran
Set ip blocks and asic family id
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 18 Nov 2019 10:14:36 +0000 (18:14 +0800)]
drm/amdgpu: correct mmBIF_SDMA4_DOORBELL_RANGE address for aldebaran
On aldebaran, mmBIF_SDMA4_DOORBELL_RANGE isn't right next to
mmBIF_SDMA3_DOORBELL_RANGE.
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 09:17:10 +0000 (17:17 +0800)]
drm/amdgpu: add sdma block support for aldebaran
Add initial sdma support for aldebaran, and this asic has 5 sdma instances.
v2: remove adundant condition check
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <Evan.Quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 08:52:46 +0000 (16:52 +0800)]
drm/amdgpu: add gfx v9 block support for aldebaran
Add gfx initial support
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 08:16:03 +0000 (16:16 +0800)]
drm/amdgpu: set fw load type for aldebaran
Set backdoor loading way in current phase
v2: change case location to not break other asics
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 07:06:01 +0000 (15:06 +0800)]
drm/amdgpu: add gmc v9 block support for Aldebaran
Add gfx memory controller support
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Sat, 5 Sep 2020 15:15:48 +0000 (23:15 +0800)]
drm/amdgpu: add mmhub support for aldebaran (v3)
v1: dupilcate mmhub_v1_7.c from mmhub_v1_0.c because
mmhub register address for aldebaran is different
from existing asics (Le)
v2: switch to latest mmhub_v9_4_2 register headers (Hawking)
v3: squash in init VM_L2_CNTL3 default value for mmhub v1_7
Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 04:03:24 +0000 (12:03 +0800)]
drm/amdgpu: add soc15 common ip block support for aldebaran
Initialize aldebaran common ip block
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 12 Nov 2019 03:24:01 +0000 (11:24 +0800)]
drm/amdgpu: add gpu_info fw parse support for aldebaran
Parses asic configurations stored in gpu_info firmware and make them available
for driver to use.
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Sat, 5 Sep 2020 14:53:24 +0000 (22:53 +0800)]
drm/amdgpu: add register base init for aldebaran (v2)
v1: add aldebaran_reg_base_init function to initialize
register base for aldebaran (Le)
v2: update VCN HWIP and initialize base offset (James)
Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: add ip offset header for aldebaran (v5)
v1: re-use arct ip base offset array for aldebaran (Le)
v2: create aldebaran ip base offset array for major ip
blocks (Hawking)
v3: re-use arct VCN ip base offset array for aldebaran
(James)
v4: correct MP1 ip base offset array (Hawking)
v5: update VCN ip base offset array to aldebaran one
(Hawking)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 11 Nov 2019 10:01:34 +0000 (18:01 +0800)]
drm/amdgpu: add aldebaran asic type
Add aldebaran in amdgpu_asic_name array and amdgpu_asic_type enum
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 7 Dec 2020 12:37:25 +0000 (20:37 +0800)]
drm/amdgpu: add vcn v2_6_0 ip headers (v3)
v1: Add vcn v2_6_0 register offset and
shift masks in header files (Hawking)
v2: Clean up vcn v2_6_0 registers (Alex)
v3: update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 16 Dec 2020 04:22:14 +0000 (12:22 +0800)]
drm/amdgpu: add umc v6_7_0 ip headers (v3)
v1: Add umc v6_7_0 register offset and shift masks
in header files (Hawking)
v2: Clean up registers (Alex)
v3: update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 7 Dec 2020 12:35:36 +0000 (20:35 +0800)]
drm/amdgpu: add thm v13_0_2 ip headers (v3)
v1: Add thm v13_0_2 register offset and
shift masks in header files (Hawking)
v2: Clean up thm v13_0_2 registers (Alex)
v3: update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 7 Dec 2020 12:42:54 +0000 (20:42 +0800)]
drm/amdgpu: add sdma v4_4_0 ip headers (v2)
Add sdma v4_4_0 register offset and shift
masks in header files
v2: update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>