Stephen Boyd [Wed, 30 Aug 2023 21:39:19 +0000 (14:39 -0700)]
Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next
- Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
- Remove non-OF mmp clk drivers
- Move number of clks from DT headers to drivers
* clk-imx:
clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
clk: imx: pll14xx: align pdiv with reference manual
clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
clk: imx25: make __mx25_clocks_init return void
clk: imx25: print silicon revision during init
dt-bindings: clocks: imx8mp: make sai4 a dummy clock
clk: imx8mp: fix sai4 clock
clk: imx: imx8ulp: update SPLL2 type
clk: imx: pllv4: Fix SPLL2 MULT range
clk: imx: imx8: add audio clock mux driver
dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
clk: imx: clk-gpr-mux: Simplify .determine_rate()
clk: imx: Add 519.75MHz frequency support for imx9 pll
clk: imx93: Add PDM IPG clk
dt-bindings: clock: imx93: Add PDM IPG clk
* clk-samsung:
dt-bindings: clock: samsung: remove define with number of clocks
clk: samsung: exynoautov9: do not define number of clocks in bindings
clk: samsung: exynos850: do not define number of clocks in bindings
clk: samsung: exynos7885: do not define number of clocks in bindings
clk: samsung: exynos5433: do not define number of clocks in bindings
clk: samsung: exynos5420: do not define number of clocks in bindings
clk: samsung: exynos5410: do not define number of clocks in bindings
clk: samsung: exynos5260: do not define number of clocks in bindings
clk: samsung: exynos5250: do not define number of clocks in bindings
clk: samsung: exynos4: do not define number of clocks in bindings
clk: samsung: exynos3250: do not define number of clocks in bindings
* clk-annotate:
clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
clk: Annotate struct clk_hw_onecell_data with __counted_by
* clk-marvell:
clk: pxa910: Move number of clocks to driver source
clk: pxa1928: Move number of clocks to driver source
clk: pxa168: Move number of clocks to driver source
clk: mmp2: Move number of clocks to driver source
clk: mmp: Remove old non-OF clock drivers
* clk-lmk:
clk: lmk04832: Support using PLL1_LD as SPI readback pin
clk: lmk04832: Don't disable vco clock on probe fail
clk: lmk04832: Set missing parent_names for output clocks
Stephen Boyd [Wed, 30 Aug 2023 21:38:19 +0000 (14:38 -0700)]
Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next
- Add Versa3 clk generator to support 48KHz playback/record with audio
codec on RZ/G2L SMARC EVK
- Introduce kstrdup_and_replace() and use it
* clk-versa:
clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
clk: versaclock3: Switch to use i2c_driver's probe callback
clk: Add support for versa3 clock driver
dt-bindings: clock: Add Renesas versa3 clock generator bindings
* clk-strdup:
clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()
clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()
driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace()
lib/string_helpers: Add kstrdup_and_replace() helper
* clk-amlogic: (22 commits)
dt-bindings: soc: amlogic: document System Control registers
dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
clk: meson: axg-audio: move bindings include to main driver
clk: meson: meson8b: move bindings include to main driver
clk: meson: a1: move bindings include to main driver
clk: meson: eeclk: move bindings include to main driver
clk: meson: aoclk: move bindings include to main driver
dt-bindings: clk: axg-audio-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
dt-bindings: clk: meson8b-clkc: expose all clock ids
dt-bindings: clk: g12a-aoclkc: expose all clock ids
dt-bindings: clk: g12a-clks: expose all clock ids
dt-bindings: clk: axg-clkc: expose all clock ids
dt-bindings: clk: gxbb-clkc: expose all clock ids
clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
...
* clk-allwinner:
clk: sunxi-ng: nkm: Prefer current parent rate
clk: sunxi-ng: a64: select closest rate for pll-video0
clk: sunxi-ng: div: Support finding closest rate
clk: sunxi-ng: mux: Support finding closest rate
clk: sunxi-ng: nkm: Support finding closest rate
clk: sunxi-ng: nm: Support finding closest rate
clk: sunxi-ng: Add helper function to find closest rate
clk: sunxi-ng: Add feature to find closest rate
clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
clk: sunxi-ng: nkm: Use correct parameter name for parent HW
clk: sunxi-ng: Modify mismatched function name
clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()
* clk-rockchip:
clk: rockchip: rv1126: Add PD_VO clock tree
clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
clk: rockchip: rk3568: Add PLL rate for 101MHz
Mike Looijmans [Wed, 2 Aug 2023 06:40:59 +0000 (08:40 +0200)]
clk: lmk04832: Don't disable vco clock on probe fail
The probe() method never calls clk_prepare_enable(), so it should not
call clk_disable_unprepare() for the vco.clk in the error path. Fixes
a "lmk-vco already disabled" BUG when probe fails.
Yangtao Li [Wed, 5 Jul 2023 06:53:10 +0000 (14:53 +0800)]
clk: ti: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Kees Cook [Thu, 17 Aug 2023 20:29:42 +0000 (13:29 -0700)]
clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
As found with Coccinelle[1], add __counted_by for struct spmi_pmic_div_clk_cc.
Kees Cook [Thu, 17 Aug 2023 20:30:22 +0000 (13:30 -0700)]
clk: Annotate struct clk_hw_onecell_data with __counted_by
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
As found with Coccinelle[1], add __counted_by for struct clk_hw_onecell_data.
Additionally, since the element count member must be set before accessing
the annotated flexible array member, move its initialization earlier.
Stephen Boyd [Tue, 22 Aug 2023 20:29:15 +0000 (13:29 -0700)]
Merge tag 'qcom-clk-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
- Support for the Global Clock Controller in IPQ5018 is added.
- The SMD RPM driver is cleaned up, with interconnect bus clocks moved
out to the interconnect drivers. Due to being tangled with the
related interconnect updates, the topic branch with interconnect
patches was merged in as well.
- Various bugs in PM runtime integration is fixes across many platforms.
- The MSM8996 core bus framework gains support for MSM8996 Pro.
- MDM9615 is transitioned to parent_hw and parent_data, with related
cleanups. With this the cxo proxy clock is dropped from the driver.
And LCC support for MDM9615 is merged into the MSM8960 driver, to
avoid duplication.
- Network-related resets are added on IPQ4019
- A couple of missing USB-related clocks are added for IPQ9574
- The missing gpll0_sleep_clk_src is added to MSM8917 global clock
controller
- A few minor fixes for MSM8998 global clock controller.
- In the QDU1000 global clock controller GDSCs, clkrefs, and GPLL1 are
added, while PCIe pipe clock, SDCC rcg ops are corrected.
- Missing GDSCs are added to SC8280XP global clock controller driver,
flags for existing GDSCs are corrected, by enabling retention and
dropping the always-on flags. Retention is also enabled for the
display clock controller GDSCs.
- SDCC apps_clk_src is marked CLK_OPS_PARENT_ENABLE to fix issues with
missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while
sm8450 is corrected to use floor ops.
- SM6350 GPU clock controller clock supplies are corrected.
- Unwanted clocks from the IPQ5332 GCC are dropped.
- The missing OXILICX GDSC is added to MSM8226 GCC.
- The delay in the reset controller is transitioned to fsleep() to
invoke the appropriate sleep method depending on duration.
- The SM83550 Video clock controller is extended to support SC8280XP.
* tag 'qcom-clk-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (86 commits)
clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC
clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags
clk: qcom: gcc-ipq5018: change some variable static
clk: qcom: gcc-ipq4019: add missing networking resets
dt-bindings: clock: qcom: ipq4019: add missing networking resets
clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC
dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC
clk: qcom: gcc-qdu1000: Update the RCGs ops
clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
clk: qcom: gcc-qdu1000: Add support for GDSCs
clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
clk: qcom: gcc-qdu1000: Fix clkref clocks handling
clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs
clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
clk: qcom: ipq5332: drop the mem noc clocks
clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks
clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTs
...
Biju Das [Fri, 21 Jul 2023 07:00:19 +0000 (08:00 +0100)]
clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
The device_get_match_data(), is to get match data for firmware interfaces
such as just OF/ACPI. This driver has I2C matching table as well. Use
i2c_get_match_data() to get match data for I2C, ACPI and DT-based
matching.
Biju Das [Fri, 21 Jul 2023 07:00:18 +0000 (08:00 +0100)]
clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
The device_get_match_data(), is to get match data for firmware interfaces
such as just OF/ACPI. This driver has I2C matching table as well. Use
i2c_get_match_data() to get match data for I2C, ACPI and DT-based
matching.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230721070019.96627-2-biju.das.jz@bp.renesas.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 22 Aug 2023 18:13:36 +0000 (11:13 -0700)]
Merge tag 'samsung-clk-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clock drivers changes from Krzysztof Kozlowski:
Remove from the bindings the #defines with number of clocks supported by
each clock controller driver. This number can vary, e.g. when we
implement more clocks in the driver. Having the number in the bindings
prevents changing it. Instead, this should be just a #define inside the
driver.
* tag 'samsung-clk-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
dt-bindings: clock: samsung: remove define with number of clocks
clk: samsung: exynoautov9: do not define number of clocks in bindings
clk: samsung: exynos850: do not define number of clocks in bindings
clk: samsung: exynos7885: do not define number of clocks in bindings
clk: samsung: exynos5433: do not define number of clocks in bindings
clk: samsung: exynos5420: do not define number of clocks in bindings
clk: samsung: exynos5410: do not define number of clocks in bindings
clk: samsung: exynos5260: do not define number of clocks in bindings
clk: samsung: exynos5250: do not define number of clocks in bindings
clk: samsung: exynos4: do not define number of clocks in bindings
clk: samsung: exynos3250: do not define number of clocks in bindings
Stephen Boyd [Tue, 22 Aug 2023 17:58:47 +0000 (10:58 -0700)]
Merge tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Add the PDM IPC clock for i.MX93
- Add 519.75MHz frequency support for i.MX9 PLL
- Simplify the .determine_rate() for GPR mux
- Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource
- Add the audio mux clock to i.MX8
- Fix the SPLL2 MULT range for PLLv4
- Update the SPLL2 type in i.MX8ULP
- Fix the SAI4 clock on i.MX8MP
- Add silicon revision print for i.MX25 on clocks init
- Drop the return value from __mx25_clocks_init
- Fix the clock pauses on no-op set_rate for i.MX8M composite clock
- Drop restrictions for PLL14xx and fix its max prediv value
- Drop the 393216000 and 361267200 from PLL14xx rate table to allow
glitch free switching
* tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
clk: imx: pll14xx: align pdiv with reference manual
clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
clk: imx25: make __mx25_clocks_init return void
clk: imx25: print silicon revision during init
dt-bindings: clocks: imx8mp: make sai4 a dummy clock
clk: imx8mp: fix sai4 clock
clk: imx: imx8ulp: update SPLL2 type
clk: imx: pllv4: Fix SPLL2 MULT range
clk: imx: imx8: add audio clock mux driver
dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
clk: imx: clk-gpr-mux: Simplify .determine_rate()
clk: imx: Add 519.75MHz frequency support for imx9 pll
clk: imx93: Add PDM IPG clk
dt-bindings: clock: imx93: Add PDM IPG clk
Konrad Dybcio [Mon, 31 Jul 2023 12:20:13 +0000 (14:20 +0200)]
clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC
On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must
be always-on as long as the APSS is online and only has to run
at 19.2 MHz. Define it to be as such in the ACTIVE domain.
Some SoCs use that clock for bus scaling, while others just need it for
reaching the hardware. This commit will hurt neither.
Konrad Dybcio [Mon, 31 Jul 2023 12:20:12 +0000 (14:20 +0200)]
clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags
Some clocks, at least PCNoC (a.k.a CNoC_PERIPH) need to be always on,
at least on the ACTIVE side, regardless of whether they're used for bus
scaling or not.
Introduce a new macro to preset non-INT_MAX rates and clk flags to make
it easy and work implicitly through the CCF.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:38 +0000 (10:27 +0200)]
dt-bindings: clock: samsung: remove define with number of clocks
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Remove it entirely from the bindings, once Linux drivers stopped using
them.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:37 +0000 (10:27 +0200)]
clk: samsung: exynoautov9: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:36 +0000 (10:27 +0200)]
clk: samsung: exynos850: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:35 +0000 (10:27 +0200)]
clk: samsung: exynos7885: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:34 +0000 (10:27 +0200)]
clk: samsung: exynos5433: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:33 +0000 (10:27 +0200)]
clk: samsung: exynos5420: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:32 +0000 (10:27 +0200)]
clk: samsung: exynos5410: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:31 +0000 (10:27 +0200)]
clk: samsung: exynos5260: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:30 +0000 (10:27 +0200)]
clk: samsung: exynos5250: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:29 +0000 (10:27 +0200)]
clk: samsung: exynos4: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Krzysztof Kozlowski [Tue, 8 Aug 2023 08:27:28 +0000 (10:27 +0200)]
clk: samsung: exynos3250: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Stephen Boyd [Tue, 15 Aug 2023 00:29:38 +0000 (17:29 -0700)]
Merge tag 'sunxi-clk-for-6.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver changes from Chen-Yu Tsai:
- Parameter name correction for ccu_nkm_round_rate()
- Implement CLK_SET_RATE_PARENT for NKM clocks, i.e. consider alternative
parent rates when determining clock rates
- Set CLK_SET_RATE_PARENT for A64 pll-mipi
- Support finding closest (as opposed to closest but not higher) clock
rate for NM, NKM, mux and div type clocks, as use it for A64
pll-video0
- Prefer current parent rate if able to generate ideal clock rate for
NKM clocks
* tag 'sunxi-clk-for-6.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: nkm: Prefer current parent rate
clk: sunxi-ng: a64: select closest rate for pll-video0
clk: sunxi-ng: div: Support finding closest rate
clk: sunxi-ng: mux: Support finding closest rate
clk: sunxi-ng: nkm: Support finding closest rate
clk: sunxi-ng: nm: Support finding closest rate
clk: sunxi-ng: Add helper function to find closest rate
clk: sunxi-ng: Add feature to find closest rate
clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
clk: sunxi-ng: nkm: Use correct parameter name for parent HW
Ahmad Fatoum [Mon, 7 Aug 2023 08:47:44 +0000 (10:47 +0200)]
clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates"),
the driver has the ability to dynamically compute PLL parameters to
approximate the requested rates. This is not always used, because the
logic is as follows:
- Check if the target rate is hardcoded in the frequency table
- Check if varying only kdiv is possible, so switch over is glitch free
- Compute rate dynamically by iterating over pdiv range
If we skip the frequency table for the 1443x PLL, we find that the
computed values differ to the hardcoded ones. This can be valid if the
hardcoded values guarantee for example an earlier lock-in or if the
divisors are chosen, so that other important rates are more likely to
be reached glitch-free.
For rates (393216000 and 361267200, this doesn't seem to be the case:
They are only approximated by existing parameters (393215995 and 361267196 Hz, respectively) and they aren't reachable glitch-free from
other hardcoded frequencies. Dropping them from the table allows us
to lock-in to these frequencies exactly.
This is immediately noticeable because they are the assigned-clock-rates
for IMX8MN_AUDIO_PLL1 and IMX8MN_AUDIO_PLL2, respectively and a look
into clk_summary so far showed that they were a few Hz short of the target:
Marco Felsch [Mon, 7 Aug 2023 08:47:43 +0000 (10:47 +0200)]
clk: imx: pll14xx: align pdiv with reference manual
The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come
with a 6-bit pre-divider. Neither the reference manuals nor the
datasheets of these SoCs do mention any restrictions. Furthermore the
current code doesn't respect the restrictions from the comment too.
Therefore drop the restriction and align the max pre-divider (pdiv)
value to 63 to get more accurate frequencies.
Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") Cc: stable@vger.kernel.org Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Adam Ford <aford173@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.kernel.org/r/20230807084744.1184791-1-m.felsch@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Ahmad Fatoum [Mon, 7 Aug 2023 08:22:00 +0000 (10:22 +0200)]
clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
Reconfiguring the clock divider to the exact same value is observed
on an i.MX8MN to often cause a longer than usual clock pause, probably
because the divider restarts counting whenever the register is rewritten.
This issue doesn't show up normally, because the clock framework will
take care to not call set_rate when the clock rate is the same.
However, when we reconfigure an upstream clock, the common code will
call set_rate with the newly calculated rate on all children, e.g.:
- sai5 is running normally and divides Audio PLL out by 16.
- Audio PLL rate is increased by 32Hz (glitch-free kdiv change)
- rates for children are recalculated and rates are set recursively
- imx8m_clk_composite_divider_set_rate(sai5) is called with
32/16 = 2Hz more
- imx8m_clk_composite_divider_set_rate computes same divider as before
- divider register is written, so it restarts counting from zero and
MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns.
Some external clock consumers can be upset by such unexpected clock pauses,
so let's make sure we only rewrite the divider value when the value to be
written is actually different.
Martin Kaiser [Wed, 2 Aug 2023 18:40:46 +0000 (20:40 +0200)]
clk: imx25: make __mx25_clocks_init return void
The __mx25_clocks_init function always returns 0 and its only
caller does not check the return value. Let's remove it.
Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230802184046.153394-3-martin@kaiser.cx Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Martin Kaiser [Wed, 2 Aug 2023 18:40:45 +0000 (20:40 +0200)]
clk: imx25: print silicon revision during init
Print the imx25 silicon revision when the clocks are initialised.
Use the same mechanism as for imx27, i.e. call mx25_revision.
This function is unused at the moment.
Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230802184046.153394-2-martin@kaiser.cx Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Marco Felsch [Mon, 31 Jul 2023 14:21:50 +0000 (16:21 +0200)]
dt-bindings: clocks: imx8mp: make sai4 a dummy clock
The hardware don't have a SAI4 instance so remove the define. Use a
comment to keep it as reference and to avoid confusion.
Fixes: 108869144739 ("dt-bindings: imx: Add clock binding doc for i.MX8MP") Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.kernel.org/r/20230731142150.3186650-2-m.felsch@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Marco Felsch [Mon, 31 Jul 2023 14:21:49 +0000 (16:21 +0200)]
clk: imx8mp: fix sai4 clock
The reference manual don't mention a SAI4 hardware block. This would be
clock slice 78 which is skipped (TRM, page 237). Remove any reference to
this clock to align the driver with the reality.
Peng Fan [Sun, 25 Jun 2023 12:33:40 +0000 (20:33 +0800)]
clk: imx: imx8ulp: update SPLL2 type
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. Following the changes to pllv4,
use the new type IMX_PLLV4_IMX8ULP_1GHZ.
Ye Li [Sun, 25 Jun 2023 12:33:39 +0000 (20:33 +0800)]
clk: imx: pllv4: Fix SPLL2 MULT range
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
using a range from 27 to 54, not some fixed values. If using
current PLL implementation, some clock rate can't be supported.
Fix the issue by adding new type for the SPLL2 and use MULT range
to replace MULT table
Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp") Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Shengjiu Wang [Tue, 25 Jul 2023 04:56:24 +0000 (12:56 +0800)]
clk: imx: imx8: add audio clock mux driver
The Audio Clock Mux (ACM) is a collection of control registers
and multiplexers that are used to route the audio source clocks
to the audio peripherals.
Each audio peripheral has its dedicated audio clock mux
(which differ based on usage) and control register.
Shengjiu Wang [Tue, 25 Jul 2023 04:56:23 +0000 (12:56 +0800)]
dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
Add the clock dt-binding file for Audio Clock Mux. which
is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL.
Add the clockid for clocks in header file.
The Audio Clock Mux is binded with all the audio IP and audio clocks
in the subsystem, so need to list the power domain of related clocks
and IPs. Each clock and IP has a power domain, so there are so many
power domains.
This is the parent clock of gpll0_early, so it needs to be enabled
for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC
by adding its existing definition to the clock list.
This clock also doesn't work with clk_alpha_pll_ops, use
clk_branch_simple_ops instead to make it enable and disable correctly.
Imran Shaik [Thu, 3 Aug 2023 10:57:41 +0000 (16:27 +0530)]
clk: qcom: gcc-qdu1000: Update the RCGs ops
The clock RCGs are required to be parked at safe clock source(XO)
during disable as per the hardware expectation and clk_rcg2_shared_ops
are the closest implementation for the same. Hence update the clock
RCG ops to clk_rcg2_shared_ops.
Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's
status bit is not inverted in the latest hardware version of QDU1000
and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well.
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Kathiravan T [Mon, 10 Jul 2023 10:28:07 +0000 (15:58 +0530)]
clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
With the removal of the mem noc clocks in the commit e224dc703521 ("clk:
qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the
gcc_apss_axi_clk_src clock as well, since there are no clocks uses this
clock as a parent.
Kathiravan T [Mon, 10 Jul 2023 10:28:06 +0000 (15:58 +0530)]
clk: qcom: ipq5332: drop the mem noc clocks
Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. So drop these clocks from the GCC driver.
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed
child of MMSS_GPLL0_DIV that's always-on. Properly representing the
former in the GCC driver makes us unable to keep doing so.
Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a
fixed .name link to keep backwards compatibility.
Konrad Dybcio [Mon, 3 Jul 2023 18:20:07 +0000 (20:20 +0200)]
clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properly
Up until now, we've been relying on some non-descript hardware magic
to pinkypromise turn the clocks on for us. While new SoCs shine with
that feature, MSM8998 can not always be fully trusted.
Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual
enable voting.
Stephen Boyd [Wed, 9 Aug 2023 21:17:47 +0000 (14:17 -0700)]
Merge tag 'sunxi-clk-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Jernej Skrabec:
- Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource()
- Fix function name in a comment in ccu_mmc_timing.c
* tag 'sunxi-clk-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Modify mismatched function name
clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()
Stephen Boyd [Wed, 9 Aug 2023 21:09:07 +0000 (14:09 -0700)]
Merge tag 'clk-meson-v6.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- dt-bindings: expose all Amlogic clock ids
- Migrate Amlogic gxbb clock controllers dt-bindings to schema
* tag 'clk-meson-v6.6-1' of https://github.com/BayLibre/clk-meson: (22 commits)
dt-bindings: soc: amlogic: document System Control registers
dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
clk: meson: axg-audio: move bindings include to main driver
clk: meson: meson8b: move bindings include to main driver
clk: meson: a1: move bindings include to main driver
clk: meson: eeclk: move bindings include to main driver
clk: meson: aoclk: move bindings include to main driver
dt-bindings: clk: axg-audio-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
dt-bindings: clk: meson8b-clkc: expose all clock ids
dt-bindings: clk: g12a-aoclkc: expose all clock ids
dt-bindings: clk: g12a-clks: expose all clock ids
dt-bindings: clk: axg-clkc: expose all clock ids
dt-bindings: clk: gxbb-clkc: expose all clock ids
clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
...
Frank Oltmanns [Mon, 7 Aug 2023 12:43:43 +0000 (14:43 +0200)]
clk: sunxi-ng: a64: select closest rate for pll-video0
Selecting the closest rate for pll-video0 instead of the closest rate
that is less than the requested rate has no downside for this clock,
while allowing for selecting a more suitable rate, e.g. for the
connected panels.
Furthermore, the algorithm that sets an NKM clock's parent benefits from
the closest rate. Without it, the NKM clock's rate might drift away from
the requested rate in the multiple successive calls to
ccu_nkm_determine_rate that the clk framework performs when setting a
clock rate.
Therefore, configure pll-video0 and, in consequence, all of its
descendents to select the closest rate.
Frank Oltmanns [Mon, 7 Aug 2023 12:43:42 +0000 (14:43 +0200)]
clk: sunxi-ng: div: Support finding closest rate
Add initalization macros for divisor clocks with mux
(SUNXI_CCU_M_WITH_MUX) to support finding the closest rate. This clock
type requires the appropriate flags to be set in the .common structure
(for the mux part of the clock) and the .div part.
Frank Oltmanns [Mon, 7 Aug 2023 12:43:41 +0000 (14:43 +0200)]
clk: sunxi-ng: mux: Support finding closest rate
When finding the best rate for a mux clock, consider rates that are
higher than the requested rate when CCU_FEATURE_ROUND_CLOSEST is used.
Furthermore, introduce an initialization macro that sets this flag.
Frank Oltmanns [Mon, 7 Aug 2023 12:43:40 +0000 (14:43 +0200)]
clk: sunxi-ng: nkm: Support finding closest rate
When finding the best rate for a NKM clock, consider rates that are
higher than the requested rate, if the CCU_FEATURE_CLOSEST_RATE flag is
set by using the helper function ccu_is_better_rate().
Accommodate ccu_mux_helper_determine_rate to this change.
Frank Oltmanns [Mon, 7 Aug 2023 12:43:39 +0000 (14:43 +0200)]
clk: sunxi-ng: nm: Support finding closest rate
Use the helper function ccu_is_better_rate() to determine the rate that
is closest to the requested rate, thereby supporting rates that are
higher than the requested rate if the clock uses the
CCU_FEATURE_CLOSEST_RATE.
Add the macro SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST which
sets CCU_FEATURE_CLOSEST_RATE.
To avoid code duplication, add the macros
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT that allows selecting
arbitrary features and use it in the original
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX as well as the newly introduced
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST macros.
Frank Oltmanns [Mon, 7 Aug 2023 12:43:38 +0000 (14:43 +0200)]
clk: sunxi-ng: Add helper function to find closest rate
The default behaviour of clocks in the sunxi-ng driver is to select a
clock rate that is closest to but less than the requested rate.
Add the ccu_is_better_rate() helper function that - depending on the
fact if thc CCU_FEATURE_CLOSEST_RATE flag is set - decides if a rate is
closer than another rate.
Frank Oltmanns [Mon, 7 Aug 2023 12:43:35 +0000 (14:43 +0200)]
clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
In case the CLK_SET_RATE_PARENT flag is set, consider using a different
parent rate when determining a new rate.
To find the best match for the requested rate, perform the following
steps for each NKM combination:
- calculate the optimal parent rate,
- find the best parent rate that the parent clock actually supports
- use that parent rate to calculate the effective rate.
In case the clk does not support setting the parent rate, use the same
algorithm as before.
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