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8 weeks agoMerge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk...
Stephen Boyd [Thu, 29 May 2025 07:30:28 +0000 (00:30 -0700)]
Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next

* clk-socfpga:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables

* clk-sophgo:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

* clk-thead:
  clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
  dt-bindings: clock: thead: Add TH1520 VO clock controller

* clk-samsung:
  clk: samsung: correct clock summary for hsi1 block
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: Use samsung CCF common function

8 weeks agoMerge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into...
Stephen Boyd [Thu, 29 May 2025 07:30:17 +0000 (00:30 -0700)]
Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and 'clk-cleanup' into clk-next

* clk-bindings:
  dt-bindings: clock: Drop st,stm32h7-rcc.txt
  dt-bindings: clock: convert bcm2835-aux-clock to yaml
  dt-bindings: clock: Drop maxim,max77686.txt
  dt-bindings: clock: convert vf610-clock.txt to yaml format

* clk-renesas: (26 commits)
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  ...

* clk-spacemit:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

* clk-cleanup:
  clk: test: Forward-declare struct of_phandle_args in kunit/clk.h
  clk: davinci: Use of_get_available_child_by_name()
  clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
  clk: bcm: rpi: Drop module alias
  clk: bcm: kona: Remove unused scaled_div_build

2 months agoMerge tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk...
Stephen Boyd [Thu, 22 May 2025 22:32:50 +0000 (15:32 -0700)]
Merge tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clock driver updates from Krzysztof Kozlowski:

 - Add Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers
 - Fix Samsung ExynosAutov920 HSI1 USBDRD clock parents
 - Minor cleanup for Samsung Exynos4 clk drivers

* tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: correct clock summary for hsi1 block
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: Use samsung CCF common function

2 months agoMerge tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Thu, 22 May 2025 22:26:04 +0000 (15:26 -0700)]
Merge tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
   Renesas RZ/G3E

* tag 'renesas-clk-for-v6.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g047: Add XSPI clock/reset
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
  clk: renesas: Use str_on_off() helper

2 months agoMerge tag 'thead-clk-for-v6.16' of https://github.com/pdp7/linux into clk-thead
Stephen Boyd [Thu, 22 May 2025 22:21:43 +0000 (15:21 -0700)]
Merge tag 'thead-clk-for-v6.16' of https://github.com/pdp7/linux into clk-thead

Pull T-HEAD clk driver updates from Drew Fustini:

 - Clk driver for Video Output (VO) subsystem in the T-HEAD TH1520 SoC

* tag 'thead-clk-for-v6.16' of https://github.com/pdp7/linux:
  clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
  dt-bindings: clock: thead: Add TH1520 VO clock controller

2 months agoMerge tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux into clk...
Stephen Boyd [Thu, 22 May 2025 21:55:12 +0000 (14:55 -0700)]
Merge tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux into clk-sophgo

Pull RISC-V Sophgo clk driver updates from Chen Wang:

 - Replace compatible for Sophgo CV1800 series SoC
 - Add clock support for Sophgo SG2044

* tag 'riscv-sophgo-clk-for-v6.16' of https://github.com/sophgo/linux:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

2 months agoclk: samsung: correct clock summary for hsi1 block
Pritam Manohar Sutar [Tue, 6 May 2025 08:01:54 +0000 (13:31 +0530)]
clk: samsung: correct clock summary for hsi1 block

clk_summary shows wrong value for "mout_hsi1_usbdrd_user".
It shows 400Mhz instead of 40Mhz as below.

dout_shared2_div4           1 1 0 400000000 0 0 50000 Y ...
  mout_hsi1_usbdrd_user     0 0 0 400000000 0 0 50000 Y ...
    dout_clkcmu_hsi1_usbdrd 0 0 0 40000000  0 0 50000 Y ...

Correct the clk_tree by adding correct clock parent for
"mout_hsi1_usbdrd_user".

Post this change, clk_summary shows correct value.

dout_shared2_div4           1 1 0 400000000 0 0 50000 Y ...
  mout_clkcmu_hsi1_usbdrd   0 0 0 400000000 0 0 50000 Y ...
    dout_clkcmu_hsi1_usbdrd 0 0 0 40000000  0 0 50000 Y ...
      mout_hsi1_usbdrd_user 0 0 0 40000000  0 0 50000 Y ...

Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC")
Cc: <stable@kernel.org>
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250506080154.3995512-1-pritam.sutar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agoclk: renesas: r9a09g047: Add XSPI clock/reset
Biju Das [Thu, 24 Apr 2025 08:13:56 +0000 (09:13 +0100)]
clk: renesas: r9a09g047: Add XSPI clock/reset

Add XSPI clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agoclk: renesas: r9a09g047: Add support for xspi mux and divider
Biju Das [Thu, 24 Apr 2025 08:13:55 +0000 (09:13 +0100)]
clk: renesas: r9a09g047: Add support for xspi mux and divider

The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and
pllcm33_xspi divider to select different clock rates. Add support for
both.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agoMerge tag 'renesas-r9a09g047-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Geert Uytterhoeven [Thu, 8 May 2025 18:17:14 +0000 (20:17 +0200)]
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag3' into renesas-clk-for-v6.16

Renesas RZ/G3E XSPI and GBETH Core DT Binding Definitions

XSPI and Gigabit Ethernet PTP reference core clock DT binding
definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and
DT source files.

2 months agodt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
Biju Das [Thu, 24 Apr 2025 08:13:54 +0000 (09:13 +0100)]
dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks

Add definitions for XSPI core clock and Gigabit Ethernet PTP reference
core clocks in the R9A09G047 CPG DT bindings header file.

The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and
factor two as both parent and child share same gating bit.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agoclk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
Michal Wilczynski [Thu, 3 Apr 2025 09:44:24 +0000 (11:44 +0200)]
clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC

The T-Head TH1520 SoC integrates a variety of clocks for its subsystems,
including the Application Processor (AP) and the Video Output (VO) [1].
Up until now, the T-Head clock driver only supported AP clocks.

Extend the driver to provide clock functionality for the VO subsystem.
At this stage, the focus is on implementing the VO clock gates, as these
are currently the most relevant and required components for enabling and
disabling the VO subsystem functionality.  Future enhancements may
introduce additional VO-related clocks as necessary.

Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
2 months agodt-bindings: clock: thead: Add TH1520 VO clock controller
Michal Wilczynski [Thu, 3 Apr 2025 09:44:23 +0000 (11:44 +0200)]
dt-bindings: clock: thead: Add TH1520 VO clock controller

Add device tree bindings for the TH1520 Video Output (VO) subsystem
clock controller. The VO sub-system manages clock gates for multimedia
components including HDMI, MIPI, and GPU.

Document the VIDEO_PLL requirements for the VO clock controller, which
receives its input from the AP clock controller. The VIDEO_PLL is a
Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz
with maximum FOUTVCO of 2376 MHz.

This binding complements the existing AP sub-system clock controller
which manages CPU, DPU, GMAC and TEE PLLs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
2 months agoMerge tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux...
Stephen Boyd [Wed, 7 May 2025 03:51:31 +0000 (20:51 -0700)]
Merge tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into clk-socfpga

Pull SoCFPGA clk driver updates from Dinh Nguyen:

 - Optimize local variables for clocks

* tag 'socfpga_clk_updates_for_6.16_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables

2 months agoclk: sophgo: Add clock controller support for SG2044 SoC
Inochi Amaoto [Fri, 18 Apr 2025 02:03:24 +0000 (10:03 +0800)]
clk: sophgo: Add clock controller support for SG2044 SoC

Add clock driver and clock definition for SG2044 SoC.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250418020325.421257-6-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2 months agoclk: sophgo: Add PLL clock controller support for SG2044 SoC
Inochi Amaoto [Fri, 18 Apr 2025 02:03:23 +0000 (10:03 +0800)]
clk: sophgo: Add PLL clock controller support for SG2044 SoC

Add PLL clock driver and clock definition for SG2044 SoC.

Link: https://lore.kernel.org/r/20250418020325.421257-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2 months agodt-bindings: clock: sophgo: add clock controller for SG2044
Inochi Amaoto [Fri, 18 Apr 2025 02:03:22 +0000 (10:03 +0800)]
dt-bindings: clock: sophgo: add clock controller for SG2044

The clock controller on the SG2044 provides common clock function
for all IPs on the SoC. This device requires PLL clock to function
normally.

Add definition for the clock controller of the SG2044 SoC.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250418020325.421257-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2 months agodt-bindings: soc: sophgo: Add SG2044 top syscon device
Inochi Amaoto [Fri, 18 Apr 2025 02:03:20 +0000 (10:03 +0800)]
dt-bindings: soc: sophgo: Add SG2044 top syscon device

The SG2044 top syscon device provide PLL clock control and some other
misc feature of the SoC.

Add the compatible string for SG2044 top syscon device.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250418020325.421257-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2 months agoclk: sophgo: Add support for newly added precise compatible
Inochi Amaoto [Sun, 4 May 2025 10:45:51 +0000 (18:45 +0800)]
clk: sophgo: Add support for newly added precise compatible

Add of device id definition for newly added precise compatible.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250504104553.1447819-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2 months agodt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC
Inochi Amaoto [Sun, 4 May 2025 10:45:50 +0000 (18:45 +0800)]
dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

As previous binding uses a wildcard compatible for existed clock device
of CV1800 series SoC, it is not suitable for existed requirement. The
only exception is sophgo,sg2000-clk, it does match a real device, so
keep it as is.

Add new precise compatible for existed clock devices of CV1800 series
SoCs and make old wildcard compatible deprecated.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250504104553.1447819-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2 months agoclk: test: Forward-declare struct of_phandle_args in kunit/clk.h
Richard Fitzgerald [Thu, 27 Mar 2025 12:52:14 +0000 (12:52 +0000)]
clk: test: Forward-declare struct of_phandle_args in kunit/clk.h

Add a forward-declare of struct of_phandle_args to prevent the compiler
warning:

../include/kunit/clk.h:29:63: warning: ‘struct of_phandle_args’ declared
inside parameter list will not be visible outside of this definition or
declaration
   struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data),

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20250327125214.82598-1-rf@opensource.cirrus.com
Fixes: a82fcb16d977 ("clk: test: Add test managed of_clk_add_hw_provider()")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agoclk: davinci: Use of_get_available_child_by_name()
Biju Das [Thu, 10 Apr 2025 06:20:38 +0000 (07:20 +0100)]
clk: davinci: Use of_get_available_child_by_name()

Simplify of_davinci_pll_init() by using of_get_available_child_by_name().

While at it, move of_node_put(child) inside the if block to avoid
additional check if of_child is NULL.

Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250410062040.6346-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agoclk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
Henry Martin [Wed, 2 Apr 2025 02:05:13 +0000 (10:05 +0800)]
clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()

devm_kasprintf() returns NULL when memory allocation fails. Currently,
raspberrypi_clk_register() does not check for this case, which results
in a NULL pointer dereference.

Add NULL check after devm_kasprintf() to prevent this issue.

Fixes: 93d2725affd6 ("clk: bcm: rpi: Discover the firmware clocks")
Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250402020513.42628-1-bsdhenrymartin@gmail.com
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agoclk: bcm: rpi: Drop module alias
Stefan Wahren [Tue, 15 Apr 2025 18:56:14 +0000 (20:56 +0200)]
clk: bcm: rpi: Drop module alias

Since commit fbac2e7787ac ("clk: bcm: rpi: Allow the driver to
be probed by DT") the module alias isn't necessary anymore. So
we can drop it.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20250415185614.16292-1-wahrenst@gmx.net
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agoclk: bcm: kona: Remove unused scaled_div_build
Dr. David Alan Gilbert [Mon, 5 May 2025 01:35:45 +0000 (02:35 +0100)]
clk: bcm: kona: Remove unused scaled_div_build

scaled_div_build() was added in 2014 by
commit 1f27f15258bf ("clk: bcm281xx: add initial clock framework support")
but hasn't been used.

Remove it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Link: https://lore.kernel.org/r/20250505013545.359745-1-linux@treblig.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agodt-bindings: clock: Drop st,stm32h7-rcc.txt
Rob Herring (Arm) [Mon, 5 May 2025 16:19:32 +0000 (11:19 -0500)]
dt-bindings: clock: Drop st,stm32h7-rcc.txt

The binding is already covered by st,stm32-rcc.yaml.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250505161933.1432791-1-robh@kernel.org
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agodt-bindings: clock: convert bcm2835-aux-clock to yaml
Stefan Wahren [Sat, 3 May 2025 08:09:49 +0000 (10:09 +0200)]
dt-bindings: clock: convert bcm2835-aux-clock to yaml

Convert the DT binding document for BCM2835 auxiliary peripheral clock
from .txt to YAML.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20250503080949.3945-1-wahrenst@gmx.net
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[sboyd@kernel.org: Drop aux label]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agodt-bindings: clock: Drop maxim,max77686.txt
Rob Herring (Arm) [Mon, 5 May 2025 16:19:42 +0000 (11:19 -0500)]
dt-bindings: clock: Drop maxim,max77686.txt

The clock binding for Maxim MAX77686/MAX77802/MAX77620 is already
covered by mfd/maxim,max77686.yaml.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250505161943.1433081-1-robh@kernel.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agoMerge tag 'spacemit-clk-for-6.16-1' of https://github.com/spacemit-com/linux into...
Stephen Boyd [Tue, 6 May 2025 17:56:52 +0000 (10:56 -0700)]
Merge tag 'spacemit-clk-for-6.16-1' of https://github.com/spacemit-com/linux into clk-spacemit

Pull SpacemiT clk driver updates from Yixun Lan:

 - Add clock driver for SpacemiT K1 SoC
 - Add TWSI8 clock, workaround the read quirk

* tag 'spacemit-clk-for-6.16-1' of https://github.com/spacemit-com/linux:
  clk: spacemit: k1: Add TWSI8 bus and function clocks
  clk: spacemit: Add clock support for SpacemiT K1 SoC
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

2 months agoMerge tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Tue, 6 May 2025 17:52:40 +0000 (10:52 -0700)]
Merge tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add GPU and USB2 clocks and resets on Renesas RZ/V2H(P)
 - Add support for the Renesas RZ/V2N (R9A09G056) SoC
 - Add GPU clocks and resets on Renesas RZ/G3E

* tag 'renesas-clk-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits)
  clk: renesas: r9a09g057: Add clock and reset entries for USB2
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
  clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
  clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
  clk: renesas: rzv2h: Support static dividers without RMW
  clk: renesas: rzv2h: Add macro for defining static dividers
  clk: renesas: rzv2h: Add support for static mux clocks
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Fix a typo
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  clk: renesas: rzv2h: Sort compatible list based on SoC part number
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
  clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
  clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()
  clk: renesas: r9a09g057: Add clock and reset entries for GE3D
  clk: renesas: rzv2h: Rename PLL field macros for consistency
  clk: renesas: rzv2h: Add support for enabling PLLs
  ...

2 months agoclk: renesas: Use str_on_off() helper
Geert Uytterhoeven [Mon, 28 Apr 2025 11:45:55 +0000 (13:45 +0200)]
clk: renesas: Use str_on_off() helper

Use the str_on_off() helper instead of open-coding the same operation.
Note that this does change the case of the flags, which doesn't matter
much for debug messages.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/622f8554dcb815c8fc73511a1a118c1724570fa9.1745840497.git.geert+renesas@glider.be
2 months agoclk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
Shin Son [Mon, 28 Apr 2025 11:35:16 +0000 (20:35 +0900)]
clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition

The CLKS_NR_CPUCL0 macro was incorrectly defined based on a wrong clock ID.
It mistakenly referenced CLK_DOUT_CLUSTER0_PERIPHCLK, which corresponds to
a cluster peripheral clock, not the last clock ID for CPUCL0 as intended.

This patch corrects the definition to use CLK_DOUT_CPUCL0_NOCP + 1,
properly matching the last clock ID for CPUCL0 as intended.

This error was due to confusion with the hardware diagram, and this patch
ensures that the number of clocks for CPUCL0 is correctly defined.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250428113517.426987-4-shin.son@samsung.com
Fixes: 59636ec89c2c ("clk: samsung: exynosautov920: add cpucl0 clock support")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agoclk: samsung: exynosautov920: add cpucl1/2 clock support
Shin Son [Mon, 28 Apr 2025 11:35:15 +0000 (20:35 +0900)]
clk: samsung: exynosautov920: add cpucl1/2 clock support

Register compatible and cmu_info data to support clock CPUCL1/2
(CPU Cluster 1 and CPU Cluster 2),
these provide clock for CPUCL1/2_SWTICH/CLUSTER.

These clocks are required early during boot for the CPUs,
so they are declared using CLK_OF_DECLARE instead of being registered
through a platform driver.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250428113517.426987-3-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agoMerge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk
Krzysztof Kozlowski [Wed, 30 Apr 2025 07:25:13 +0000 (09:25 +0200)]
Merge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk

2 months agodt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
Shin Son [Mon, 28 Apr 2025 11:35:14 +0000 (20:35 +0900)]
dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions

Add cpucl1 and cpucl2 clock definitions.

CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2,
which provide clock support for the CPUs on Exynosauto V920 SoC.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250428113517.426987-2-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agodt-bindings: clock: convert vf610-clock.txt to yaml format
Frank Li [Fri, 11 Apr 2025 21:23:38 +0000 (17:23 -0400)]
dt-bindings: clock: convert vf610-clock.txt to yaml format

Convert vf610-clock.txt to yaml format.

Additional changes:
- swap audio_ext and enet_ext to match existed dts order
- remove clock consumer in example

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250411212339.3273202-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2 months agoclk: samsung: exynosautov920: add cpucl0 clock support
Shin Son [Wed, 23 Apr 2025 04:41:52 +0000 (13:41 +0900)]
clk: samsung: exynosautov920: add cpucl0 clock support

Register compatible and cmu_info data to support clock CPUCL0(CPU
Cluster 0), this provides clock for CPUCL0_SWTICH/DBG/CLUSTER.  These
clocks are required early during boot for the CPUs, so they are declared
using CLK_OF_DECLARE instead of being registered through a platform
driver.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250423044153.1288077-3-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agoMerge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk
Krzysztof Kozlowski [Sun, 27 Apr 2025 19:21:53 +0000 (21:21 +0200)]
Merge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk

2 months agodt-bindings: clock: exynosautov920: add cpucl0 clock definitions
Shin Son [Wed, 23 Apr 2025 04:41:51 +0000 (13:41 +0900)]
dt-bindings: clock: exynosautov920: add cpucl0 clock definitions

Add cpucl0 clock definitions.

CPUCL0 refers to CPU Cluster 0, which provide clock support
for the CPUs on Exynosauto V920 SoC.

Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250423044153.1288077-2-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agoclk: socfpga: stratix10: Optimize local variables
Thorsten Blum [Wed, 19 Feb 2025 10:44:35 +0000 (11:44 +0100)]
clk: socfpga: stratix10: Optimize local variables

Since readl() returns a u32, the local variable reg can also have the
data type u32. Furthermore, mdiv and refdiv are derived from reg and can
also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of refdiv to u32 removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
3 months agoclk: socfpga: clk-pll: Optimize local variables
Thorsten Blum [Wed, 19 Feb 2025 10:42:25 +0000 (11:42 +0100)]
clk: socfpga: clk-pll: Optimize local variables

Since readl() returns a u32, the local variables reg and bypass can also
have the data type u32. Furthermore, divf and divq are derived from reg
and can also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
3 months agoclk: renesas: r9a09g057: Add clock and reset entries for USB2
Lad Prabhakar [Mon, 7 Apr 2025 16:52:01 +0000 (17:52 +0100)]
clk: renesas: r9a09g057: Add clock and reset entries for USB2

Add clock and reset entries for USB2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoMerge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Geert Uytterhoeven [Tue, 22 Apr 2025 09:37:21 +0000 (11:37 +0200)]
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16

Renesas RZ/V2H USB2 and GBETH Clock DT Binding Definitions

USB2 and Gigabit Ethernet clock DT binding definitions for the Renesas
RZ/V2H (R9A09G057) SoC, shared by driver and DT source files.

3 months agodt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
Lad Prabhakar [Mon, 7 Apr 2025 16:52:00 +0000 (17:52 +0100)]
dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks

Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP
reference core clocks in the R9A09G057 CPG DT bindings header file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
Lad Prabhakar [Mon, 7 Apr 2025 16:51:58 +0000 (17:51 +0100)]
clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation

Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used
to confirm the clock state.

According to the manual, enabling a clock requires setting the
CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON
bit.  Similarly, disabling a clock requires clearing the CPG_CLK_ON bit
and confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
Lad Prabhakar [Mon, 7 Apr 2025 16:51:57 +0000 (17:51 +0100)]
clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()

Replace hard-coded "ON"/"OFF" strings with the `str_on_off()` helper in
`rzv2h_mod_clock_endisable()`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Support static dividers without RMW
Biju Das [Mon, 7 Apr 2025 16:51:56 +0000 (17:51 +0100)]
clk: renesas: rzv2h: Support static dividers without RMW

Add support for static dividers that do not require read-modify-write
(RMW) operations.  This enables the use of the generic clk_divider_ops
instead of the custom RMW-based implementation.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Add macro for defining static dividers
Lad Prabhakar [Mon, 7 Apr 2025 16:51:55 +0000 (17:51 +0100)]
clk: renesas: rzv2h: Add macro for defining static dividers

Unlike dynamic dividers, static dividers do not have a monitor bit.
Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring
consistency with existing dynamic divider macros.

Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence
of a monitor bit, allowing the monitoring step to be skipped when `mon`
is set to `CSDIV_NO_MON`.

Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic
`clk_hw_register_divider_table()` for registering satic dividers as some
of the static dividers require RMW operations.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Add support for static mux clocks
Lad Prabhakar [Mon, 7 Apr 2025 16:51:54 +0000 (17:51 +0100)]
clk: renesas: rzv2h: Add support for static mux clocks

Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the
Renesas RZ/V2H(P) SoC.  Extend `cpg_core_clk` to include parent names,
mux flags, and a new `smuxed` struct.  Update clock registration to
handle static mux clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: r9a09g047: Add clock and reset entries for GE3D
Tommaso Merciai [Wed, 2 Apr 2025 13:11:38 +0000 (15:11 +0200)]
clk: renesas: r9a09g047: Add clock and reset entries for GE3D

Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
GE3D.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250402131142.1270701-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Fix a typo
Biju Das [Thu, 20 Mar 2025 09:31:01 +0000 (09:31 +0000)]
clk: renesas: rzv2h: Fix a typo

Fix a typo montor->monitor in kernel-doc comment.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250320093107.36784-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: spacemit: k1: Add TWSI8 bus and function clocks
Haylen Chu [Wed, 16 Apr 2025 13:54:04 +0000 (13:54 +0000)]
clk: spacemit: k1: Add TWSI8 bus and function clocks

The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux
selection bits, reset assertion bit and enable bits for function and bus
clocks. It has a quirk that reading always results in zero.

As a workaround, let's hardcode the mux value as zero to select
pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask
is combined from the real bus and function clocks to avoid the
write-only register being shared between two clk_hws, in which case
updates of one clk_hw zero the other's bits.

With a 1:1 factor serving as placeholder for the bus clock, the I2C-8
controller could be brought up, which is essential for boards attaching
power-management chips to it.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-5-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
3 months agoclk: spacemit: Add clock support for SpacemiT K1 SoC
Haylen Chu [Wed, 16 Apr 2025 13:54:03 +0000 (13:54 +0000)]
clk: spacemit: Add clock support for SpacemiT K1 SoC

The clock tree of K1 SoC contains three main types of clock hardware
(PLL/DDN/MIX) and has control registers split into several multifunction
devices: APBS (PLLs), MPMU, APBC and APMU.

All register operations are done through regmap to ensure atomicity
between concurrent operations of clock driver and reset,
power-domain driver that will be introduced in the future.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
3 months agodt-bindings: clock: spacemit: Add spacemit,k1-pll
Haylen Chu [Wed, 16 Apr 2025 13:54:02 +0000 (13:54 +0000)]
dt-bindings: clock: spacemit: Add spacemit,k1-pll

Add definition for the PLL found on SpacemiT K1 SoC, which takes the
external 24MHz oscillator as input and generates clocks in various
frequencies for the system.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-3-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
3 months agodt-bindings: soc: spacemit: Add spacemit,k1-syscon
Haylen Chu [Wed, 16 Apr 2025 13:54:01 +0000 (13:54 +0000)]
dt-bindings: soc: spacemit: Add spacemit,k1-syscon

Document APMU, MPMU and APBC syscons found on SpacemiT K1 SoC, which are
capable of generating clock and reset signals. Additionally, APMU and MPMU
manage power domains.

Signed-off-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-2-heylenay@4d2.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
3 months agoclk: samsung: Use samsung CCF common function
Varada Pavani [Fri, 7 Mar 2025 09:24:03 +0000 (14:54 +0530)]
clk: samsung: Use samsung CCF common function

Use samsung CCF function which registers multiple clock providers using
single function call samsung_cmu_register_clocks().

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Link: https://lore.kernel.org/r/20250307092403.19742-1-v.pavani@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agoclk: renesas: rzv2h: Add support for RZ/V2N SoC
Lad Prabhakar [Mon, 7 Apr 2025 19:16:24 +0000 (20:16 +0100)]
clk: renesas: rzv2h: Add support for RZ/V2N SoC

The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC
with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present
only on the RZ/V2H(P) SoC.

Add minimal clock and reset entries required to boot the Renesas
RZ/V2N EVK and binds it with the RZ/V2H CPG family driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoMerge tag 'renesas-r9a09g056-dt-binding-defs-tag1' into renesas-clk-for-v6.16
Geert Uytterhoeven [Mon, 14 Apr 2025 08:56:36 +0000 (10:56 +0200)]
Merge tag 'renesas-r9a09g056-dt-binding-defs-tag1' into renesas-clk-for-v6.16

Renesas RZ/V2N DT Bindings and Definitions

DT bindings and binding definitions for the Renesas RZ/V2N (R9A09G056)
SoC, shared by driver and DT source files.

3 months agoclk: renesas: rzv2h: Sort compatible list based on SoC part number
Lad Prabhakar [Mon, 7 Apr 2025 19:16:23 +0000 (20:16 +0100)]
clk: renesas: rzv2h: Sort compatible list based on SoC part number

Reorder the compatible entries in `rzv2h_cpg_match[]` to follow a
numerical sequence based on the SoC part numbers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agodt-bindings: pinctrl: renesas: Document RZ/V2N SoC
Lad Prabhakar [Mon, 7 Apr 2025 19:16:25 +0000 (20:16 +0100)]
dt-bindings: pinctrl: renesas: Document RZ/V2N SoC

Add documentation for the pin controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family
and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC
has an additional dedicated pin.

To account for this, a SoC-specific compatible string,
'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agodt-bindings: clock: renesas: Document RZ/V2N SoC CPG
Lad Prabhakar [Mon, 7 Apr 2025 19:16:22 +0000 (20:16 +0100)]
dt-bindings: clock: renesas: Document RZ/V2N SoC CPG

Document the device tree bindings for the Renesas RZ/V2N (R9A09G056)
SoC Clock Pulse Generator (CPG).

Update `renesas,rzv2h-cpg.yaml` to include the compatible string for
RZ/V2N SoC and adjust the title and description accordingly.

Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock
constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific
clock driver will be reused for this SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agodt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
Lad Prabhakar [Mon, 7 Apr 2025 19:16:19 +0000 (20:16 +0100)]
dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC

Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System
Controller (SYS) binding, as both IPs are very similar.

However, they have different SoC IDs, and the RZ/V2N does not have
PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle
these differences, introduce a new compatible string
`renesas,r9a09g056-sys`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agodt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
Lad Prabhakar [Mon, 7 Apr 2025 19:16:17 +0000 (20:16 +0100)]
dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK

Document the Renesas RZ/V2N (R9A09G056) SoC variants, distinguishing
between configurations with and without specific hardware features such
as GPU, ISP, and cryptographic extensions. Also, document the
"renesas,rzv2n-evk" compatible string for the RZ/V2N EVK board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
Tommaso Merciai [Mon, 17 Mar 2025 08:32:11 +0000 (09:32 +0100)]
clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()

rzv2h_cpg_assert() and rzv2h_cpg_deassert() functions are similar. Share
this code via __rzv2h_cpg_assert(). This avoid code duplication.

Reported-by: Pavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/cip-dev/Z9QA9rwuXCuVbOXp@duo.ucw.cz/
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250317083213.371614-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()
Tommaso Merciai [Mon, 17 Mar 2025 08:32:10 +0000 (09:32 +0100)]
clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()

Remove duplicate code into rzv2h_ddiv_set_rate().

Reported-by: Pavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/cip-dev/Z9QBZo4GgtMjid0v@duo.ucw.cz/
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250317083213.371614-3-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: r9a09g057: Add clock and reset entries for GE3D
Lad Prabhakar [Sun, 9 Mar 2025 21:14:02 +0000 (21:14 +0000)]
clk: renesas: r9a09g057: Add clock and reset entries for GE3D

Add PLLGPU along with the necessary clock and reset entries for GE3D.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Rename PLL field macros for consistency
Lad Prabhakar [Sun, 9 Mar 2025 21:14:01 +0000 (21:14 +0000)]
clk: renesas: rzv2h: Rename PLL field macros for consistency

Rename PLL field extraction macros to include the associated register name
(`CPG_PLL_CLK1` or `CPG_PLL_CLK2`) to maintain consistency with other PLL
register macros. Update all corresponding macro references accordingly.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Add support for enabling PLLs
Lad Prabhakar [Sun, 9 Mar 2025 21:14:00 +0000 (21:14 +0000)]
clk: renesas: rzv2h: Add support for enabling PLLs

Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being
disabled by default in TF-A. Add support for enabling PLL clocks in the
RZ/V2H(P) CPG driver to manage this.

Introduce `is_enabled` and `enable` callbacks to handle PLL state
transitions. With the `enable` callback, PLLGPU will be turned ON only
when the GPU node is enabled; otherwise, it will remain off. Define new
macros for PLL standby and monitor registers to facilitate this process.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`
Lad Prabhakar [Sun, 9 Mar 2025 21:13:59 +0000 (21:13 +0000)]
clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`

Remove the redundant `type` field from `struct pll_clk`, as it is not used
in the PLL clock handling logic.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoclk: renesas: rzv2h: Refactor PLL configuration handling
Lad Prabhakar [Sun, 9 Mar 2025 21:13:58 +0000 (21:13 +0000)]
clk: renesas: rzv2h: Refactor PLL configuration handling

Refactor PLL handling by introducing a `struct pll` to encapsulate PLL
configuration parameters, ensuring consistency with the existing dynamic
divider structure.

Introduce the `PLL_PACK()` macro to simplify PLL structure initialization
and update the `DEF_PLL()` macro to use the new `pll` structure. Modify
relevant clock register functions to utilize the structured PLL data
instead of raw configuration values.

This refactoring improves code readability, maintainability, and
alignment with the existing clock configuration approach.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoLinux 6.15-rc1
Linus Torvalds [Sun, 6 Apr 2025 20:11:33 +0000 (13:11 -0700)]
Linux 6.15-rc1

3 months agotools/include: make uapi/linux/types.h usable from assembly
Thomas Weißschuh [Wed, 2 Apr 2025 20:21:57 +0000 (21:21 +0100)]
tools/include: make uapi/linux/types.h usable from assembly

The "real" linux/types.h UAPI header gracefully degrades to a NOOP when
included from assembly code.

Mirror this behaviour in the tools/ variant.

Test for __ASSEMBLER__ over __ASSEMBLY__ as the former is provided by the
toolchain automatically.

Reported-by: Mark Brown <broonie@kernel.org>
Closes: https://lore.kernel.org/lkml/af553c62-ca2f-4956-932c-dd6e3a126f58@sirena.org.uk/
Fixes: c9fbaa879508 ("selftests: vDSO: parse_vdso: Use UAPI headers instead of libc headers")
Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de>
Link: https://patch.msgid.link/20250321-uapi-consistency-v1-1-439070118dc0@linutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoMerge tag 'turbostat-2025.05.06' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 6 Apr 2025 19:32:43 +0000 (12:32 -0700)]
Merge tag 'turbostat-2025.05.06' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull turbostat updates from Len Brown:

 - support up to 8192 processors

 - add cpuidle governor debug telemetry, disabled by default

 - update default output to exclude cpuidle invocation counts

 - bug fixes

* tag 'turbostat-2025.05.06' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power turbostat: v2025.05.06
  tools/power turbostat: disable "cpuidle" invocation counters, by default
  tools/power turbostat: re-factor sysfs code
  tools/power turbostat: Restore GFX sysfs fflush() call
  tools/power turbostat: Document GNR UncMHz domain convention
  tools/power turbostat: report CoreThr per measurement interval
  tools/power turbostat: Increase CPU_SUBSET_MAXCPUS to 8192
  tools/power turbostat: Add idle governor statistics reporting
  tools/power turbostat: Fix names matching
  tools/power turbostat: Allow Zero return value for some RAPL registers
  tools/power turbostat: Clustered Uncore MHz counters should honor show/hide options

3 months agoMerge tag 'soundwire-6.15-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 6 Apr 2025 19:04:53 +0000 (12:04 -0700)]
Merge tag 'soundwire-6.15-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire

Pull soundwire fix from Vinod Koul:

 - add missing config symbol CONFIG_SND_HDA_EXT_CORE required for asoc
   driver CONFIG_SND_SOF_SOF_HDA_SDW_BPT

* tag 'soundwire-6.15-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire:
  ASoC: SOF: Intel: Let SND_SOF_SOF_HDA_SDW_BPT select SND_HDA_EXT_CORE

3 months agotools/power turbostat: v2025.05.06
Len Brown [Sun, 6 Apr 2025 18:49:20 +0000 (14:49 -0400)]
tools/power turbostat: v2025.05.06

Support up to 8192 processors
Add cpuidle governor debug telemetry, disabled by default
Update default output to exclude cpuidle invocation counts
Bug fixes

Signed-off-by: Len Brown <len.brown@intel.com>
3 months agotools/power turbostat: disable "cpuidle" invocation counters, by default
Len Brown [Sun, 6 Apr 2025 18:29:57 +0000 (14:29 -0400)]
tools/power turbostat: disable "cpuidle" invocation counters, by default

Create "pct_idle" counter group, the sofware notion of residency
so it can now be singled out, independent of other counter groups.

Create "cpuidle" group, the cpuidle invocation counts.
Disable "cpuidle", by default.

Create "swidle" = "cpuidle" + "pct_idle".
Undocument "sysfs", the old name for "swidle", but keep it working
for backwards compatibilty.

Create "hwidle", all the HW idle counters

Modify "idle", enabled by default
"idle" = "hwidle" + "pct_idle" (and now excludes "cpuidle")

Signed-off-by: Len Brown <len.brown@intel.com>
3 months agoMerge tag 'perf-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 6 Apr 2025 17:48:12 +0000 (10:48 -0700)]
Merge tag 'perf-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf event fix from Ingo Molnar:
 "Fix a perf events time accounting bug"

* tag 'perf-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/core: Fix child_total_time_enabled accounting bug at task exit

3 months agoMerge tag 'sched-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 6 Apr 2025 17:44:58 +0000 (10:44 -0700)]
Merge tag 'sched-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull scheduler fixes from Ingo Molnar:

 - Fix a nonsensical Kconfig combination

 - Remove an unnecessary rseq-notification

* tag 'sched-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  rseq: Eliminate useless task_work on execve
  sched/isolation: Make CONFIG_CPU_ISOLATION depend on CONFIG_SMP

3 months agoDisable SLUB_TINY for build testing
Linus Torvalds [Sun, 6 Apr 2025 17:00:04 +0000 (10:00 -0700)]
Disable SLUB_TINY for build testing

... and don't error out so hard on missing module descriptions.

Before commit 6c6c1fc09de3 ("modpost: require a MODULE_DESCRIPTION()")
we used to warn about missing module descriptions, but only when
building with extra warnigns (ie 'W=1').

After that commit the warning became an unconditional hard error.

And it turns out not all modules have been converted despite the claims
to the contrary.  As reported by Damian Tometzki, the slub KUnit test
didn't have a module description, and apparently nobody ever really
noticed.

The reason nobody noticed seems to be that the slub KUnit tests get
disabled by SLUB_TINY, which also ends up disabling a lot of other code,
both in tests and in slub itself.  And so anybody doing full build tests
didn't actually see this failre.

So let's disable SLUB_TINY for build-only tests, since it clearly ends
up limiting build coverage.  Also turn the missing module descriptions
error back into a warning, but let's keep it around for non-'W=1'
builds.

Reported-by: Damian Tometzki <damian@riscv-rocks.de>
Link: https://lore.kernel.org/all/01070196099fd059-e8463438-7b1b-4ec8-816d-173874be9966-000000@eu-central-1.amazonses.com/
Cc: Masahiro Yamada <masahiroy@kernel.org>
Cc: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
Fixes: 6c6c1fc09de3 ("modpost: require a MODULE_DESCRIPTION()")
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agotools/power turbostat: re-factor sysfs code
Len Brown [Sun, 6 Apr 2025 16:53:18 +0000 (12:53 -0400)]
tools/power turbostat: re-factor sysfs code

Probe cpuidle "sysfs" residency and counts separately,
since soon we will make one disabled on, and the
other disabled off.

Clarify that some BIC (build-in-counters) are actually "groups".
since we're about to re-name some of those groups.

no functional change.

Signed-off-by: Len Brown <len.brown@intel.com>
3 months agotools/power turbostat: Restore GFX sysfs fflush() call
Zhang Rui [Wed, 19 Mar 2025 00:53:07 +0000 (08:53 +0800)]
tools/power turbostat: Restore GFX sysfs fflush() call

Do fflush() to discard the buffered data, before each read of the
graphics sysfs knobs.

Fixes: ba99a4fc8c24 ("tools/power turbostat: Remove unnecessary fflush() call")
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
3 months agotools/power turbostat: Document GNR UncMHz domain convention
Len Brown [Sun, 6 Apr 2025 16:23:22 +0000 (12:23 -0400)]
tools/power turbostat: Document GNR UncMHz domain convention

Document that on Intel Granite Rapids Systems,
Uncore domains 0-2 are CPU domains, and
uncore domains 3-4 are IO domains.

Signed-off-by: Len Brown <len.brown@intel.com>
3 months agotools/power turbostat: report CoreThr per measurement interval
Len Brown [Sun, 6 Apr 2025 15:18:39 +0000 (11:18 -0400)]
tools/power turbostat: report CoreThr per measurement interval

The CoreThr column displays total thermal throttling events
since boot time.

Change it to report events during the measurement interval.

This is more useful for showing a user the current conditions.
Total events since boot time are still available to the user via
/sys/devices/system/cpu/cpu*/thermal_throttle/*

Document CoreThr on turbostat.8

Fixes: eae97e053fe30 ("turbostat: Support thermal throttle count print")
Reported-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Cc: Chen Yu <yu.c.chen@intel.com>
3 months agotools/power turbostat: Increase CPU_SUBSET_MAXCPUS to 8192
Justin Ernst [Wed, 19 Mar 2025 20:27:31 +0000 (15:27 -0500)]
tools/power turbostat: Increase CPU_SUBSET_MAXCPUS to 8192

On systems with >= 1024 cpus (in my case 1152), turbostat fails with the error output:
"turbostat: /sys/fs/cgroup/cpuset.cpus.effective: cpu str malformat 0-1151"

A similar error appears with the use of turbostat --cpu when the inputted cpu
range contains a cpu number >= 1024:
# turbostat -c 1100-1151
"--cpu 1100-1151" malformed
...

Both errors are caused by parse_cpu_str() reaching its limit of CPU_SUBSET_MAXCPUS.

It's a good idea to limit the maximum cpu number being parsed, but 1024 is too low.
For a small increase in compute and allocated memory, increasing CPU_SUBSET_MAXCPUS
brings support for parsing cpu numbers >= 1024.

Increase CPU_SUBSET_MAXCPUS to 8192, a common setting for CONFIG_NR_CPUS on x86_64.

Signed-off-by: Justin Ernst <justin.ernst@hpe.com>
Signed-off-by: Len Brown <len.brown@intel.com>
3 months agoMerge tag 'timers-cleanups-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 6 Apr 2025 15:35:37 +0000 (08:35 -0700)]
Merge tag 'timers-cleanups-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer cleanups from Thomas Gleixner:
 "A set of final cleanups for the timer subsystem:

   - Convert all del_timer[_sync]() instances over to the new
     timer_delete[_sync]() API and remove the legacy wrappers.

     Conversion was done with coccinelle plus some manual fixups as
     coccinelle chokes on scoped_guard().

   - The final cleanup of the hrtimer_init() to hrtimer_setup()
     conversion.

     This has been delayed to the end of the merge window, so that all
     patches which have been merged through other trees are in mainline
     and all new users are catched.

  Doing this right before rc1 ensures that new code which is merged post
  rc1 is not introducing new instances of the original functionality"

* tag 'timers-cleanups-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  tracing/timers: Rename the hrtimer_init event to hrtimer_setup
  hrtimers: Rename debug_init_on_stack() to debug_setup_on_stack()
  hrtimers: Rename debug_init() to debug_setup()
  hrtimers: Rename __hrtimer_init_sleeper() to __hrtimer_setup_sleeper()
  hrtimers: Remove unnecessary NULL check in hrtimer_start_range_ns()
  hrtimers: Make callback function pointer private
  hrtimers: Merge __hrtimer_init() into __hrtimer_setup()
  hrtimers: Switch to use __htimer_setup()
  hrtimers: Delete hrtimer_init()
  treewide: Convert new and leftover hrtimer_init() users
  treewide: Switch/rename to timer_delete[_sync]()

3 months agoMerge tag 'irq-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 6 Apr 2025 15:17:43 +0000 (08:17 -0700)]
Merge tag 'irq-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull more irq updates from Thomas Gleixner:
 "A set of updates for the interrupt subsystem:

   - A treewide cleanup for the irq_domain code, which makes the naming
     consistent and gets rid of the original oddity of naming domains
     'host'.

     This is a trivial mechanical change and is done late to ensure that
     all instances have been catched and new code merged post rc1 wont
     reintroduce new instances.

   - A trivial consistency fix in the migration code

     The recent introduction of irq_force_complete_move() in the core
     code, causes a problem for the nostalgia crowd who maintains ia64
     out of tree.

     The code assumes that hierarchical interrupt domains are enabled
     and dereferences irq_data::parent_data unconditionally. That works
     in mainline because both architectures which enable that code have
     hierarchical domains enabled. Though it breaks the ia64 build,
     which enables the functionality, but does not have hierarchical
     domains.

     While it's not really a problem for mainline today, this
     unconditional dereference is inconsistent and trivially fixable by
     using the existing helper function irqd_get_parent_data(), which
     has the appropriate #ifdeffery in place"

* tag 'irq-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  genirq/migration: Use irqd_get_parent_data() in irq_force_complete_move()
  irqdomain: Stop using 'host' for domain
  irqdomain: Rename irq_get_default_host() to irq_get_default_domain()
  irqdomain: Rename irq_set_default_host() to irq_set_default_domain()

3 months agoMerge tag 'timers-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 6 Apr 2025 15:13:16 +0000 (08:13 -0700)]
Merge tag 'timers-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer fix from Thomas Gleixner:
 "A revert to fix a adjtimex() regression:

  The recent change to prevent that time goes backwards for the coarse
  time getters due to immediate multiplier adjustments via adjtimex(),
  changed the way how the timekeeping core treats that.

  That change result in a regression on the adjtimex() side, which is
  user space visible:

   1) The forwarding of the base time moves the update out of the
      original period and establishes a new one. That's changing the
      behaviour of the [PF]LL control, which user space expects to be
      applied periodically.

   2) The clearing of the accumulated NTP error due to #1, changes the
      behaviour as well.

  An attempt to delay the multiplier/frequency update to the next tick
  did not solve the problem as userspace expects that the multiplier or
  frequency updates are in effect, when the syscall returns.

  There is a different solution for the coarse time problem available,
  so revert the offending commit to restore the existing adjtimex()
  behaviour"

* tag 'timers-urgent-2025-04-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Revert "timekeeping: Fix possible inconsistencies in _COARSE clockids"

3 months agoMerge tag 'sh-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubi...
Linus Torvalds [Sun, 6 Apr 2025 15:10:45 +0000 (08:10 -0700)]
Merge tag 'sh-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux

Pull sh updates from John Paul Adrian Glaubitz:
 "One important fix and one small configuration update.

  The first patch by Artur Rojek fixes an issue with the J2 firmware
  loader not being able to find the location of the device tree blob due
  to insufficient alignment of the .bss section which rendered J2 boards
  unbootable.

  The second patch by Johan Korsnes updates the defconfigs on sh to drop
  the CONFIG_NET_CLS_TCINDEX configuration option which became obsolete
  after 8c710f75256b ("net/sched: Retire tcindex classifier").

  Summary:

   - sh: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX

   - sh: Align .bss section padding to 8-byte boundary"

* tag 'sh-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux:
  sh: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX
  sh: Align .bss section padding to 8-byte boundary

3 months agoMerge tag 'kbuild-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy...
Linus Torvalds [Sat, 5 Apr 2025 22:46:50 +0000 (15:46 -0700)]
Merge tag 'kbuild-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild

Pull Kbuild updates from Masahiro Yamada:

 - Improve performance in gendwarfksyms

 - Remove deprecated EXTRA_*FLAGS and KBUILD_ENABLE_EXTRA_GCC_CHECKS

 - Support CONFIG_HEADERS_INSTALL for ARCH=um

 - Use more relative paths to sources files for better reproducibility

 - Support the loong64 Debian architecture

 - Add Kbuild bash completion

 - Introduce intermediate vmlinux.unstripped for architectures that need
   static relocations to be stripped from the final vmlinux

 - Fix versioning in Debian packages for -rc releases

 - Treat missing MODULE_DESCRIPTION() as an error

 - Convert Nios2 Makefiles to use the generic rule for built-in DTB

 - Add debuginfo support to the RPM package

* tag 'kbuild-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (40 commits)
  kbuild: rpm-pkg: build a debuginfo RPM
  kconfig: merge_config: use an empty file as initfile
  nios2: migrate to the generic rule for built-in DTB
  rust: kbuild: skip `--remap-path-prefix` for `rustdoc`
  kbuild: pacman-pkg: hardcode module installation path
  kbuild: deb-pkg: don't set KBUILD_BUILD_VERSION unconditionally
  modpost: require a MODULE_DESCRIPTION()
  kbuild: make all file references relative to source root
  x86: drop unnecessary prefix map configuration
  kbuild: deb-pkg: add comment about future removal of KDEB_COMPRESS
  kbuild: Add a help message for "headers"
  kbuild: deb-pkg: remove "version" variable in mkdebian
  kbuild: deb-pkg: fix versioning for -rc releases
  Documentation/kbuild: Fix indentation in modules.rst example
  x86: Get rid of Makefile.postlink
  kbuild: Create intermediate vmlinux build with relocations preserved
  kbuild: Introduce Kconfig symbol for linking vmlinux with relocations
  kbuild: link-vmlinux.sh: Make output file name configurable
  kbuild: do not generate .tmp_vmlinux*.map when CONFIG_VMLINUX_MAP=y
  Revert "kheaders: Ignore silly-rename files"
  ...

3 months agoMerge tag 'drm-next-2025-04-05' of https://gitlab.freedesktop.org/drm/kernel
Linus Torvalds [Sat, 5 Apr 2025 22:35:11 +0000 (15:35 -0700)]
Merge tag 'drm-next-2025-04-05' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Weekly fixes, mostly from the end of last week, this week was very
  quiet, maybe you scared everyone away. It's mostly amdgpu, and xe,
  with some i915, adp and bridge bits, since I think this is overly
  quiet I'd expect rc2 to be a bit more lively.

  bridge:
   - tda998x: Select CONFIG_DRM_KMS_HELPER

  amdgpu:
   - Guard against potential division by 0 in fan code
   - Zero RPM support for SMU 14.0.2
   - Properly handle SI and CIK support being disabled
   - PSR fixes
   - DML2 fixes
   - DP Link training fix
   - Vblank fixes
   - RAS fixes
   - Partitioning fix
   - SDMA fix
   - SMU 13.0.x fixes
   - Rom fetching fix
   - MES fixes
   - Queue reset fix

  xe:
   - Fix NULL pointer dereference on error path
   - Add missing HW workaround for BMG
   - Fix survivability mode not triggering
   - Fix build warning when DRM_FBDEV_EMULATION is not set

  i915:
   - Bounds check for scalers in DSC prefill latency computation
   - Fix build by adding a missing include

  adp:
   - Fix error handling in plane setup"

  # -----BEGIN PGP SIGNATURE-----

* tag 'drm-next-2025-04-05' of https://gitlab.freedesktop.org/drm/kernel: (34 commits)
  drm/i2c: tda998x: select CONFIG_DRM_KMS_HELPER
  drm/amdgpu/gfx12: fix num_mec
  drm/amdgpu/gfx11: fix num_mec
  drm/amd/pm: Add gpu_metrics_v1_8
  drm/amdgpu: Prefer shadow rom when available
  drm/amd/pm: Update smu metrics table for smu_v13_0_6
  drm/amd/pm: Remove host limit metrics support
  Remove unnecessary firmware version check for gc v9_4_2
  drm/amdgpu: stop unmapping MQD for kernel queues v3
  Revert "drm/amdgpu/sdma_v4_4_2: update VM flush implementation for SDMA"
  drm/amdgpu: Parse all deferred errors with UMC aca handle
  drm/amdgpu: Update ta ras block
  drm/amdgpu: Add NPS2 to DPX compatible mode
  drm/amdgpu: Use correct gfx deferred error count
  drm/amd/display: Actually do immediate vblank disable
  drm/amd/display: prevent hang on link training fail
  Revert "drm/amd/display: dml2 soc dscclk use DPM table clk setting"
  drm/amd/display: Increase vblank offdelay for PSR panels
  drm/amd: Handle being compiled without SI or CIK support better
  drm/amd/pm: Add zero RPM enabled OD setting support for SMU14.0.2
  ...

3 months agokbuild: rpm-pkg: build a debuginfo RPM
Uday Shankar [Mon, 31 Mar 2025 22:46:32 +0000 (16:46 -0600)]
kbuild: rpm-pkg: build a debuginfo RPM

The rpm-pkg make target currently suffers from a few issues related to
debuginfo:
1. debuginfo for things built into the kernel (vmlinux) is not available
   in any RPM produced by make rpm-pkg. This makes using tools like
   systemtap against a make rpm-pkg kernel impossible.
2. debug source for the kernel is not available. This means that
   commands like 'disas /s' in gdb, which display source intermixed with
   assembly, can only print file names/line numbers which then must be
   painstakingly resolved to actual source in a separate editor.
3. debuginfo for modules is available, but it remains bundled with the
   .ko files that contain module code, in the main kernel RPM. This is a
   waste of space for users who do not need to debug the kernel (i.e.
   most users).

Address all of these issues by additionally building a debuginfo RPM
when the kernel configuration allows for it, in line with standard
patterns followed by RPM distributors. With these changes:
1. systemtap now works (when these changes are backported to 6.11, since
   systemtap lags a bit behind in compatibility), as verified by the
   following simple test script:

   # stap -e 'probe kernel.function("do_sys_open").call { printf("%s\n", $$parms); }'
   dfd=0xffffffffffffff9c filename=0x7fe18800b160 flags=0x88800 mode=0x0
   ...

2. disas /s works correctly in gdb, with source and disassembly
   interspersed:

   # gdb vmlinux --batch -ex 'disas /s blk_op_str'
   Dump of assembler code for function blk_op_str:
   block/blk-core.c:
   125     {
      0xffffffff814c8740 <+0>:     endbr64

   127
   128             if (op < ARRAY_SIZE(blk_op_name) && blk_op_name[op])
      0xffffffff814c8744 <+4>:     mov    $0xffffffff824a7378,%rax
      0xffffffff814c874b <+11>:    cmp    $0x23,%edi
      0xffffffff814c874e <+14>:    ja     0xffffffff814c8768 <blk_op_str+40>
      0xffffffff814c8750 <+16>:    mov    %edi,%edi

   126             const char *op_str = "UNKNOWN";
      0xffffffff814c8752 <+18>:    mov    $0xffffffff824a7378,%rdx

   127
   128             if (op < ARRAY_SIZE(blk_op_name) && blk_op_name[op])
      0xffffffff814c8759 <+25>:    mov    -0x7dfa0160(,%rdi,8),%rax

   126             const char *op_str = "UNKNOWN";
      0xffffffff814c8761 <+33>:    test   %rax,%rax
      0xffffffff814c8764 <+36>:    cmove  %rdx,%rax

   129                     op_str = blk_op_name[op];
   130
   131             return op_str;
   132     }
      0xffffffff814c8768 <+40>:    jmp    0xffffffff81d01360 <__x86_return_thunk>
   End of assembler dump.

3. The size of the main kernel package goes down substantially,
   especially if many modules are built (quite typical). Here is a
   comparison of installed size of the kernel package (configured with
   allmodconfig, dwarf4 debuginfo, and module compression turned off)
   before and after this patch:

   # rpm -qi kernel-6.13* | grep -E '^(Version|Size)'
   Version     : 6.13.0postpatch+
   Size        : 1382874089
   Version     : 6.13.0prepatch+
   Size        : 17870795887

   This is a ~92% size reduction.

Note that a debuginfo package can only be produced if the following
configs are set:
- CONFIG_DEBUG_INFO=y
- CONFIG_MODULE_COMPRESS=n
- CONFIG_DEBUG_INFO_SPLIT=n

The first of these is obvious - we can't produce debuginfo if the build
does not generate it. The second two requirements can in principle be
removed, but doing so is difficult with the current approach, which uses
a generic rpmbuild script find-debuginfo.sh that processes all packaged
executables. If we want to remove those requirements the best path
forward is likely to add some debuginfo extraction/installation logic to
the modules_install target (controllable by flags). That way, it's
easier to operate on modules before they're compressed, and the logic
can be reused by all packaging targets.

Signed-off-by: Uday Shankar <ushankar@purestorage.com>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
3 months agokconfig: merge_config: use an empty file as initfile
Daniel Gomez [Fri, 28 Mar 2025 14:28:37 +0000 (14:28 +0000)]
kconfig: merge_config: use an empty file as initfile

The scripts/kconfig/merge_config.sh script requires an existing
$INITFILE (or the $1 argument) as a base file for merging Kconfig
fragments. However, an empty $INITFILE can serve as an initial starting
point, later referenced by the KCONFIG_ALLCONFIG Makefile variable
if -m is not used. This variable can point to any configuration file
containing preset config symbols (the merged output) as stated in
Documentation/kbuild/kconfig.rst. When -m is used $INITFILE will
contain just the merge output requiring the user to run make (i.e.
KCONFIG_ALLCONFIG=<$INITFILE> make <allnoconfig/alldefconfig> or make
olddefconfig).

Instead of failing when `$INITFILE` is missing, create an empty file and
use it as the starting point for merges.

Signed-off-by: Daniel Gomez <da.gomez@samsung.com>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
3 months agonios2: migrate to the generic rule for built-in DTB
Masahiro Yamada [Sun, 22 Dec 2024 00:30:53 +0000 (09:30 +0900)]
nios2: migrate to the generic rule for built-in DTB

Commit 654102df2ac2 ("kbuild: add generic support for built-in boot
DTBs") introduced generic support for built-in DTBs.

Select GENERIC_BUILTIN_DTB when built-in DTB support is enabled.

To keep consistency across architectures, this commit also renames
CONFIG_NIOS2_DTB_SOURCE_BOOL to CONFIG_BUILTIN_DTB, and
CONFIG_NIOS2_DTB_SOURCE to CONFIG_BUILTIN_DTB_NAME.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
3 months agosh: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX
Johan Korsnes [Sun, 23 Mar 2025 19:13:30 +0000 (20:13 +0100)]
sh: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX

This option was removed from Kconfig in 8c710f75256b ("net/sched:
Retire tcindex classifier") but from the defconfigs.

Fixes: 8c710f75256b ("net/sched: Retire tcindex classifier")
Signed-off-by: Johan Korsnes <johan.korsnes@gmail.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Rich Felker <dalias@libc.org>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
3 months agosh: Align .bss section padding to 8-byte boundary
Artur Rojek [Sun, 16 Feb 2025 17:55:44 +0000 (18:55 +0100)]
sh: Align .bss section padding to 8-byte boundary

J2-based devices expect to find a device tree blob at the end of the
.bss section. As of a77725a9a3c5 ("scripts/dtc: Update to upstream
version v1.6.1-19-g0a3a9d3449c8"), libfdt enforces 8-byte alignment
for the DTB, causing J2 devices to fail early in sh_fdt_init().

As the J2 loader firmware calculates the DTB location based on the kernel
image .bss section size rather than the __bss_stop symbol offset, the
required alignment can't be enforced with BSS_SECTION(0, PAGE_SIZE, 8).

To fix this, inline a modified version of the above macro which grows
.bss by the required size. While this change affects all existing SH
boards, it should be benign on platforms which don't need this alignment.

Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Tested-by: Rob Landley <rob@landley.net>
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
3 months agoMerge tag 'input-for-v6.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sat, 5 Apr 2025 16:20:39 +0000 (09:20 -0700)]
Merge tag 'input-for-v6.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input

Pull input updates from Dmitry Torokhov:

 - a brand new driver for touchpads and touchbars in newer Apple devices

 - support for Berlin-A series in goodix-berlin touchscreen driver

 - improvements to matrix_keypad driver to better handle GPIOs toggling

 - assorted small cleanups in other input drivers

* tag 'input-for-v6.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
  Input: goodix_berlin - add support for Berlin-A series
  dt-bindings: input: goodix,gt9916: Document gt9897 compatible
  dt-bindings: input: matrix_keypad - add wakeup-source property
  dt-bindings: input: matrix_keypad - add missing property
  Input: pm8941-pwrkey - fix dev_dbg() output in pm8941_pwrkey_irq()
  Input: synaptics - hide unused smbus_pnp_ids[] array
  Input: apple_z2 - fix potential confusion in Kconfig
  Input: matrix_keypad - use fsleep for delays after activating columns
  Input: matrix_keypad - add settle time after enabling all columns
  dt-bindings: input: matrix_keypad: add settle time after enabling all columns
  dt-bindings: input: matrix_keypad: convert to YAML
  dt-bindings: input: Correct indentation and style in DTS example
  MAINTAINERS: Add entries for Apple Z2 touchscreen driver
  Input: apple_z2 - add a driver for Apple Z2 touchscreens
  dt-bindings: input: touchscreen: Add Z2 controller
  Input: Switch to use hrtimer_setup()
  Input: drop vb2_ops_wait_prepare/finish

3 months agotracing/timers: Rename the hrtimer_init event to hrtimer_setup
Nam Cao [Wed, 5 Feb 2025 10:55:21 +0000 (11:55 +0100)]
tracing/timers: Rename the hrtimer_init event to hrtimer_setup

The function hrtimer_init() doesn't exist anymore. It was replaced by
hrtimer_setup().

Thus, rename the hrtimer_init trace event to hrtimer_setup to keep it
consistent.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/all/cba84c3d853c5258aa3a262363a6eac08e2c7afc.1738746927.git.namcao@linutronix.de
3 months agohrtimers: Rename debug_init_on_stack() to debug_setup_on_stack()
Nam Cao [Wed, 5 Feb 2025 10:55:20 +0000 (11:55 +0100)]
hrtimers: Rename debug_init_on_stack() to debug_setup_on_stack()

All the hrtimer_init*() functions have been renamed to hrtimer_setup*().
Rename debug_init_on_stack() to debug_setup_on_stack() as well, to keep the
names consistent.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/all/073cf6162779a2f5b12624677d4c49ee7eccc1ed.1738746927.git.namcao@linutronix.de
3 months agohrtimers: Rename debug_init() to debug_setup()
Nam Cao [Wed, 5 Feb 2025 10:55:19 +0000 (11:55 +0100)]
hrtimers: Rename debug_init() to debug_setup()

All the hrtimer_init*() functions have been renamed to hrtimer_setup*().
Rename debug_init() to debug_setup() as well, to keep the names consistent.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/all/4b730c1f79648b16a1c5413f928fdc2e138dfc43.1738746927.git.namcao@linutronix.de
3 months agohrtimers: Rename __hrtimer_init_sleeper() to __hrtimer_setup_sleeper()
Nam Cao [Wed, 5 Feb 2025 10:55:18 +0000 (11:55 +0100)]
hrtimers: Rename __hrtimer_init_sleeper() to __hrtimer_setup_sleeper()

All the hrtimer_init*() functions have been renamed to hrtimer_setup*().
Rename __hrtimer_init_sleeper() to __hrtimer_setup_sleeper() as well, to
keep the names consistent.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/all/807694aedad9353421c4a7347629a30c5c31026f.1738746927.git.namcao@linutronix.de