Lars Povlsen [Wed, 9 Dec 2020 14:27:51 +0000 (15:27 +0100)]
pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)
This adds 'interrupt-controller' features for the signals available on
the Microchip SGPIO controller, however only for controller versions
on the Sparx5 platform (or later).
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Zou Wei [Tue, 24 Nov 2020 11:42:53 +0000 (19:42 +0800)]
pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword
Fix the following sparse warnings:
drivers/pinctrl/pinctrl-microchip-sgpio.c:63:31: warning: symbol 'properties_luton' was not declared. Should it be static?
drivers/pinctrl/pinctrl-microchip-sgpio.c:68:31: warning: symbol 'properties_ocelot' was not declared. Should it be static?
drivers/pinctrl/pinctrl-microchip-sgpio.c:73:31: warning: symbol 'properties_sparx5' was not declared. Should it be static?
Tiezhu Yang [Tue, 24 Nov 2020 09:17:03 +0000 (17:17 +0800)]
pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error
If CONFIG_HAS_IOMEM is not set, devm_platform_ioremap_resource() will
be not built in drivers/base/platform.c and then there exists a build
error about undefined reference to "devm_platform_ioremap_resource"
in pinctrl-at91-pio4.c under COMPILE_TEST and CONFIG_PINCTRL_AT91PIO4,
make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix it.
Zhiyong Tao [Fri, 20 Nov 2020 09:30:58 +0000 (17:30 +0800)]
pinctrl: mtk: Fix low level output voltage issue
This patch is used to fix low level output voltage issue.
A pin is changed from input pull-up to output high.
The Dout value of the pin is default as 0.
If we change the direction of the pin before the dout value of the pin,
It maybe produce a low level output voltage between "input pull-up" and
"output high".
Yu Kuai [Thu, 19 Nov 2020 01:12:19 +0000 (09:12 +0800)]
pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe()
if of_find_device_by_node() succeed, pinctrl_falcon_probe() doesn't have
a corresponding put_device(). Thus add put_device() to fix the exception
handling for this function implementation.
s500_padinfo[] is never modified and should be made 'const' to allow
the compiler to optimize code generation, i.e. put it in the text
section instead of the data section.
Before:
text data bss dec hex filename
12503 5088 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o
After:
text data bss dec hex filename
14435 3156 0 17591 44b7 drivers/pinctrl/actions/pinctrl-s500.o
Lars Povlsen [Fri, 13 Nov 2020 14:51:50 +0000 (15:51 +0100)]
pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
The driver is added as a pinctrl driver, albeit only having just GPIO
support currently. The hardware supports other functions that will be
added following.
Eugen Hristev [Fri, 13 Nov 2020 13:24:29 +0000 (15:24 +0200)]
pinctrl: at91-pio4: add support for fewer lines on last PIO bank
Some products, like sama7g5, do not have a full last bank of PIO lines.
In this case for example, sama7g5 only has 8 lines for the PE bank.
PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
To cope with this situation, added a data attribute that is product dependent,
to specify the number of lines of the last bank.
In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
adjust the total number of lines accordingly.
This will avoid advertising 160 lines instead of the actual 136, as this
product supports, and to avoid reading/writing to invalid register addresses.
Linus Walleij [Tue, 24 Nov 2020 14:38:07 +0000 (15:38 +0100)]
Merge tag 'intel-pinctrl-v5.11-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.11-1
* Add Intel Alder Lake-S pin controller support
* Add Intel Elkhart Lake pin controller support
* Add Intel Lakefield driver pin controller support
* Miscellaneous fixes for Intel Lynxpoint driver
The following is an automated git shortlog grouped by driver:
intel:
- Add Intel Alder Lake-S pin controller support
- Add Intel Elkhart Lake pin controller support
- Add blank line before endif in Kconfig
- Add Intel Lakefield pin controller support
lynxpoint:
- Enable pin configuration setting for GPIO chip
- Use defined constant for disabled bias explicitly
- Unify initcall location in the code
Yangtao Li [Tue, 10 Nov 2020 06:24:40 +0000 (14:24 +0800)]
pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Yangtao Li [Tue, 10 Nov 2020 06:23:44 +0000 (14:23 +0800)]
pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
The interrupt descriptor cannot be found in the interrupt processing
function, and this situation cannot happen when the system is running
normally. It doesn't seem right to return directly to the status of not
handling gic. In this case, it must be a bug, let's mark it with
WARN_ON.
John Stultz [Tue, 10 Nov 2020 21:56:19 +0000 (21:56 +0000)]
pinctrl: qcom: Fix msm8953 Kconfig entry to depend on, not select PINCTRL_MSM
One fixup following my patch commit be117ca32261 ("pinctrl:
qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then
a selected config") being queued in LinusW's tree, as a new
config entry was added for the msm8953 that also needs the
change.
Gustavo A. R. Silva [Fri, 20 Nov 2020 18:31:44 +0000 (12:31 -0600)]
pinctrl: renesas: Fix fall-through warnings for Clang
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning
by explicitly adding a break statement instead of letting the code fall
through to the next case.
Andy Shevchenko [Thu, 12 Nov 2020 19:03:01 +0000 (21:03 +0200)]
pinctrl: baytrail: Avoid clearing debounce value when turning it off
Baytrail pin control has a common register to set up debounce timeout.
When a pin configuration requested debounce to be disabled, the rest
of the pins may still want to have debounce enabled and thus rely on
the common timeout value. Avoid clearing debounce value when turning
it off for one pin while others may still use it.
Rikard Falkeborn [Mon, 9 Nov 2020 22:10:12 +0000 (23:10 +0100)]
pinctrl: renesas: Constify sh73a0_vccq_mc0_ops
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the
ops field in the regulator_desc struct, which is a const pointer. Make
it const to allow the compiler to put it in read-only memory.
Geert Uytterhoeven [Wed, 28 Oct 2020 15:16:37 +0000 (16:16 +0100)]
pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIO
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles
GPIOs, too. To reduce code size when compiling a kernel supporting only
modern SoCs, most, but not all, of the GPIO functionality is protected
by checks for CONFIG_PINCTRL_SH_FUNC_GPIO.
Factor out the remaining parts when not needed:
1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input
resp. output capabilities (SuperH and SH/R-Mobile).
2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO
pins to interrupt numbers (SH/R-Mobile).
3. sh_pfc_gpio_set_direction() configures GPIO direction, called from
the GPIO driver through pinctrl_gpio_direction_{in,out}put()
(SH/R-Mobile). Unfortunately this function cannot just be moved to
drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of
sh_pfc_pinctrl, which is internal to
drivers/pinctrl/renesas/pinctrl.c.
While code size reduction is minimal, this does help in documenting
depencies.
Geert Uytterhoeven [Wed, 28 Oct 2020 15:16:36 +0000 (16:16 +0100)]
pinctrl: renesas: r8a7778: Use common R-Car bias handling
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that
have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD)
registers, like R-Car Gen3 and RZ/G2. Update the function to handle
SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car
Gen1/Gen2 and RZ/G1.
Reduce code duplication by converting the R-Car M1A pin control driver
to use the common handler.
Note that this changes behavior in case the (invalid!) option
"bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored
silently; after this change, it is considered the same as
"bias-pull-up".
Geert Uytterhoeven [Wed, 28 Oct 2020 15:16:35 +0000 (16:16 +0100)]
pinctrl: renesas: r8a7778: Use physical addresses for PUPR regs
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car
M1A uses register offsets instead of register physical addresses.
This is different from the handling on other R-Car parts.
Convert the bias handling from register offsets to physical addresses.
This increases uniformity, and prepares for consolidation of the bias
handling.
Geert Uytterhoeven [Wed, 28 Oct 2020 15:16:33 +0000 (16:16 +0100)]
pinctrl: renesas: Optimize sh_pfc_pin_config
Shrink sh_pfc_pin_config from 8 to 2 bytes:
- The mux_set flag can be removed, as a non-zero mark value means the
same (zero = PINMUX_RESERVED is an invalid mark value),
- The gpio_enabled flag needs only a single bit,
- Mark values are small integers, and can easily fit in a 15-bit
bitfield.
This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs
array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB.
Geert Uytterhoeven [Wed, 28 Oct 2020 15:16:32 +0000 (16:16 +0100)]
pinctrl: renesas: Reorder struct sh_pfc_pin to remove hole
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is
present in between the enum_id and name members of the sh_pfc_pin
structure. Get rid of this hole by sorting the structure's members by
decreasing size.
This saves up to 1.5 KiB per enabled SoC, and reduces the size of a
kernel including support for all R-Car Gen3 SoCs by more than 10 KiB.
Geert Uytterhoeven [Wed, 28 Oct 2020 15:16:30 +0000 (16:16 +0100)]
pinctrl: renesas: Remove superfluous goto in sh_pfc_gpio_set_direction()
Commit b13431ed6eab808a ("pinctrl: sh-pfc: Remove incomplete flag
"cfg->type"") removed the last statement in between the goto and the
label. Hence remove both.
Biju Das [Mon, 19 Oct 2020 12:42:58 +0000 (13:42 +0100)]
pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[34]
This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs.
Optimize pinctrl image size for RZ/G1[MN], when support for R-Car
M2-W/M2-N (R8A779[13]) is not enabled.
Biju Das [Mon, 19 Oct 2020 13:28:05 +0000 (14:28 +0100)]
pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.
Biju Das [Mon, 19 Oct 2020 12:42:53 +0000 (13:42 +0100)]
pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1
This driver supports both RZ/G2H and R-Car H3 ES2 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2
(R8A77951) is not enabled.
Andy Shevchenko [Wed, 11 Nov 2020 12:06:05 +0000 (14:06 +0200)]
pinctrl: merrifield: Set default bias in case no particular value given
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible
because it gives a good trade off between weakness and minimization of leakage
current (will be only 50 uA with the above choice).
Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Evan Green [Wed, 11 Nov 2020 23:17:28 +0000 (15:17 -0800)]
pinctrl: jasperlake: Fix HOSTSW_OWN offset
GPIOs that attempt to use interrupts get thwarted with a message like:
"pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because
the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's
owned by ACPI.
Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Cc: stable@vger.kernel.org Signed-off-by: Evan Green <evgreen@chromium.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Andy Shevchenko [Tue, 10 Nov 2020 19:59:23 +0000 (21:59 +0200)]
pinctrl: jasperlake: Unhide SPI group of pins
If the group of pins is hidden in the pin list it affects
the register offset calculation despite fixed GPIO base.
Hence, the offsets of all pins after the hidden group
are broken. Instead we have to unhide the group and use a flag
to exclude it from GPIO number space.
Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Reported-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Vinod Koul [Wed, 11 Nov 2020 04:36:10 +0000 (10:06 +0530)]
pinctrl: qcom: sdx55: update kconfig dependency
Commit be117ca32261 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a
dependency rather then a selected config") moved the qcom pinctrl drivers
to have PINCTRL_MSM as dependency rather then a selected config, so do
this change for SDX55 pinctrl driver as well.
Linus Walleij [Tue, 10 Nov 2020 23:23:30 +0000 (00:23 +0100)]
pinctrl: nomadik: db8500: Add more detailed LCD groups
We need a more granular distribution among funcion A
and function B for the LCD pins for the Samsung
GT-I9070. Provide some new pin groups so we can
configure this phone properly.
John Stultz [Fri, 6 Nov 2020 04:27:10 +0000 (04:27 +0000)]
firmware: QCOM_SCM: Allow qcom_scm driver to be loadable as a permenent module
Allow the qcom_scm driver to be loadable as a permenent module.
This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to
ensure that drivers that call into the qcom_scm driver are
also built as modules. While not ideal in some cases its the
only safe way I can find to avoid build errors without having
those drivers select QCOM_SCM and have to force it on (as
QCOM_SCM=n can be valid for those drivers).
Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-3-john.stultz@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
John Stultz [Fri, 6 Nov 2020 04:27:08 +0000 (04:27 +0000)]
pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a depenency rather then a selected config
This patch reworks PINCTRL_MSM to be a visible option, and
instead of having the various SoC specific drivers select
PINCTRL_MSM, this switches those configs to depend on
PINCTRL_MSM.
This is useful, as it will be needed in order to cleanly support
having the qcom-scm driver, which pinctrl-msm calls into,
configured as a module. Without this change, we would eventually
have to add dependency lines to every config that selects
PINCTRL_MSM, and that would becomes a maintenance headache.
We also add PINCTRL_MSM to the arm64 defconfig to avoid
surprises as otherwise PINCTRL_MSM/IPQ* options previously
enabled, will be off.
Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-1-john.stultz@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Coiby Xu [Thu, 5 Nov 2020 23:19:11 +0000 (07:19 +0800)]
pinctrl: amd: print debounce filter info in debugfs
Print the status of debounce filter as follows,
$ cat /sys/kernel/debug/gpio
pin129 interrupt is disabled | interrupt is masked |
disable wakeup in S0i3 state | disable wakeup in S3 state |
disable wakeup in S4/S5 state| input is high | pull-up is disabled |
Pull-down is disabled | output is disabled |
debouncing filter disabled | 0x50000
pin130 interrupt is disabled | interrupt is masked |
disable wakeup in S0i3 state | disable wakeup in S3 state |
disable wakeup in S4/S5 state | input is high | pull-up is disabled |
Pull-down is disabled | output is disabled |
debouncing filter (high) enabled |
debouncing timeout is 124800 (us)| 0x503c8
Paul Cercueil [Sun, 1 Nov 2020 09:01:04 +0000 (09:01 +0000)]
pinctrl: ingenic: Add lcd-8bit group for JZ4770
Add the "lcd-8bit" group to the "lcd" function.
As "lcd-24bit" is a superset of "lcd-8bit", in theory the former could
be modified to only contain the pins not already included in "lcd-8bit",
just like how it's done for the JZ4740 and JZ4725B platforms. However,
we can't do that without breaking Device Tree ABI, so in that case we
have no choice but to have two groups containing the same pins.
Paul Cercueil [Sun, 1 Nov 2020 09:01:03 +0000 (09:01 +0000)]
pinctrl: ingenic: Get rid of repetitive data
Abuse the pin function pointer to store the pin function value directly,
when all the pins of a group have the same function value. Now when the
pointer value is <= 3 (unsigned), the pointer value is used as the pin
function; otherwise it is used as a regular pointer.
This drastically reduces the number of pin function tables needed, and
drops .data usage by about 2 KiB. Additionally, the few pin function
tables that are still around now contain u8 instead of int, since the
largest number that will be stored is 3.
Geert Uytterhoeven [Wed, 28 Oct 2020 14:51:17 +0000 (15:51 +0100)]
pinctrl: Remove hole in pinctrl_gpio_range
On 64-bit platforms, pointer size and alignment are 64-bit, hence two
4-byte holes are present before the pins and gc members of the
pinctrl_gpio_range structure. Get rid of these holes by moving the
pins pointer.
This reduces kernel size of an arm64 Rockchip kernel by ca. 512 bytes.
Andy Shevchenko [Thu, 29 Oct 2020 11:13:15 +0000 (13:13 +0200)]
pinctrl: intel: Add Intel Alder Lake-S pin controller support
This driver adds pinctrl/GPIO support for Intel Alder Lake-S SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 2 Nov 2020 12:21:07 +0000 (14:21 +0200)]
pinctrl: intel: Add Intel Elkhart Lake pin controller support
This driver adds pinctrl/GPIO support for Intel Elkhart Lake SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 26 Oct 2020 19:23:25 +0000 (21:23 +0200)]
pinctrl: intel: Add Intel Lakefield pin controller support
This driver adds pinctrl/GPIO support for Intel Lakefield SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 14 Oct 2020 10:46:38 +0000 (13:46 +0300)]
pinctrl: intel: Set default bias in case no particular value given
When GPIO library asks pin control to set the bias, it doesn't pass
any value of it and argument is considered boolean (and this is true
for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual
drivers must behave well, when they got the resistance value of 1 Ohm,
i.e. transforming it to sane default.
In case of Intel pin control hardware the 5 kOhm sounds plausible
because on one hand it's a minimum of resistors present in all
hardware generations and at the same time it's high enough to minimize
leakage current (will be only 200 uA with the above choice).
Fixes: e57725eabf87 ("pinctrl: intel: Add support for hardware debouncer") Reported-by: Jamie McClymont <jamie@kwiius.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
As easy to get the 3 resistors are gated separately and according to
parallel circuits calculations we may get combinations of the above where
the result is always strictly less than minimal resistance. Hence,
additional values can be:
Joe Perches [Thu, 22 Oct 2020 02:36:07 +0000 (19:36 -0700)]
treewide: Convert macro and uses of __section(foo) to __section("foo")
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.
Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.
Rasmus Villemoes [Sat, 24 Oct 2020 01:04:26 +0000 (03:04 +0200)]
kernel/sys.c: fix prototype of prctl_get_tid_address()
tid_addr is not a "pointer to (pointer to int in userspace)"; it is in
fact a "pointer to (pointer to int in userspace) in userspace". So
sparse rightfully complains about passing a kernel pointer to
put_user().
Eric Biggers [Fri, 23 Oct 2020 23:27:16 +0000 (16:27 -0700)]
mm: remove kzfree() compatibility definition
Commit 453431a54934 ("mm, treewide: rename kzfree() to
kfree_sensitive()") renamed kzfree() to kfree_sensitive(),
but it left a compatibility definition of kzfree() to avoid
being too disruptive.
Since then a few more instances of kzfree() have slipped in.
Just get rid of them and remove the compatibility definition
once and for all.
Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 25 Oct 2020 18:28:49 +0000 (11:28 -0700)]
Merge tag 'timers-urgent-2020-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer fixes from Thomas Gleixner:
"A time namespace fix and a matching selftest. The futex absolute
timeouts which are based on CLOCK_MONOTONIC require time namespace
corrected. This was missed in the original time namesapce support"
* tag 'timers-urgent-2020-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
selftests/timens: Add a test for futex()
futex: Adjust absolute futex timeouts with per time namespace offset
Linus Torvalds [Sun, 25 Oct 2020 18:25:16 +0000 (11:25 -0700)]
Merge tag 'sched-urgent-2020-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull scheduler fixes from Thomas Gleixner:
"Two scheduler fixes:
- A trivial build fix for sched_feat() to compile correctly with
CONFIG_JUMP_LABEL=n
- Replace a zero lenght array with a flexible array"
* tag 'sched-urgent-2020-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
sched/features: Fix !CONFIG_JUMP_LABEL case
sched: Replace zero-length array with flexible-array
Linus Torvalds [Sun, 25 Oct 2020 18:12:31 +0000 (11:12 -0700)]
Merge tag 'ntb-5.10' of git://github.com/jonmason/ntb
Pull NTB fixes from Jon Mason.
* tag 'ntb-5.10' of git://github.com/jonmason/ntb:
NTB: Use struct_size() helper in devm_kzalloc()
ntb: intel: Fix memleak in intel_ntb_pci_probe
NTB: hw: amd: fix an issue about leak system resources
Linus Torvalds [Sun, 25 Oct 2020 18:10:23 +0000 (11:10 -0700)]
Merge branch 'i2c/for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fix from Wolfram Sang:
"Regression fix for rc1 and stable kernels as well"
* 'i2c/for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: core: Restore acpi_walk_dep_device_list() getting called after registering the ACPI i2c devs
Linus Torvalds [Sun, 25 Oct 2020 18:05:04 +0000 (11:05 -0700)]
Merge tag '5.10-rc-smb3-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6
Pull more cifs updates from Steve French:
"Add support for stat of various special file types (WSL reparse points
for char, block, fifo)"
* tag '5.10-rc-smb3-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6:
cifs: update internal module version number
smb3: add some missing definitions from MS-FSCC
smb3: remove two unused variables
smb3: add support for stat of WSL reparse points for special file types
Linus Torvalds [Sun, 25 Oct 2020 17:59:34 +0000 (10:59 -0700)]
Merge branch 'parisc-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull more parisc updates from Helge Deller:
- During this merge window O_NONBLOCK was changed to become 000200000,
but we missed that the syscalls timerfd_create(), signalfd4(),
eventfd2(), pipe2(), inotify_init1() and userfaultfd() do a strict
bit-wise check of the flags parameter.
To provide backward compatibility with existing userspace we
introduce parisc specific wrappers for those syscalls which filter
out the old O_NONBLOCK value and replaces it with the new one.
- Prevent HIL bus driver to get stuck when keyboard or mouse isn't
attached
- Improve error return codes when setting rtc time
- Minor documentation fix in pata_ns87415.c
* 'parisc-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
ata: pata_ns87415.c: Document support on parisc with superio chip
parisc: Add wrapper syscalls to fix O_NONBLOCK flag usage
hil/parisc: Disable HIL driver when it gets stuck
parisc: Improve error return codes when setting rtc time
Linus Torvalds [Sun, 25 Oct 2020 17:55:35 +0000 (10:55 -0700)]
Merge tag 'for-linus-5.10b-rc1c-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip
Pull more xen updates from Juergen Gross:
- a series for the Xen pv block drivers adding module parameters for
better control of resource usge
- a cleanup series for the Xen event driver
* tag 'for-linus-5.10b-rc1c-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip:
Documentation: add xen.fifo_events kernel parameter description
xen/events: unmask a fifo event channel only if it was masked
xen/events: only register debug interrupt for 2-level events
xen/events: make struct irq_info private to events_base.c
xen: remove no longer used functions
xen-blkfront: Apply changed parameter name to the document
xen-blkfront: add a parameter for disabling of persistent grants
xen-blkback: add a parameter for disabling of persistent grants
projects / users / jedix / linux-maple.git / log