Stephen Boyd [Tue, 27 Apr 2021 23:34:44 +0000 (16:34 -0700)]
Merge branches 'clk-imx', 'clk-samsung', 'clk-zynq', 'clk-rockchip' and 'clk-uniphier' into clk-next
- Simplify Zynq Kconfig dependencies
* clk-imx:
clk: imx: Reference preceded by free
clk: imx8mq: Correct the pcie1 sels
clk: imx8mp: Remove the none exist pcie clocks
clk: imx: Fix reparenting of UARTs not associated with stdout
* clk-samsung:
clk: samsung: Remove redundant dev_err calls
clk: exynos7: Mark aclk_fsys1_200 as critical
* clk-zynq:
clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
clk: zynqmp: Drop dependency on ARCH_ZYNQMP
clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
* clk-rockchip:
clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller
clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends
clk: rockchip: add clock controller for rk3568
clk: rockchip: support more core div setting
dt-binding: clock: Document rockchip, rk3568-cru bindings
clk: rockchip: add dt-binding header for rk3568
Stephen Boyd [Tue, 27 Apr 2021 23:34:28 +0000 (16:34 -0700)]
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next
- Use clk_hw pointers in socfpga driver
- Cleanup parent data in qcom clk drivers
* clk-cleanup:
clk: Drop double "if" in clk_core_determine_round_nolock() comment
clk: at91: Trivial typo fixes in the file sama7g5.c
clk: use clk_core_enable_lock() a bit more
* clk-socfpga:
clk: socfpga: remove redundant initialization of variable div
clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return
clk: socfpga: Fix code formatting
clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
clk: socfpga: arria10: convert to use clk_hw
clk: socfpga: use clk_hw_register for a5/c5
* clk-allwinner:
clk: sunxi: Demote non-conformant kernel-doc headers
clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll
* clk-qcom: (45 commits)
clk: qcom: rpmh: add support for SDX55 rpmh IPA clock
clk: qcom: gcc-sdm845: get rid of the test clock
clk: qcom: convert SDM845 Global Clock Controller to parent_data
dt-bindings: clock: separate SDM845 GCC clock bindings
clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE
clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE
clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE
clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: videocc-sm8250: use parent_hws where possible
clk: qcom: videocc-sm8150: use parent_hws where possible
clk: qcom: gpucc-sm8250: use parent_hws where possible
clk: qcom: gpucc-sm8150: use parent_hws where possible
clk: qcom: gcc-sm8350: use parent_hws where possible
clk: qcom: gcc-sm8250: use parent_hws where possible
clk: qcom: gcc-sm8150: use parent_hws where possible
clk: qcom: gcc-sdx55: use parent_hws where possible
...
staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210410055059.13518-4-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.
Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.
We also have a buch of gate clocks with their parents:
* "hsdma": "150m"
* "fe": "250m"
* "sp_divtx": "270m"
* "timer": "50m"
* "pcm": "270m"
* "pio": "50m"
* "gdma": "bus"
* "nand": "125m"
* "i2c": "50m"
* "i2s": "270m"
* "spi": "bus"
* "uart1": "50m"
* "uart2": "50m"
* "uart3": "50m"
* "eth": "50m"
* "pcie0": "125m"
* "pcie1": "125m"
* "pcie2": "125m"
* "crypto": "250m"
* "shxc": "50m"
With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.
Colin Ian King [Fri, 9 Apr 2021 09:01:03 +0000 (10:01 +0100)]
clk: uniphier: Fix potential infinite loop
The for-loop iterates with a u8 loop counter i and compares this
with the loop upper limit of num_parents that is an int type.
There is a potential infinite loop if num_parents is larger than
the u8 loop counter. Fix this by making the loop counter the same
type as num_parents. Also make num_parents an unsigned int to
match the return type of the call to clk_hw_get_num_parents.
Addresses-Coverity: ("Infinite loop") Fixes: 734d82f4a678 ("clk: uniphier: add core support code for UniPhier clock driver") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Masahiro Yamada <masahiroy@kernel.org> Link: https://lore.kernel.org/r/20210409090104.629722-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 12 Apr 2021 19:40:32 +0000 (12:40 -0700)]
Merge tag 'v5.13-rockchip-clocks' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Support for the clock controller on the new rk3568
- Some cleanups for rk3399 modularization
* tag 'v5.13-rockchip-clocks' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller
clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends
clk: rockchip: add clock controller for rk3568
clk: rockchip: support more core div setting
dt-binding: clock: Document rockchip, rk3568-cru bindings
clk: rockchip: add dt-binding header for rk3568
Stephen Boyd [Fri, 9 Apr 2021 19:13:15 +0000 (12:13 -0700)]
Merge tag 'clk-v5.13-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- clean up of redundant dev_err() calls after dev_ioremap_resource()
- fix for the clk-exynos7 driver (part of upcoming Galaxy S6 device
support)
* tag 'clk-v5.13-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Remove redundant dev_err calls
clk: exynos7: Mark aclk_fsys1_200 as critical
clk: qcom: convert SDM845 Global Clock Controller to parent_data
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
CONFIG_IPQ_APSS_PLL is tristate option and therefore this driver can
be compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
CONFIG_QCOM_A53PLL is tristate option and therefore this driver can be
compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
CONFIG_QCOM_A7PLL is tristate option and therefore this driver can be
compiled as a module. This patch adds missing MODULE_DEVICE_TABLE
definition which generates correct modalias for automatic loading of
this driver when it is built as an external module.
Stephen Boyd [Fri, 9 Apr 2021 16:50:46 +0000 (09:50 -0700)]
Merge tag 'clk-imx-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Fix reparenting of UART clocks by initializing only the ones
associated to stdout
- Correct the PCIE clocks for i.MX8MP and i.MX8MQ
- Make LPCG and SCU clocks return on registering failure
* tag 'clk-imx-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx: Reference preceded by free
clk: imx8mq: Correct the pcie1 sels
clk: imx8mp: Remove the none exist pcie clocks
clk: imx: Fix reparenting of UARTs not associated with stdout
Quanyang Wang [Tue, 6 Apr 2021 15:31:31 +0000 (23:31 +0800)]
clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever,
we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this
pll has been enabled. In ATF implementation, it will only assign
the mode to the variable (struct pm_pll *)pll->mode when handling
IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force
ATF send request to PWU to set the pll mode to PLL's register.
There is a scenario that happens in enabling VPLL_INT(clk_id:96):
1) VPLL_INT has been enabled during booting.
2) A driver calls clk_set_rate and according to the rate, the VPLL_INT
should be set to FRAC mode. Then zynqmp_pll_set_mode is called
to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point
ATF just stores the mode to a variable.
3) This driver calls clk_prepare_enable and zynqmp_pll_enable is
called to try to enable VPLL_INT pll. Because of 1), the function
zynqmp_pll_enable just returns without doing anything after checking
that this pll has been enabled.
In the scenario above, the pll mode of VPLL_INT will never be set
successfully. So adding set_pll_mode to check condition to fix it.
Quanyang Wang [Tue, 6 Apr 2021 15:40:15 +0000 (23:40 +0800)]
clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
The round_rate callback should only perform rate calculation and not
involve calling zynqmp_pll_set_mode to change the pll mode. So let's
move zynqmp_pll_set_mode out of round_rate and to set_rate callback.
Punit Agrawal [Mon, 22 Mar 2021 06:17:54 +0000 (15:17 +0900)]
clk: zynqmp: Drop dependency on ARCH_ZYNQMP
The clock driver depends on ZYNQMP_FIRMWARE which in turn depends on
ARCH_ZYNQMP. Simplify the Kconfig by dropping the redundant dependency
on ARCH_ZYNQMP as it'll be applied transitively via ZYNQMP_FIRMWARE.
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Colin Ian King [Tue, 6 Apr 2021 18:27:46 +0000 (19:27 +0100)]
clk: socfpga: remove redundant initialization of variable div
The variable div is being initialized with a value that is
never read and it is being updated later with a new value. The
initialization is redundant and can be removed.
Colin Ian King [Tue, 6 Apr 2021 17:01:15 +0000 (18:01 +0100)]
clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return
There is an error return path that is not kfree'ing socfpga_clk leading
to a memory leak. Fix this by adding in the missing kfree call.
Addresses-Coverity: ("Resource leak") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210406170115.430990-1-colin.king@canonical.com Acked-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paweł Chmiel [Sat, 24 Oct 2020 15:43:46 +0000 (17:43 +0200)]
clk: exynos7: Mark aclk_fsys1_200 as critical
This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper solution based on runtime PM is applied
(similar to what was done for Exynos5433), mark that clock as critical
so it won't be disabled.
It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
UFS module is probed before pmic used to power that device.
In this case defer probe was happening and that clock was disabled by
UFS driver, causing whole boot to hang on next CMU access.
Fixes: 753195a749a6 ("clk: samsung: exynos7: Correct CMU_FSYS1 clocks names") Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/linux-clk/20201024154346.9589-1-pawel.mikolaj.chmiel@gmail.com
[s.nawrocki: Added comment in the code] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Richard Zhu [Mon, 15 Mar 2021 08:17:48 +0000 (16:17 +0800)]
clk: imx8mq: Correct the pcie1 sels
- The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock.
Change the sys2_pll_500m to sys2_pll_50m.
- Correct one misspell of the imx8mq_pcie1_ctrl_sels definition, from
"sys2_pll_250m" to "sys2_pll_333m".
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Richard Zhu [Mon, 15 Mar 2021 08:17:47 +0000 (16:17 +0800)]
clk: imx8mp: Remove the none exist pcie clocks
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
directly, and can't be contolled by CCM at all.
Remove the PCIE PHY clock from clock driver to clean up codes.
There is only one PCIe in i.MX8MP, remove the none exist second PCIe
related clocks.
Remove the none exsits clocks IDs together.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Adam Ford [Sat, 13 Mar 2021 12:28:17 +0000 (06:28 -0600)]
clk: imx: Fix reparenting of UARTs not associated with stdout
Most if not all i.MX SoC's call a function which enables all UARTS.
This is a problem for users who need to re-parent the clock source,
because any attempt to change the parent results in an busy error
due to the fact that the clocks have been enabled already.
clk: failed to reparent uart1 to sys_pll1_80m: -16
Instead of pre-initializing all UARTS, scan the device tree to see
which UART clocks are associated to stdout, and only enable those
UART clocks if it's needed early. This will move initialization of
the remaining clocks until after the parenting of the clocks.
When the clocks are shutdown, this mechanism will also disable any
clocks that were pre-initialized.
Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Stephen Boyd [Sat, 3 Apr 2021 07:01:06 +0000 (00:01 -0700)]
Merge tag 'sunxi-clk-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard:
"Our usual PR for the Allwinner SoCs, this time adding support for sigma-delta
modulation on the V3s Audio PLL, and fixing a kernel doc header."
* tag 'sunxi-clk-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi: Demote non-conformant kernel-doc headers
clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll
Stephen Boyd [Sat, 3 Apr 2021 06:59:04 +0000 (23:59 -0700)]
Merge tag 'renesas-clk-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Spelling fixes
- Zero init clk_init_data
* tag 'renesas-clk-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: Zero init clk_init_data
clk: renesas: Couple of spelling fixes
Geert Uytterhoeven [Fri, 26 Mar 2021 10:54:34 +0000 (11:54 +0100)]
clk: renesas: Zero init clk_init_data
As clk_core_populate_parent_map() checks clk_init_data.num_parents
first, and checks clk_init_data.parent_names[] before
clk_init_data.parent_data[] and clk_init_data.parent_hws[], leaving the
latter uninitialized doesn't do harm for now. However, it is better to
play it safe, and initialize all clk_init_data structures to zeroes, to
avoid any current and future members containing uninitialized data.
Remove a few explicit zero initializers, which are now superfluous.
Taniya Das [Sat, 27 Mar 2021 01:41:05 +0000 (07:11 +0530)]
clk: qcom: camcc: Update the clock ops for the SC7180
Some of the RCGs could be always ON from the XO source and could be used
as the clock on signal for the GDSC to be operational. In the cases where
the GDSCs are parked at different source with the source clock disabled,
it could lead to the GDSC to be stuck at ON/OFF during gdsc disable/enable.
Thus park the RCGs at XO during clock disable and update the rcg_ops to
use the shared_ops.
Krzysztof Kozlowski [Sun, 14 Mar 2021 11:07:09 +0000 (12:07 +0100)]
clk: socfpga: fix iomem pointer cast on 64-bit
Pointers should be cast with uintptr_t instead of integer. This fixes
warning when compile testing on ARM64:
drivers/clk/socfpga/clk-gate.c: In function ‘socfpga_clk_recalc_rate’:
drivers/clk/socfpga/clk-gate.c:102:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
Geert Uytterhoeven [Fri, 26 Mar 2021 12:08:33 +0000 (13:08 +0100)]
clk: Drop double "if" in clk_core_determine_round_nolock() comment
The comments for clk_core_determine_round_nolock() contain a double
"if": one at the end of a line, followed by another one at the beginning
of the next line. Drop the former.
Elaine Zhang [Mon, 15 Mar 2021 08:56:07 +0000 (16:56 +0800)]
clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Elaine Zhang [Mon, 15 Mar 2021 08:56:06 +0000 (16:56 +0800)]
clk: rockchip: add dt-binding header for rk3568
Add the dt-bindings header for the rk3568, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3568.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210315085608.16010-3-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Douglas Anderson [Wed, 24 Feb 2021 17:50:25 +0000 (09:50 -0800)]
clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk
While picking commit a8cd989e1a57 ("mmc: sdhci-msm: Warn about
overclocking SD/MMC") back to my tree I was surprised that it was
reporting warnings. I thought I fixed those! Looking closer at the
fix, I see that I totally bungled it (or at least I halfway bungled
it). The SD card clock got fixed (and that was the one I was really
focused on fixing), but I totally adjusted the wrong clock for eMMC.
Sigh. Let's fix my dumb mistake.
Now both SD and eMMC have floor for the "apps" clock.
This doesn't matter a lot for the final clock rate for HS400 eMMC but
could matter if someone happens to put some slower eMMC on a sc7180.
We also transition through some of these lower rates sometimes and
having them wrong could cause problems during these transitions.
These were the messages I was seeing at boot:
mmc1: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
mmc1: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz
mmc1: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz
Marijn Suijten [Tue, 2 Mar 2021 23:41:06 +0000 (00:41 +0100)]
clk: qcom: rcg2: Rectify clk_gfx3d rate rounding without mux division
In case the mux is not divided parent_req was mistakenly not assigned to
leading __clk_determine_rate to determine the best frequency setting for
a requested rate of 0, resulting in the msm8996 platform not booting.
Rectify this by refactoring the logic to unconditionally assign to
parent_req.rate with the clock rate the caller is expecting.
Fixes: 7cbb78a99db6 ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers") Reported-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210302234106.3418665-1-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/sunxi/clk-sun9i-core.c:27: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_pll4_factors'
drivers/clk/sunxi/clk-sun9i-core.c:100: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_gt_factors'
drivers/clk/sunxi/clk-sun9i-core.c:155: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_ahb_factors'
drivers/clk/sunxi/clk-sun9i-core.c:235: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_apb1_factors'
drivers/clk/sunxi/clk-usb.c:22: warning: cannot understand function prototype: 'struct usb_reset_data '
drivers/clk/sunxi/clk-sun6i-ar100.c:26: warning: Function parameter or member 'req' not described in 'sun6i_get_ar100_factors'
Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@siol.net> Cc: Boris BREZILLON <boris.brezillon@free-electrons.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210303142430.3168703-1-lee.jones@linaro.org
Tobias Schramm [Thu, 18 Feb 2021 11:20:01 +0000 (12:20 +0100)]
clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll
Previously it was not possible to achieve clock rates of 24.576MHz and
22.5792MHz, which are commonly required core clocks for the i2s
peripheral of v3s based SoCs.
Add support for those clock rates through the audio pll's sigma-delta
modulator.
Linus Torvalds [Sat, 6 Mar 2021 01:27:59 +0000 (17:27 -0800)]
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Pull rdma fixes from Jason Gunthorpe:
"Nothing special here, though Bob's regression fixes for rxe would have
made it before the rc cycle had there not been such strong winter
weather!
- Fix corner cases in the rxe reference counting cleanup that are
causing regressions in blktests for SRP
- Two kdoc fixes so W=1 is clean
- Missing error return in error unwind for mlx5
- Wrong lock type nesting in IB CM"
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma:
RDMA/rxe: Fix errant WARN_ONCE in rxe_completer()
RDMA/rxe: Fix extra deref in rxe_rcv_mcast_pkt()
RDMA/rxe: Fix missed IB reference counting in loopback
RDMA/uverbs: Fix kernel-doc warning of _uverbs_alloc
RDMA/mlx5: Set correct kernel-doc identifier
IB/mlx5: Add missing error code
RDMA/rxe: Fix missing kconfig dependency on CRYPTO
RDMA/cm: Fix IRQ restore in ib_send_cm_sidr_rep
Linus Torvalds [Sat, 6 Mar 2021 01:23:03 +0000 (17:23 -0800)]
Merge tag 'gcc-plugins-v5.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux
Pull gcc-plugins fixes from Kees Cook:
"Tiny gcc-plugin fixes for v5.12-rc2. These issues are small but have
been reported a couple times now by static analyzers, so best to get
them fixed to reduce the noise. :)
- Fix coding style issues (Jason Yan)"
* tag 'gcc-plugins-v5.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
gcc-plugins: latent_entropy: remove unneeded semicolon
gcc-plugins: structleak: remove unneeded variable 'ret'
Linus Torvalds [Sat, 6 Mar 2021 01:21:25 +0000 (17:21 -0800)]
Merge tag 'pstore-v5.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux
Pull pstore fixes from Kees Cook:
- Rate-limit ECC warnings (Dmitry Osipenko)
- Fix error path check for NULL (Tetsuo Handa)
* tag 'pstore-v5.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
pstore/ram: Rate-limit "uncorrectable error in header" message
pstore: Fix warning in pstore_kill_sb()
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