Stephen Boyd [Mon, 6 Oct 2025 17:56:46 +0000 (12:56 -0500)]
Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next
* clk-samsung:
clk: s2mps11: add support for S2MPG10 PMIC clock
dt-bindings: clock: samsung,s2mps11: add s2mpg10
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
* clk-tegra:
clk: tegra: dfll: Add CVB tables for Tegra114
clk: tegra: Add DFLL DVCO reset control for Tegra114
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
* clk-amlogic:
clk: amlogic: fix recent code refactoring
clk: amlogic: c3-peripherals: use helper for basic composite clocks
clk: amlogic: align s4 and c3 pwm clock descriptions
clk: amlogic: add composite clock helpers
clk: amlogic: use the common pclk definition
clk: amlogic: introduce a common pclk definition
clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
clk: amlogic: move PCLK definition to clkc-utils
clk: amlogic: aoclk: use clkc-utils syscon probe
clk: amlogic: use probe helper in mmio based controllers
clk: amlogic: add probe helper for mmio based controllers
clk: amlogic: drop meson-clkcee
clk: amlogic: naming consistency alignment
clk: tegra: do not overallocate memory for bpmp clocks
struct tegra_bpmp::clocks is a pointer to a dynamically allocated array
of pointers to 'struct tegra_bpmp_clk'.
But the size of the allocated area is calculated like it is an array
containing actual 'struct tegra_bpmp_clk' objects - it's not true, there
are just pointers.
Found by Linux Verification Center (linuxtesting.org) with Svace static
analysis tool.
Fixes: 2db12b15c6f3 ("clk: tegra: Register clocks from root to leaf") Signed-off-by: Fedor Pchelkin <pchelkin@ispras.ru> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Qianfeng Rong [Sat, 30 Aug 2025 12:27:52 +0000 (20:27 +0800)]
clk: ep93xx: Use int type to store negative error codes
Change the 'ret' variable in ep93xx_uart_clock_init() from unsigned int to
int, as it needs to store either negative error codes or zero.
Storing the negative error codes in unsigned type, doesn't cause an issue
at runtime but can be confusing. Additionally, assigning negative error
codes to unsigned type may trigger a GCC warning when the -Wsign-conversion
flag is enabled.
No effect on runtime.
Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
André Draszik [Wed, 30 Jul 2025 09:31:35 +0000 (10:31 +0100)]
clk: s2mps11: add support for S2MPG10 PMIC clock
Add support for Samsung's S2MPG10 PMIC clock, which is similar to the
existing PMIC clocks supported by this driver.
S2MPG10 has three clock outputs @ 32kHz: AP, peri1 and peri2.
Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
André Draszik [Wed, 30 Jul 2025 09:31:34 +0000 (10:31 +0100)]
dt-bindings: clock: samsung,s2mps11: add s2mpg10
The Samsung S2MPG10 clock controller is similar to the existing clock
controllers supported by this binding. Register offsets / layout are
slightly different, so it needs its own compatible.
Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
st/stih407-clock.dtsi file has been removed in commit 65322c1daf51
("clk: st: flexgen: remove unused compatible"). This file has three
compatibles which are now dangling. Remove them from documentation.
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The mt8183-mfgcfg node uses a power domain in its device tree node.
To prevent schema validation warnings, add the optional `power-domains`
property to the binding schema for mediatek syscon clocks.
Fixes: 1781f2c46180 ("arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Marek Szyprowski [Thu, 18 Sep 2025 16:06:01 +0000 (18:06 +0200)]
clk: amlogic: fix recent code refactoring
Commit 4c4e17f27013 ("clk: amlogic: naming consistency alignment")
refactored some internals in the g12a meson clock driver. Unfortunately
it introduced a bug in the clock init data, which results in the
following kernel panic:
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
Mem abort info:
...
Data abort info:
...
[0000000000000000] user address but active_mm is swapper
Internal error: Oops: 0000000096000004 [#1] SMP
Modules linked in:
CPU: 4 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.17.0-rc1+ #11158 PREEMPT
Hardware name: Hardkernel ODROID-N2 (DT)
pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : __clk_register+0x60/0x92c
lr : __clk_register+0x48/0x92c
...
Call trace:
__clk_register+0x60/0x92c (P)
devm_clk_hw_register+0x5c/0xd8
meson_eeclkc_probe+0x74/0x110
g12a_clkc_probe+0x2c/0x58
platform_probe+0x5c/0xac
really_probe+0xbc/0x298
__driver_probe_device+0x78/0x12c
driver_probe_device+0xdc/0x164
__driver_attach+0x9c/0x1ac
bus_for_each_dev+0x74/0xd0
driver_attach+0x24/0x30
bus_add_driver+0xe4/0x208
driver_register+0x60/0x128
__platform_driver_register+0x24/0x30
g12a_clkc_driver_init+0x1c/0x28
do_one_initcall+0x64/0x308
kernel_init_freeable+0x27c/0x4f8
kernel_init+0x20/0x1d8
ret_from_fork+0x10/0x20
Code: 52800038aa0003fcb901001852819801 (f9400260)
---[ end trace 0000000000000000 ]---
Fix this by correcting the clock init data.
Fixes: 4c4e17f27013 ("clk: amlogic: naming consistency alignment") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on BananPi M2S Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add "clock-output-names" which is a standard property for clock
providers.
Add the "always-on" boolean property which was undocumented, but
already in use for some time. The flag prevents a clock output from
being disabled.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* tag 'clk-meson-v6.18-1' of https://github.com/BayLibre/clk-meson:
clk: amlogic: c3-peripherals: use helper for basic composite clocks
clk: amlogic: align s4 and c3 pwm clock descriptions
clk: amlogic: add composite clock helpers
clk: amlogic: use the common pclk definition
clk: amlogic: introduce a common pclk definition
clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
clk: amlogic: move PCLK definition to clkc-utils
clk: amlogic: aoclk: use clkc-utils syscon probe
clk: amlogic: use probe helper in mmio based controllers
clk: amlogic: add probe helper for mmio based controllers
clk: amlogic: drop meson-clkcee
clk: amlogic: naming consistency alignment
Stephen Boyd [Tue, 16 Sep 2025 01:11:00 +0000 (18:11 -0700)]
Merge tag 'for-6.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull Tegra clk driver updates from Thierry Reding:
- Add DFLL support on Tegra114
This is quite similar to the existing Tegra124 support and most
of the code can be reused, except for the CVB frequency tables.
* tag 'for-6.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: dfll: Add CVB tables for Tegra114
clk: tegra: Add DFLL DVCO reset control for Tegra114
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
Stephen Boyd [Sat, 13 Sep 2025 22:06:14 +0000 (15:06 -0700)]
Merge tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:
- Tesla FSD: Expose CSI clocks to consumers (DTS)
- Exynos990:
- Few fixes for fixed factor clocks, register widths and proper PLL
parents
- Add four more clocks for the DPU and HSI0 clock for USB
- Add PERIC0 and PERIC1 clock controllers (CMU), responsible for
providing clocks to serial engines
- Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC
shares all main blocks, including the clock controllers, with Samsung
SoC, so same drivers and bindings are used.
- Cleanups: switch to clk_ops::determine_rate()
* tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
Stephen Boyd [Sat, 13 Sep 2025 22:04:11 +0000 (15:04 -0700)]
Merge tag 'spacemit-clk-for-6.18-1' of https://github.com/spacemit-com/linux into clk-spacemit
Pull RISC-V SpacemiT clk driver updates from Yixun Lan:
- Convert to use clk_ops::determine_rate()
- Fix parent clocks of SSPA in SpacemiT driver
* tag 'spacemit-clk-for-6.18-1' of https://github.com/spacemit-com/linux:
clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
clk: spacemit: fix sspax_clk
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
Stephen Boyd [Sat, 13 Sep 2025 21:56:54 +0000 (14:56 -0700)]
Merge tag 'thead-clk-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead
Pull T-HEAD clock driver updates from Drew Fustini:
- Describe gate clocks with clk_gate so that clock gates can be clock
parents. This is similar to the mux clock refactor in 54edba916e29
("clk: thead: th1520-ap: Describe mux clocks with clk_mux").
- Add support for enabling/disabling PLLs. Some PLLs are put into a
disabled state by the bootloader, and clock driver now has the
ability to enable them.
- Set all AXI clocks to CLK_IS_CRITICAL. The AXI crossbar of TH1520 has
no proper timeout handling, which means gating AXI clocks can easily
lead to bus timeout and hang the system. All these clock gates are
ungated by default on system reset.
- Convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to
prevent unwanted clock gating.
- Fix parent of padctrl0 clock, fix parent of DPU pixel clocks and
support changing DPU pixel clock rate.
* tag 'thead-clk-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
clk: thead: support changing DPU pixel clock rate
clk: thead: add support for enabling/disabling PLLs
clk: thead: Correct parent for DPU pixel clocks
clk: thead: th1520-ap: fix parent of padctrl0 clock
clk: thead: th1520-ap: describe gate clocks with clk_gate
Stephen Boyd [Sat, 13 Sep 2025 21:33:10 +0000 (14:33 -0700)]
Merge tag 'renesas-clk-for-v6.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add Ethernet clocks on Renesas RZ/T2H and RZ/N2H
- Add USB3.0 clocks and resets on Renesas RZ/G3E
- Add I3C clocks and resets on Renesas RZ/V2H and RZ/V2N
- Add USB and remaining serial (SCI) clocks and resets on Renesas
RZ/T2H and RZ/N2H
- Add I3C and PCIe clocks and resets on Renesas RZ/G3S
- Add DMAC and PWM (GPT) clocks and resets on Renesas RZ/G3E
- Add Module Stop (MSTOP) support on RZ/G2L and Renesas RZ/G2UL
- Convert from clk_ops::round_rate() to clk_ops::determine_rate()
* tag 'renesas-clk-for-v6.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (27 commits)
clk: renesas: r9a09g05[67]: Reduce differences
clk: renesas: r9a09g047: Add USB3.0 clocks/resets
clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
clk: renesas: r9a09g056: Add clock and reset entries for I3C
clk: renesas: r9a09g057: Add clock and reset entries for I3C
dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks
clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()
clk: renesas: rzv2h: Re-assert reset on deassert timeout
clk: renesas: rzg2l: Re-assert reset on deassert timeout
clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()
dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs
clk: renesas: r9a09g047: Add GPT clocks and resets
clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()
clk: renesas: rzg2l: convert from round_rate() to determine_rate()
clk: renesas: r9a07g04[34]: Use tabs instead of spaces
clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL
clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
clk: renesas: r9a08g045: Add MSTOP for GPIO
...
The clock drivers for RZ/V2H and RZ/V2N are very similar.
Reduce the differences between them by:
- Moving and reformatting the PLLCM33_GEAR clock definitions,
- Replacing spaces by TABs.
clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
In case of krealloc_array() failure, the current error handling just
returns from the function without freeing the original array.
Fix this memory leak by freeing the original array.
Svyatoslav Ryhel [Fri, 29 Aug 2025 12:22:32 +0000 (15:22 +0300)]
clk: tegra: Add DFLL DVCO reset control for Tegra114
The DVCO present in the DFLL IP block has a separate reset line, exposed
via the CAR IP block. This reset line is asserted upon SoC reset.
Unless something (such as the DFLL driver) deasserts this line, the DVCO
will not oscillate, although reads and writes to the DFLL IP block will
complete.
Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124")
Svyatoslav Ryhel [Fri, 29 Aug 2025 12:22:31 +0000 (15:22 +0300)]
dt-bindings: reset: Add Tegra114 CAR header
The way that resets are handled on these Tegra devices is that there is a
set of peripheral clocks & resets which are paired up. This is because they
are laid out in banks within the CAR (clock and reset) controller. In most
cases we're referring to those resets, so you'll often see a clock ID used
in conjection with the same reset ID for a given IP block.
In addition to those peripheral resets, there are a number of extra resets
that don't have a corresponding clock and which are exposed in registers
outside of the peripheral banks, but still part of the CAR. To support
those "special" registers, the TEGRA*_RESET() is used to denote resets
outside of the regular peripheral resets. Essentially it defines the offset
within the CAR at which special resets start. In the above case, Tegra114
has 5 banks with 32 peripheral resets each. The first special reset,
TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0 = 160.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
The avdd-dsi-csi-supply is CSI power supply, it has nothing to do with
VI, like same supply is used with DSI and has nothing to do with DC.
Move it to correct place.
Tegra264 has 17 generic I2C controllers, two of which are in always-on
partition of the SoC. In addition to the features supported by Tegra194
it also supports a SW mutex register to allow sharing the same I2C
instance across multiple firmware.
Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C.
Jerome Brunet [Mon, 25 Aug 2025 14:26:35 +0000 (16:26 +0200)]
clk: amlogic: add composite clock helpers
Device composite clocks tend to reproduce the usual sel/div/gate
arrangement.
Add macros to help define simple composite clocks in the system.
The idea is _not_ to replace all instances of mux, div or gate with those
macros. It is rather to use it for recurring and/or simple composite
clocks, reducing controller verbosity where it makes sense. This should
help reviews focus on the tricky parts.
Jerome Brunet [Mon, 25 Aug 2025 14:26:32 +0000 (16:26 +0200)]
clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
Every usage of CLK_IGNORE_UNUSED should be explicitly motivated and
documented. However, the PCLK macros used by most Amlogic platforms are
adding that flag systematically. Because of this, all pclks are marked with
CLK_IGNORE_UNUSED, without any form of distinction or motivation.
This may have been fine in the early days of CCF but it is not anymore.
Just removing the flag is not an option at this stage since it could cause
regression on existing platforms.
Instead, drop the flag from the macro definition and add it to the each
clock definition, for the existing clocks. This makes quite a nasty change
but it will make it a lot easier for people to contribute to fixing the
problem, clock by clock. It will also prevent new platform from being added
with a silent use of the flag.
Jerome Brunet [Mon, 25 Aug 2025 14:26:31 +0000 (16:26 +0200)]
clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
On Amlogic SoCs, the rate of a peripheral clock should not be changed,
let alone the rate of the parent PLL.
These clocks are meant to be used as provided by the parent PLL. Changing
the rate would be dangerous and would likely break a lot of devices running
from the same PLL.
Don't propagate any rate change request that may come from these clocks and
drop the corresponding flag.
Jerome Brunet [Mon, 25 Aug 2025 14:26:30 +0000 (16:26 +0200)]
clk: amlogic: move PCLK definition to clkc-utils
clk-regmap was always meant to stay generic, without any amlogic specifics.
The hope was that it could move out of the amlogic directory one day.
Even if this may actually not become true, it should remain generic.
Move the amlogic peripheral clock definition out of clk-regmap header.
Jerome Brunet [Mon, 25 Aug 2025 14:26:28 +0000 (16:26 +0200)]
clk: amlogic: use probe helper in mmio based controllers
Factorize the probe function of the mmio based amlogic clock controllers
using the newly introduced probe helper. This removes a fair amount
of duplicated code.
Jerome Brunet [Mon, 25 Aug 2025 14:26:26 +0000 (16:26 +0200)]
clk: amlogic: drop meson-clkcee
What is being done by the Amlogic clock controller registration helper for
EE controllers could benefit other controllers. As such, having a specific
module for this makes little sense.
Move the helper function to clkc-utils and rename it to describe what it
does, registering syscon based controller, instead of what it serves.
Denzeel Oliva [Sun, 31 Aug 2025 12:13:14 +0000 (12:13 +0000)]
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
Add the missing LHS_ACEL clock ID for the HSI0 block. This clock is
required for proper USB operation, as without it, USB connections fail
with errors like device descriptor read timeouts and address response
issues.
clk: renesas: rzv2h: Re-assert reset on deassert timeout
Prevent issues during reset deassertion by re-asserting the reset if a
timeout occurs when trying to deassert. This ensures the reset line is in a
known state and improves reliability for hardware that may not immediately
clear the reset monitor bit.
clk: renesas: rzg2l: Re-assert reset on deassert timeout
Prevent issues during reset deassertion by re-asserting the reset if a
timeout occurs when trying to deassert. This ensures the reset line is in a
known state and improves reliability for hardware that may not immediately
clear the reset monitor bit.
clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()
Combine common code from rzg2l_cpg_assert() and rzg2l_cpg_deassert() into a
new __rzg2l_cpg_assert() helper to avoid code duplication. This reduces
maintenance effort and improves code clarity.
Add clock definitions for Ethernet (ETCLK A-E) to both R9A09G077 and
R9A09G087 SoCs. These definitions are required for describing Ethernet
devices in DT.
Hakyeong Kim [Mon, 25 Aug 2025 11:44:28 +0000 (17:14 +0530)]
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
Add below clock PLL support for Axis ARTPEC-8 SoC platform:
- pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz)
This is used in ARTPEC-8 SoC for shared PLL
- pll_1031x: Integer/Fractional PLL with mid frequency FVCO
(600 to 1200 MHz)
This is used in ARTPEC-8 SoC for Audio PLL
FOUT calculation for pll_1017x and pll_1031x:
FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
FOUT = (((MDIV + KDIV)/65536) x FIN)/(PDIV x 2^SDIV) for fractional PLL
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250825114436.46882-3-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Denzeel Oliva [Sat, 30 Aug 2025 16:28:42 +0000 (16:28 +0000)]
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
Add DPU_BUS and CMUREF mux/div, wire their registers and parents,
and update CLKS_NR_TOP. These use the new IDs appended to the
bindings to avoid ABI changes.
Denzeel Oliva [Sat, 30 Aug 2025 16:28:40 +0000 (16:28 +0000)]
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
HSI1/2 PCIe and HSI0 USBDP debug outputs are fixed divide-by-8.
OTP also uses 1/8 from oscclk. Replace incorrect div clocks with
fixed-factor clocks to reflect hardware.
Brian Masney [Mon, 11 Aug 2025 15:18:43 +0000 (11:18 -0400)]
clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Mon, 11 Aug 2025 15:18:42 +0000 (11:18 -0400)]
clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Mon, 11 Aug 2025 15:18:41 +0000 (11:18 -0400)]
clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Amlogic clock controller drivers are all doing the same thing, more or
less. Yet, over the years, tiny (and often pointless) differences have
emerged.
This makes reviews more difficult, allows some errors to slip through and
make it more difficult to exploit SoC commonalities, leading to code
duplication.
This change enforce, wherever possible, a consistent and predictable scheme
when it comes to code organisation and naming, The scheme chosen is what
was used the most already, to try and minimise the size of the ugly
resulting diff. Here are some of the rules applied:
- Aligning clock names, variable names and IDs.
- ID cannot change (used in DT)
- Variable names w/ SoC name prefixes
- Clock names w/o SoC name prefixes, except pclks for historic reasons
- Composite clock systematic naming : mux: X_sel, div:X_div, gate:X
- Parent table systematically named with the same name as the clock and
a '_parents' suffix
- Group various tables next to the related clock
- etc ...
Doing so removes what would otherwise show up as unrelated diff in
following changes. It will allow to introduce common definitions for
peripheral clocks, probe helpers, composite clocks, etc ... making further
review and maintenance easier.
Troy Mitchell [Mon, 11 Aug 2025 13:40:34 +0000 (21:40 +0800)]
clk: spacemit: fix sspax_clk
Hardware Requirement:
BIT[3] of this register must be set if need to select i2s_bclk as
SSPA parent clock, to solve this, introduces a new SSPAx_I2S_BCLK
clock as the virtual gate clock.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Suggested-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Haylen Chu <heylenay@4d2.org> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20250811-k1-clk-i2s-v5-2-ebadd06e1e91@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
Brian Masney [Mon, 11 Aug 2025 15:19:31 +0000 (11:19 -0400)]
clk: samsung: pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Mon, 11 Aug 2025 15:19:30 +0000 (11:19 -0400)]
clk: samsung: cpu: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Mon, 11 Aug 2025 15:19:25 +0000 (11:19 -0400)]
clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()
This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.
Brian Masney [Mon, 11 Aug 2025 15:19:24 +0000 (11:19 -0400)]
clk: renesas: rzg2l: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Geert Uytterhoeven [Wed, 20 Aug 2025 07:16:19 +0000 (09:16 +0200)]
Merge tag 'renesas-r9a09g077-dt-binding-defs-tag3' into renesas-clk-for-v6.18
Renesas RZ/T2H and RZ/N2H USB_CLK and Pin Control DT Binding Definitions
USB_CLK Clock and Pin Control DT binding definitions for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT
source files.
clk: renesas: r9a08g045: Add PCIe clocks and resets
Add clocks and resets for the PCIe IP available on the Renesas RZ/G3S
SoC. The clkl1pm clock is required for PCIe link power management (PM)
control and should be enabled based on the state of the CLKREQ# pin.
Therefore, mark it as a no_pm clock to allow the PCIe driver to manage
it during link PM transitions.
Icenowy Zheng [Sat, 16 Aug 2025 09:11:12 +0000 (17:11 +0800)]
clk: thead: support changing DPU pixel clock rate
The DPU pixel clock rate corresponds to the required dot clock of the
display mode, so it needs to be tweakable.
Add support to change it, by adding generic divider setting code,
arming the code to the dpu0/dpu1 clocks, and setting the pixel clock
connected to the DPU (after a gate) to CLK_SET_RATE_PARENT to propagate
it to the dividers.
Icenowy Zheng [Sat, 16 Aug 2025 09:11:11 +0000 (17:11 +0800)]
clk: thead: add support for enabling/disabling PLLs
The 2nd control word of T-Head TH1520 PLLs contains a bit to put the VCO
into reset state, which means disabling the PLL.
Some PLLs are put to disabled state by the bootloader, and the clock
driver should be able to enable them.
Add support for enabling/disabling PLLs. PLLs other than DPU ones are
set CLK_IS_CRITICAL to prevent killing the system -- they're meant to
drive CPU or system buses (even the GMAC/Video ones are driving arbitrary
buses).
Michal Wilczynski [Sat, 16 Aug 2025 09:11:10 +0000 (17:11 +0800)]
clk: thead: Correct parent for DPU pixel clocks
The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to
the video_pll_clk.
According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from
"DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to
the `dpu0_clk` clock, which is a divider whose parent is the
`dpu0_pll_clk`.
This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk`
to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its
correct source, `dpu1_clk`.
Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC") Reported-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
[Icenowy: add Drew's R-b and rebased atop ccu_gate refactor] Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Drew Fustini <fustini@kernel.org>
Icenowy Zheng [Sat, 16 Aug 2025 08:44:44 +0000 (16:44 +0800)]
clk: thead: th1520-ap: describe gate clocks with clk_gate
Similar to previous situation of mux clocks, the gate clocks of
clk-th1520-ap drivers are also using a helper that creates a temporary
struct clk_hw and abandons the struct clk_hw in struct ccu_common, which
prevents clock gates to be clock parents.
Do the similar refactor of dropping struct ccu_common and directly use
struct clk_gate here.
This patch mimics the refactor done on struct ccu_mux in 54edba916e29
("clk: thead: th1520-ap: Describe mux clocks with clk_mux").
Inbaraj E [Thu, 14 Aug 2025 14:09:33 +0000 (19:39 +0530)]
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
Add clock id for PCLK and PLL. These clock id will be used for
operation of CSI driver. PCLK is AXI2APB clock used for register
access. PLL clock is main clock source for CAM_CSI block.
Inbaraj E [Thu, 14 Aug 2025 14:09:32 +0000 (19:39 +0530)]
dt-bindings: clock: Add CAM_CSI clock macro for FSD
CAM_CSI block has ACLK, PCLK and PLL clocks. PCLK id is already
assigned. To use PCLK and PLL clock in driver add id macro for CAM_CSI_PLL
and CAM_CSI_PCLK.
Geert Uytterhoeven [Wed, 13 Aug 2025 08:20:22 +0000 (10:20 +0200)]
clk: renesas: mstp: Add genpd OF provider at postcore_initcall()
Genpd OF providers must now be registered after genpd bus registration.
However, cpg_mstp_add_clk_domain() is only called from CLK_OF_DECLARE(),
which is too early. Hence on R-Car M1A, R-Car H1, and RZ/A1, the
CPG/MSTP Clock Domain fails to register, and any devices residing in
that clock domain fail to probe.
Fix this by splitting initialization into two steps:
- The first part keeps on registering the PM domain with genpd at
CLK_OF_DECLARE(),
- The second and new part moves the registration of the genpd OF
provider to a postcore_initcall().
See also commit c5ae5a0c61120d0c ("pmdomain: renesas: rcar-sysc: Add
genpd OF provider at postcore_initcall").
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