David Gow [Fri, 25 Feb 2022 04:15:02 +0000 (12:15 +0800)]
firmware: google: Properly state IOMEM dependency
The Google Coreboot implementation requires IOMEM functions
(memmremap, memunmap, devm_memremap), but does not specify this is its
Kconfig. This results in build errors when HAS_IOMEM is not set, such as
on some UML configurations:
/usr/bin/ld: drivers/firmware/google/coreboot_table.o: in function `coreboot_table_probe':
coreboot_table.c:(.text+0x311): undefined reference to `memremap'
/usr/bin/ld: coreboot_table.c:(.text+0x34e): undefined reference to `memunmap'
/usr/bin/ld: drivers/firmware/google/memconsole-coreboot.o: in function `memconsole_probe':
memconsole-coreboot.c:(.text+0x12d): undefined reference to `memremap'
/usr/bin/ld: memconsole-coreboot.c:(.text+0x17e): undefined reference to `devm_memremap'
/usr/bin/ld: memconsole-coreboot.c:(.text+0x191): undefined reference to `memunmap'
/usr/bin/ld: drivers/firmware/google/vpd.o: in function `vpd_section_destroy.isra.0':
vpd.c:(.text+0x300): undefined reference to `memunmap'
/usr/bin/ld: drivers/firmware/google/vpd.o: in function `vpd_section_init':
vpd.c:(.text+0x382): undefined reference to `memremap'
/usr/bin/ld: vpd.c:(.text+0x459): undefined reference to `memunmap'
/usr/bin/ld: drivers/firmware/google/vpd.o: in function `vpd_probe':
vpd.c:(.text+0x59d): undefined reference to `memremap'
/usr/bin/ld: vpd.c:(.text+0x5d3): undefined reference to `memunmap'
collect2: error: ld returned 1 exit status
Fixes: a28aad66da8b ("firmware: coreboot: Collapse platform drivers into bus core") Acked-By: anton ivanov <anton.ivanov@cambridgegreys.com> Acked-By: Julius Werner <jwerner@chromium.org> Signed-off-by: David Gow <davidgow@google.com> Link: https://lore.kernel.org/r/20220225041502.1901806-1-davidgow@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Randy Dunlap [Tue, 8 Mar 2022 03:32:55 +0000 (19:32 -0800)]
kgdbts: fix return value of __setup handler
__setup() handlers should return 1 to indicate that the boot option
has been handled. A return of 0 causes the boot option/value to be
listed as an Unknown kernel parameter and added to init's (limited)
environment strings. So return 1 from kgdbts_option_setup().
Unknown kernel command line parameters "BOOT_IMAGE=/boot/bzImage-517rc7
kgdboc=kbd kgdbts=", will be passed to user space.
Run /sbin/init as init process
with arguments:
/sbin/init
with environment:
HOME=/
TERM=linux
BOOT_IMAGE=/boot/bzImage-517rc7
kgdboc=kbd
kgdbts=
Link: lore.kernel.org/r/64644a2f-4a20-bab3-1e15-3b2cdd0defe3@omprussia.ru Fixes: e8d31c204e36 ("kgdb: add kgdb internal test suite") Cc: kgdb-bugreport@lists.sourceforge.net Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reported-by: Igor Zhbanov <i.zhbanov@omprussia.ru> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20220308033255.22118-1-rdunlap@infradead.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Ang Tien Sung [Wed, 23 Feb 2022 14:41:46 +0000 (08:41 -0600)]
firmware: stratix10-svc: add missing callback parameter on RSU
Fix a bug whereby, the return response of parameter a1 from an
SMC call is not properly set to the callback data during an
INTEL_SIP_SMC_RSU_ERROR command.
Jeya R [Mon, 14 Feb 2022 16:10:02 +0000 (16:10 +0000)]
arm64: dts: qcom: add non-secure domain property to fastrpc nodes
FastRPC DSP domain would be set as secure if non-secure dsp property is not
added to the fastrpc DT node. Add this property to DT files of msm8916,
sdm845, sm8150, sm8250 and sm8350 so that nothing is broken after secure
domain patchset.
This patch is purely for backward compatibility reasons.
This patch adds support to secure memory allocations for DSP.
It repurposes the reserved field in struct fastrpc_invoke_args
to add attributes to invoke request, for example to setup a secure memory
map for dsp. Secure memory is assigned to DSP Virtual Machine IDs using
Qualcomm SCM calls.
Jeya R [Mon, 14 Feb 2022 16:09:56 +0000 (16:09 +0000)]
misc: fastrpc: check before loading process to the DSP
Reject session if DSP domain is secure, device node is non-secure and signed
PD is requested. Secure device node can access DSP without any restriction.
Unsigned PD offload is only allowed for the DSP domain that can support
unsigned offloading.
Srinivas Kandagatla [Mon, 14 Feb 2022 16:09:55 +0000 (16:09 +0000)]
misc: fastrpc: add secure domain support
ADSP/MDSP/SDSP are by default secured, which means it can only be loaded
with a Signed process.
Where as CDSP can be either be secured/unsecured. non-secured Compute DSP
would allow users to load unsigned process and run hexagon instructions,
but blocking access to secured hardware within the DSP. Where as signed
process with secure CDSP would be allowed to access all the dsp resources.
This patch adds basic code to create device nodes as per device tree property.
Jeya R [Mon, 14 Feb 2022 16:09:54 +0000 (16:09 +0000)]
dt-bindings: misc: add property to support non-secure DSP
Add property to set DSP domain as non-secure.
ADSP/MDSP/SDSP are by default secured, where as CDSP can be either be
secured/unsecured.
non-secured Compute DSP would allow users to load unsigned process
and run hexagon instructions, but limiting access to secured hardware
within the DSP.
Based on this flag device nodes for secured and unsecured are created.
Srinivas Kandagatla [Mon, 14 Feb 2022 16:09:51 +0000 (16:09 +0000)]
misc: fastrpc: separate fastrpc device from channel context
Currently fastrpc misc device instance is within channel context struct
with a kref. So we have 2 structs with refcount, both of them managing the
same channel context structure.
Separate fastrpc device from channel context and by adding a dedicated
fastrpc_device structure, this should clean the structures a bit and also help
when adding secure device node support.
NVRAM doesn't have cells at hardcoded addresses. They are stored in
internal struct (custom & dynamic format). It's still important to
define relevant cells in DT so NVMEM consumers can reference them.
Update binding to allow including basic cells as NVMEM device subnodes.
Rafał Miłecki [Fri, 25 Feb 2022 17:58:21 +0000 (17:58 +0000)]
dt-bindings: nvmem: make "reg" property optional
Most NVMEM providers have cells at hardcoded addresses however there are
some exceptions. Some devices store cells layout in internal structs
using custom formats.
It's important to allow NVMEM consumers to still reference such NVMEM
cells. Making "reg" optional allows defining NVMEM cells by their names
only and using them with phandles.
Vincent Shih [Fri, 25 Feb 2022 17:58:19 +0000 (17:58 +0000)]
nvmem: dt-bindings: Fix the error of dt-bindings check
1. Remove the unnecessary header file for dt-binding check
2. Replace OTPRX with 0x15 since it is not defined here.
3. Modify the name of the node of the clock driver.
Fixes: 8fb29b450182 ("dt-bindings: nvmem: Add bindings doc for Sunplus OCOTP driver") Reported-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Vincent Shih <vincent.sunplus@gmail.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20220225175822.8293-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Markus Reichl [Sun, 6 Mar 2022 14:58:08 +0000 (15:58 +0100)]
w1: w1_therm: Add support for Maxim MAX31850 thermoelement IF.
MAX31850 shares family number 0x3B with DS1825. The device is generally
compatible with DS1825 but needs a different temperature readout.
It operates always in 14 bit mode and has all 4 higher bits of the
Config register set to 1. Conversion time is 100ms.
Tom Rix [Tue, 15 Mar 2022 19:38:57 +0000 (15:38 -0400)]
counter: add defaults to switch-statements
Clang static analysis reports this representative problem
counter-chrdev.c:482:3: warning: Undefined or garbage value
returned to caller
return ret;
^~~~~~~~~~
counter_get_data() has a multilevel switches, some without
defaults, so ret is sometimes not set.
Add returning -EINVAL similar to other defaults.
William Breathitt Gray [Tue, 15 Mar 2022 19:38:53 +0000 (15:38 -0400)]
counter: Set counter device name
Naming the counter device provides a convenient way to identify it in
devres_log events and similar situations. This patch names the counter
device by combining the prefix "counter" with the counter device's
unique ID.
William Breathitt Gray [Tue, 15 Mar 2022 19:38:52 +0000 (15:38 -0400)]
counter: 104-quad-8: Add COMPILE_TEST depends
104_QUAD_8 depends on X86, but compiles fine on ARCH=arm. This patch
adds support for COMPILE_TEST which is useful for compile testing code
changes to the driver and Counter subsystem.
Manivannan Sadhasivam [Tue, 1 Mar 2022 16:03:08 +0000 (21:33 +0530)]
bus: mhi: Make mhi_state_str[] array static inline and move to common.h
mhi_state_str[] array could be used by MHI endpoint stack also. So let's
make the array as "static inline function" and move it inside the
"common.h" header so that the endpoint stack could also make use of it.
Manivannan Sadhasivam [Tue, 1 Mar 2022 16:03:07 +0000 (21:33 +0530)]
bus: mhi: Move common MHI definitions out of host directory
Move the common MHI definitions in host "internal.h" to "common.h" so
that the endpoint code can make use of them. This also avoids
duplicating the definitions in the endpoint stack.
Manivannan Sadhasivam [Tue, 1 Mar 2022 16:03:05 +0000 (21:33 +0530)]
bus: mhi: Cleanup the register definitions used in headers
Cleanup includes:
1. Using the GENMASK macro for masks
2. Removing brackets for single values
3. Using lowercase for hex values
4. Using two digits for hex values where applicable
5. Aligning the defines on same column
Manivannan Sadhasivam [Tue, 1 Mar 2022 16:03:03 +0000 (21:33 +0530)]
bus: mhi: Use bitfield operations for register read and write
Functions like mhi_read_reg_field(), mhi_poll_reg_field() and
mhi_write_reg_field() could be modified to not depend on the shift value
passed as an argument. Instead, the bitfield operation could be used to
extract the shift value from the mask itself.
This eliminates the need to define _SHIFT (and _SHFT) macros and
simplifies the code a bit. For shift values those cannot be determined
during build time, "__ffs()" helper is used find the shift value during
runtime.
While at it, let's also get rid of 32-bit masks like CHDBOFF_CHDBOFF_MASK
by doing the full 32-bit register read.
Paul Davey [Tue, 1 Mar 2022 16:03:01 +0000 (21:33 +0530)]
bus: mhi: Fix MHI DMA structure endianness
The MHI driver does not work on big endian architectures. The
controller never transitions into mission mode. This appears to be due
to the modem device expecting the various contexts and transfer rings to
have fields in little endian order in memory, but the driver constructs
them in native endianness.
Fix MHI event, channel and command contexts and TRE handling macros to
use explicit conversion to little endian. Mark fields in relevant
structures as little endian to document this requirement.
Fixes: a6e2e3522f29 ("bus: mhi: core: Add support for PM state transitions") Fixes: 6cd330ae76ff ("bus: mhi: core: Add support for ringing channel/event ring doorbells") Cc: stable@vger.kernel.org Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Paul Davey <paul.davey@alliedtelesis.co.nz> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-4-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Paul Davey [Tue, 1 Mar 2022 16:03:00 +0000 (21:33 +0530)]
bus: mhi: Fix pm_state conversion to string
On big endian architectures the mhi debugfs files which report pm state
give "Invalid State" for all states. This is caused by using
find_last_bit which takes an unsigned long* while the state is passed in
as an enum mhi_pm_state which will be of int size.
Fix by using __fls to pass the value of state instead of find_last_bit.
Also the current API expects "mhi_pm_state" enumerator as the function
argument but the function only works with bitmasks. So as Alex suggested,
let's change the argument to u32 to avoid confusion.
Fixes: a6e2e3522f29 ("bus: mhi: core: Add support for PM state transitions") Cc: stable@vger.kernel.org
[mani: changed the function argument to u32] Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Paul Davey <paul.davey@alliedtelesis.co.nz> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-3-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Yonglin Tan [Tue, 1 Mar 2022 16:02:59 +0000 (21:32 +0530)]
bus: mhi: pci_generic: Add mru_default for Quectel EM1xx series
For default mechanism, the driver uses default MRU 3500 if mru_default
is not initialized. The Qualcomm configured the MRU size to 32768 in the
WWAN device FW. So, we align the driver setting with Qualcomm FW setting.
Maciej W. Rozycki [Mon, 14 Feb 2022 20:16:50 +0000 (20:16 +0000)]
parport_pc: Also enable driver for PCI systems
Nowadays PC-style parallel ports come in the form of PCI and PCIe option
cards and there are some combined parallel/serial option cards as well
that we handle in the parport subsystem. There is nothing in particular
that would prevent them from being used in any system equipped with PCI
or PCIe connectivity, except that we do not permit the PARPORT_PC config
option to be selected for platforms for which ARCH_MIGHT_HAVE_PC_PARPORT
has not been set for.
The only PCI platforms that actually can't make use of PC-style parallel
port hardware are those newer PCIe systems that have no support for I/O
cycles in the host bridge, required by such parallel ports. Notably,
this includes the s390 arch, which has port I/O accessors that cause
compilation warnings (promoted to errors with `-Werror'), and there are
other cases such as the POWER9 PHB4 device, though this one has variable
port I/O accessors that depend on the particular system. Also it is not
clear whether the serial port side of devices enabled by PARPORT_SERIAL
uses port I/O or MMIO. Finally Super I/O solutions are always either
ISA or platform devices.
Make the PARPORT_PC option selectable also for PCI systems then, except
for the s390 arch, however limit the availability of PARPORT_PC_SUPERIO
to platforms that enable ARCH_MIGHT_HAVE_PC_PARPORT. Update platforms
accordingly for the required <asm/parport.h> header.
Andy Shevchenko [Thu, 10 Feb 2022 13:49:43 +0000 (15:49 +0200)]
pps: generators: pps_gen_parport: Switch to use module_parport_driver()
Switch to use module_parport_driver() to reduce boilerplate code.
Note, it doesn't matter when we check the module parameter. If it was
writable we even would have more flexibility of changing it at runtime
(when built-in the kernel) after this patch.
Lad Prabhakar [Wed, 9 Mar 2022 20:23:27 +0000 (20:23 +0000)]
platform: goldfish: pipe: Use platform_get_irq() to get the interrupt
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypasses the hierarchical setup and messes up the
irq chaining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Yonghua Huang [Mon, 28 Feb 2022 02:22:12 +0000 (05:22 +0300)]
virt: acrn: obtain pa from VMA with PFNMAP flag
acrn_vm_ram_map can't pin the user pages with VM_PFNMAP flag
by calling get_user_pages_fast(), the PA(physical pages)
may be mapped by kernel driver and set PFNMAP flag.
This patch fixes logic to setup EPT mapping for PFN mapped RAM region
by checking the memory attribute before adding EPT mapping for them.
Alexander Usyskin [Tue, 8 Mar 2022 09:59:26 +0000 (11:59 +0200)]
mei: avoid iterator usage outside of list_for_each_entry
Usage of the iterator outside of the list_for_each_entry
is considered harmful. https://lkml.org/lkml/2022/2/17/1032
Do not reference the loop variable outside of the loop,
by rearranging the orders of execution.
Instead of performing search loop and checking outside the loop
if the end of the list was hit and no matching element was found,
the execution is performed inside the loop upon a successful match
followed by a goto statement to the next step,
therefore no condition has to be performed after the loop has ended.
Vishnu Dasa [Fri, 18 Mar 2022 06:00:40 +0000 (23:00 -0700)]
VMCI: Release notification_bitmap in error path
notification_bitmap may not be released when VMCI_CAPS_DMA_DATAGRAM
capability is missing from the device. Add missing
'err_free_notification_bitmap' label and use it instead of
'err_free_data_buffers' to avoid this.
Vishnu Dasa [Fri, 18 Mar 2022 05:58:43 +0000 (22:58 -0700)]
VMCI: Check exclusive_vectors when freeing interrupt 1
free_irq() may be called to free an interrupt that was not
allocated. Add missing 'if' statement to check for
exclusive_vectors when freeing interrupt 1.
Eliminate anonymous module_init() and module_exit(), which can lead to
confusion or ambiguity when reading System.map, crashes/oops/bugs,
or an initcall_debug log.
Give each of these init and exit functions unique driver-specific
names to eliminate the anonymous names.
Greg Kroah-Hartman [Fri, 18 Mar 2022 11:49:10 +0000 (12:49 +0100)]
Merge tag 'coresight-next-v5.18-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
Suzuki writes:
coresight: changes for v5.18
The coresight update for v5.18 includes
- TRBE erratum workarounds for Arm Cortex-A510
- Fixes for leaking root namespace PIDs into non-root namespace
trace sessions
- Miscellaneous fixes and cleanups
Updated tag to reflect missing committer s-o-b tags.
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
* tag 'coresight-next-v5.18-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux:
coresight: Drop unused 'none' enum value for each component
coresight: etm3x: Don't trace PID for non-root PID namespace
coresight: etm4x: Don't trace PID for non-root PID namespace
coresight: etm4x: Don't use virtual contextID for non-root PID namespace
coresight: etm4x: Add lock for reading virtual context ID comparator
coresight: trbe: Move check for kernel page table isolation from EL0 to probe
coresight: no-op refactor to make INSTP0 check more idiomatic
hwtracing: coresight: Replace acpi_bus_get_device()
coresight: syscfg: Fix memleak on registration failure in cscfg_create_device
coresight: Fix TRCCONFIGR.QE sysfs interface
coresight: trbe: Work around the trace data corruption
coresight: trbe: Work around the invalid prohibited states
coresight: trbe: Work around the ignored system register writes
Greg Kroah-Hartman [Fri, 18 Mar 2022 11:41:32 +0000 (12:41 +0100)]
Merge tag 'iio-for-5.18a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
Jonathan writes:
First set of new device support, fixes, cleanups and features for IIO in 5.18
This cycle we had quite a few series that applied similar changes
to lots of drivers. To keep this description manageable I have
called those out in their own section rather than per driver.
Particularly pleased to see the long running AFE precision series
going in this cycle.
Series includes some late breaking fixes.
New device support
* adi,ada4250 amplifier
- New driver and dt bindings for this programmable gain amplifier.
* adi,admv1014 microwave down-converter
- New driver, dt bindings and some device specific ABI that
may be generalized as more drivers for devices similar to this
are added.
* adi,admv4420 K Band down-converter.
- New driver and dt bindings.
* adi,adxl367 accelerometer driver.
- New driver, dt-bindings + some new IIO ABI definitions to support
reference magnitude events where an estimate of the acceleration
due to gravity has been removed.
- A few fixes as follow up patches.
* adi,ltc2688 DAC with toggle and dither modes.
- New driver and bindings. Includes some new driver specific (for now)
ABI for handling toggle mode and the addition of a dither waveform to
the DAC output.
* AFE (analog front end) add support for additional types of analog device
in front of an ADC.
- RTD temperature sensors with dt bindings.
- Temperature transducers wit dt bindings.
- Related cleanup and features listed in other sections below.
* maxim,ds3502 potentiometer.
- Add support to ds1803 driver which required significant rework.
* mediatek,mt2701-auxadc driver
- Add mediatek,mt8186-auxadc - id table and chip specific info only.
* semtech,sx9324, semtech,ax9360
- Substantial refactoring of sx9310 to extract core logic for reuse
into a separate module
- New driver using this supporting sx9324 proximity sensors.
- New driver using this supporting sx9360 proximity sensors.
* silan,sc7a20
- Compatible with the st,lis2dh (or nearly anyway) so add ID and
chip specific info to enable support. Also silan vendor ID added
for dt-bindings.
Staging graduation
* adi,ad7280a monitoring ADC for stacked lithium-ion batteries in
electric cars and similar.
- Substantial rework of driver required to bring inline with current
IIO best practice. An unusual device in IIO so some interesting features
we may see more of in future.
Multiple driver/core cleanup
- Use sysfs_emit() in simple locations where there is no path to change
to various core created attributes.
- Trivial white space fixes around inconsistency between space after { and
before } in id tables.
- Introduce new handling for fractional types to avoid repeated similar
implementations. Use this in 3 drivers. Note this is also targeted
at future use in the AFE driver and was motivated by discussions
around the precision related work on that driver.
- of related header cleanups - drop of*.h and add mod_devicetable.h as
appropriate.
- Move a number of symbol exports into IIO_* namespaces. Two categories,
1) Library used by multiple drivers e.g. st_sensors
2) Core driver module exporting functions used by bus specific modules.
A few related cleanups in this set.
- Switch from CONFIG_PM_* guards to new DEFINE_SIMPLE_DEV_PM_OPS() and
similar to simplify drivers and take advantage of these new macros
allowing the compiler to do the job or removing unused code without
the need for __maybe_unused markings. Conversion of other drivers to
these new macros ongoing.
Features
* adi,adf4350
- Switch from of specific to generic device properties enabling use with
other firmware types.
* adi,adx345
- Switch from of specific to generic device properties.
- Add ACPI ID ADS0345
- Related driver cleanup.
* adi,hmc425a
- Switch from of specific to generic device properties.
* afe analog rescaler driver
- Wider range of types supported for scale.
- Support offset.
- Kunit tests.
* atlas,ezo-sensor
- Convert from of to device properties.
* fsl,mma8452
- Support mount matrix.
* infineon,dps310:
- Add ACPI ID IFX3100.
* invensense,mpu6050
- Convert to generic device properties.
* maxim,ds1803
- Add out_raw_available before supporting more devices.
- Convert from of specific to device properties.
* samsung,ssp_sensors
- Convert from of specific to device properties.
* st,stm32-timer trigger
- Convert from of specific to device properties.
* ti,hdc101x
- Add ACPI ID TXNW1010.
* ti,tsc2046:
- Add read_raw support to enable use of iio_hwmon and similar.
Fixes / cleanup.
* mailmap
- Update for Cai Huoqing
* MAINTAINERS
- Fix Analog Devices related links.
- Add entry for ADRF6780
- Add entry for ADMV1013
- Add entry for AD7293
- Add entry for ADMV8818
- Update files listed for adis-lib
* iio core:
- Fix wrong comment about current_mode being something a driver should
ever access.
- Use struct_size() rather than open coding in industrialio-hw-consumer
* adi,axl355
- Use units.h definitions instead of local versions.
* adi,adis-lib
- Simplify *updated_bits() macro
- Whitespace cleanup.
* afe - Note many of these fixes only apply to particular configurations
so the problems have probably not been seen in the wild, but will be
visible with new usecases enabled this cycle.
- Fix application of consumer scale for IIO_VAL_INT.
- Apply a scale of 1 when no scale is provided.
- Make best effort to establish a valid offset value for fractional
cases.
- Use s64 for scale calculations where parameters may be signed.
- Tidy up include order.
- Improve accuracy for small fractional sales
- Reduce risk of integer overflow.
* ams,as3935
- Use devm_delayed_work_autocancel() to replace open coded equivalent.
* aspeed,adc
- Fix wrong use of divider flag.
* atmel,sama5d2-adc
- Relax atmel,trigger-edge-type to optional.
- Drop Ludovic Desroches from listed maintainers of the dt-binding
inline with previous MAINTAINERS entry update.
* fsl,mma8452
- Fix probing when i2c_device_id used.
- dev_get_drvdata() on the iio_dev->dev, no longer returns iio_dev.
Use dev_to_iio_dev() instead. Note the original path in here
worked more by luck than design.
* invensense,mpu6050
- Drop ACPI_PTR() protection to avoid an unused warning.
- Use fact ACPI_COMPANION() returns null when ACPI_HANDLE() does to
simplify handling.
* motorola,cpcap-adc
- Drop unused assignment.
* qcom,spmi-adc
- Fix wrong example of 'reg' in binding document.
* renesas,rzg2l-adc
- Trivial typo fix.
* semtech,sx9360
- Fix wrong register handling for event generation.
* st_sensors
- Allow manual disabling of I2C or SPI module if not needed for a particular
board. Default is still to enable the bus specific module if
appropriate bus is supported.
* st,lsm6dsx
- dev_get_drvdata() on the iio_dev->dev, no longer returns iio_dev.
Use dev_to_iio_dev() instead.
* ti,palmas-gpadc
- Split the interrupt fields in the dt-binding example
* ti,tsc2046
- Rework state machine to improve readability after recent debugging of
an issue fixed elsewhere.
- Add a sanity check to avoid very large memory allocations if a crazy
delay is specified.
* ti,twl6030
- Add error handling if devm_request_threaded_irq() fails.
* xilinx,ams
- Use devm_delayed_work_autocancel() instead of open coding equivalent.
- Fix missing required clock entry in dt-binding.
- Fix miss counting of channels resulting in ps channels not
being enabled.
- Fix incorrect values written to sequencer registers.
- Fix sequence for single channel reading.
* tag 'iio-for-5.18a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio: (245 commits)
iio: adc: xilinx-ams: Fix single channel switching sequence
iio: adc: xilinx-ams: Fixed wrong sequencer register settings
iio: adc: xilinx-ams: Fixed missing PS channels
dt-bindings: iio: adc: zynqmp_ams: Add clock entry
iio: accel: mma8452: use the correct logic to get mma8452_data
iio: adc: aspeed: Add divider flag to fix incorrect voltage reading.
iio: imu: st_lsm6dsx: use dev_to_iio_dev() to get iio_dev struct
dt-bindings: iio: Add ltc2688 documentation
iio: ABI: add ABI file for the LTC2688 DAC
iio: dac: add support for ltc2688
dt-bindings: iio: afe: add bindings for temperature transducers
dt-bindings: iio: afe: add bindings for temperature-sense-rtd
iio: afe: rescale: add temperature transducers
iio: afe: rescale: add RTD temperature sensor support
iio: test: add basic tests for the iio-rescale driver
iio: afe: rescale: reduce risk of integer overflow
iio: afe: rescale: fix accuracy for small fractional scales
iio: afe: rescale: add offset support
iio: afe: rescale: add INT_PLUS_{MICRO,NANO} support
iio: afe: rescale: expose scale processing function
...
Greg Kroah-Hartman [Fri, 11 Mar 2022 15:40:10 +0000 (16:40 +0100)]
Merge tag 'icc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 5.18
These are the interconnect changes for the 5.18-rc1 merge window
consisting of minor framework and driver updates.
Core changes:
- Added stubs for the bulk API to expand compile testing coverage.
Driver changes:
- imx: Implemented get_bw() function to get initial avg/peak bandwidth.
- msm8939: Fix ioremap collision for snoc-mm.
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: Add stubs for the bulk API
interconnect: qcom: msm8939: Remove snoc_mm specific regmap
dt-bindings: interconnect: Convert snoc-mm to a sub-node of snoc
interconnect: imx: Add imx_icc_get_bw function to set initial avg and peak
Anshuman Khandual [Wed, 16 Feb 2022 09:51:58 +0000 (15:21 +0530)]
coresight: Drop unused 'none' enum value for each component
CORESIGHT_DEV_TYPE_NONE/CORESIGHT_DEV_SUBTYPE_XXXX_NONE values are not used
any where. Actual enumeration can start from 0. Just drop these unused enum
values.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/1645005118-10561-1-git-send-email-anshuman.khandual@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Leo Yan [Fri, 4 Feb 2022 15:24:03 +0000 (23:24 +0800)]
coresight: etm3x: Don't trace PID for non-root PID namespace
ETMv3 driver enables PID tracing by directly using perf config from
userspace, this means the tracer will capture PID packets from root
namespace but the profiling session runs in non-root PID namespace.
Finally, the recorded packets can mislead perf reporting with the
mismatched PID values.
This patch changes to only enable PID tracing for root PID namespace.
Note, the hardware supports VMID tracing from ETMv3.5, but the driver
never enables VMID trace, this patch doesn't handle VMID trace (bit 30
in ETMCR register) particularly.
Leo Yan [Fri, 4 Feb 2022 15:24:02 +0000 (23:24 +0800)]
coresight: etm4x: Don't trace PID for non-root PID namespace
When runs in perf mode, the driver always enables the PID tracing. This
can lead confusion when the profiling session runs in non-root PID
namespace, whereas it records the PIDs from the root PID namespace.
To avoid confusion for PID tracing, when runs in perf mode, this patch
changes to only enable PID tracing for root PID namespace.
As result, after apply this patch, the perf tool reports PID as '-1' for
all samples:
Leo Yan [Fri, 4 Feb 2022 15:24:01 +0000 (23:24 +0800)]
coresight: etm4x: Don't use virtual contextID for non-root PID namespace
As commented in the function ctxid_pid_store(), it can cause the PID
values mismatching between context ID tracing and PID allocated in a
non-root namespace.
For this reason, when a process runs in non-root PID namespace, the
driver doesn't allow PID tracing and returns failure when access
contextID related sysfs nodes.
VMID works for virtual contextID when the kernel runs in EL2 mode with
VHE; on the other hand, the driver doesn't prevent users from accessing
it when programs run in the non-root namespace. Thus this can lead
to same issues with contextID described above.
This patch imposes the checking on VMID related sysfs knobs and returns
failure if current process runs in non-root PID namespace.
Sudeep Holla [Thu, 3 Feb 2022 19:01:59 +0000 (19:01 +0000)]
coresight: trbe: Move check for kernel page table isolation from EL0 to probe
Currently with the check present in the module initialisation, it shouts
on all the systems irrespective of presence of coresight trace buffer
extensions.
Similar to Arm SPE perf driver, move the check for kernel page table
isolation from EL0 to the device probe stage instead of the module
initialisation so that it complains only on the systems that support TRBE.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: coresight@lists.linaro.org Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20220203190159.3145272-1-sudeep.holla@arm.com Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
James Clark [Thu, 3 Feb 2022 11:53:35 +0000 (11:53 +0000)]
coresight: no-op refactor to make INSTP0 check more idiomatic
The spec says this:
P0 tracing support field. The permitted values are:
0b00 Tracing of load and store instructions as P0 elements is not
supported.
0b11 Tracing of load and store instructions as P0 elements is
supported, so TRCCONFIGR.INSTP0 is supported.
All other values are reserved.
The value we are looking for is 0b11 so simplify this. The double read
and && was a bit obfuscated.
James Clark [Thu, 20 Jan 2022 11:30:47 +0000 (11:30 +0000)]
coresight: Fix TRCCONFIGR.QE sysfs interface
It's impossible to program a valid value for TRCCONFIGR.QE
when TRCIDR0.QSUPP==0b10. In that case the following is true:
Q element support is implemented, and only supports Q elements without
instruction counts. TRCCONFIGR.QE can only take the values 0b00 or 0b11.
Currently the low bit of QSUPP is checked to see if the low bit of QE can
be written to, but as you can see when QSUPP==0b10 the low bit is cleared
making it impossible to ever write the only valid value of 0b11 to QE.
0b10 would be written instead, which is a reserved QE value even for all
values of QSUPP.
The fix is to allow writing the low bit of QE for any non zero value of
QSUPP.
This change also ensures that the low bit is always set, even when the
user attempts to only set the high bit.
Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Fixes: d8c66962084f ("coresight-etm4x: Controls pertaining to the reset, mode, pe and events") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220120113047.2839622-2-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Anshuman Khandual [Tue, 25 Jan 2022 14:20:37 +0000 (19:50 +0530)]
coresight: trbe: Work around the trace data corruption
TRBE implementations affected by Arm erratum #1902691 might corrupt trace
data or deadlock, when it's being written into the memory. Workaround this
problem in the driver, by preventing TRBE initialization on affected cpus.
The firmware must have disabled the access to TRBE for the kernel on such
implementations. This will cover the kernel for any firmware that doesn't
do this already. This just updates the TRBE driver as required.
Anshuman Khandual [Tue, 25 Jan 2022 14:20:36 +0000 (19:50 +0530)]
coresight: trbe: Work around the invalid prohibited states
TRBE implementations affected by Arm erratum #2038923 might get TRBE into
an inconsistent view on whether trace is prohibited within the CPU. As a
result, the trace buffer or trace buffer state might be corrupted. This
happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E,
followed by just a single context synchronization event before execution
changes from a context, in which trace is prohibited to one where it isn't,
or vice versa. In these mentioned conditions, the view of whether trace is
prohibited is inconsistent between parts of the CPU, and the trace buffer
or the trace buffer state might be corrupted.
Work around this problem in the TRBE driver by preventing an inconsistent
view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by
immediately following a change to TRBLIMITR_EL1.E with at least one ISB
instruction before an ERET, or two ISB instructions if no ERET is to take
place. This just updates the TRBE driver as required.
Anshuman Khandual [Tue, 25 Jan 2022 14:20:35 +0000 (19:50 +0530)]
coresight: trbe: Work around the ignored system register writes
TRBE implementations affected by Arm erratum #2064142 might fail to write
into certain system registers after the TRBE has been disabled. Under some
conditions after TRBE has been disabled, writes into certain TRBE registers
TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be
ignored and not be effected.
Work around this problem in the TRBE driver by executing TSB CSYNC and DSB
just after the trace collection has stopped and before performing a system
register write to one of the affected registers. This just updates the TRBE
driver as required.
Greg Kroah-Hartman [Thu, 10 Mar 2022 21:49:15 +0000 (22:49 +0100)]
Merge tag 'phy-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes:
phy-for-5.18
- New support:
- Mediatek tphy support for MT8186
- Qualcomm usb phy support for sc8180x and sc8280xp
- Qualcomm ufs phy support for sc8180x and sc8280xp
- Qualcomm usb phy support for MSM8953
- Cadence D-Phy Rx support
- Sun4i support for USB phy
- Rockchip naneng combo phy support for RK3568
- Qualcomm eDP PHY for sc7280
- Updates:
- wake on support for Synopsis XHCI controllers
- Yamilify Qualcomm USB HS phy binding
- Charger detection support for TI tusb1210
* tag 'phy-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (53 commits)
phy: qcom-qmp: add sc8280xp UFS PHY
dt-bindings: phy: qcom,qmp: add sc8180x and sc8280xp ufs compatibles
phy: qcom-snps: Add sc8280xp support
dt-bindings: phy: qcom,usb-snps-femto-v2: Add sc8180x and sc8280xp
dt-bindings: Revert "dt-bindings: soc: grf: add naneng combo phy register compatible"
phy: dt-bindings: Add Cadence D-PHY Rx bindings
phy: dt-bindings: cdns,dphy: add power-domains property
phy: dt-bindings: Convert Cadence DPHY binding to YAML
phy: cadence: Add Cadence D-PHY Rx driver
dt-bindings: phy: renesas,usb2-phy: Document RZ/V2L phy bindings
Revert "PCI: aardvark: Fix initialization with old Marvell's Arm Trusted Firmware"
Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional for Armada 3720"
Revert "ata: ahci: mvebu: Make SATA PHY optional for Armada 3720"
phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation
phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver configuration
phy: phy-brcm-usb: fixup BCM4908 support
dt-bindings: phy: mediatek,tphy: Add compatible for MT8192
phy: ti: tusb1210: Add charger detection
phy: ti: tusb1210: Add a delay between power-on and restoring the phy-parameters
phy: ti: tusb1210: Drop tusb->vendor_specific2 != 0 check from tusb1210_power_on()
...
Greg Kroah-Hartman [Thu, 10 Mar 2022 21:48:25 +0000 (22:48 +0100)]
Merge tag 'soundwire-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire into char-misc-next
Vinod writes:
soundwire updates for 5.17-rc1
- stream handling refactoring and renaming to make it consistent
in the core
- runtime pm suport for qcom driver
- in band wake up interrupt support for qcom driver
* tag 'soundwire-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: (27 commits)
soundwire: qcom: use __maybe_unused for swrm_runtime_resume()
soundwire: qcom: constify static struct qcom_swrm_data global variables
soundwire: qcom: add in-band wake up interrupt support
dt-bindings: soundwire: qcom: document optional wake irq
soundwire: qcom: add runtime pm support
soundwire: stream: make enable/disable/deprepare idempotent
soundwire: stream: sdw_stream_add_ functions can be called multiple times
soundwire: stream: introduce sdw_slave_rt_find() helper
soundwire: stream: separate alloc and config within sdw_stream_add_xxx()
soundwire: stream: move list addition to sdw_slave_alloc_rt()
soundwire: stream: rename and move master/slave_rt_free routines
soundwire: stream: group sdw_stream_ functions
soundwire: stream: split sdw_alloc_slave_rt() in alloc and config
soundwire: stream: move sdw_alloc_slave_rt() before 'master' helpers
soundwire: stream: split sdw_alloc_master_rt() in alloc and config
soundwire: stream: simplify sdw_alloc_master_rt()
soundwire: stream: group sdw_port and sdw_master/slave_port functions
soundwire: stream: add 'slave' prefix for port range checks
soundwire: stream: split alloc and config in two functions
soundwire: stream: split port allocation and configuration loops
...
Greg Kroah-Hartman [Thu, 10 Mar 2022 21:39:55 +0000 (22:39 +0100)]
Merge tag 'misc-habanalabs-next-2022-02-28' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into char-misc-next
Oded writes:
This tag contains habanalabs driver changes for v5.18:
- Add new feature of recording time-stamp when a completion
queue counter reaches a target value as determined by the
userspace application. This is used by the graph compiler
to accurately measure the time it takes for certain workloads
to execute, which helps to fine-tune future compilations.
- Add two new attributes to sysfs that expose the VRM and
f/w OS version
- Add a delay to the reset path that allows the driver to
receive and handle additional events from the f/w before
doing the reset. This can help when debugging why a reset
event was received from the f/w.
- Re-factor some of the sysfs code in the driver. Mainly,
move functions from hwmgr.c to more relevant files and
totally remove hwmgr.c file.
- Fix multiple bugs such as races, use-after-free, ignoring
error codes, etc.
- As usual, multiple minor changes and small fixes.
* tag 'misc-habanalabs-next-2022-02-28' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux: (50 commits)
habanalabs: remove deprecated firmware states
habanalabs: add an option to delay a device reset
habanalabs: Add check for pci_enable_device
habanalabs: Fix reset upon device release bug
habanalabs: make sure device mem alloc is page aligned
habanalabs/gaudi: add missing handling of NIC related events
habanalabs/gaudi: handle axi errors from NIC engines
habanalabs: allow user to set allocation page size
habanalabs: use kernel-doc for memory ioctl documentation
habanalabs: avoid using an uninitialized variable
habanalabs: set max power on device init per ASIC
habanalabs: use proper max_power variable for device utilization
habanalabs: enable stop-on-error debugfs setting per ASIC
habanalabs: change function to static
habanalabs: add missing include of vmalloc.h
habanalabs: fix use-after-free bug
habanalabs: rephrase error messages in PCI initialization
habanalabs: fix spelling mistake
habanalabs: Timestamps buffers registration
habanalabs: fix race when waiting on encaps signal
...
Greg Kroah-Hartman [Thu, 10 Mar 2022 21:38:19 +0000 (22:38 +0100)]
Merge tag 'fpga-for-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next
Moritz writes:
FPGA Manager changes for 5.18-rc1
Christophe's patch is part of a larger effort of removing the use of the
deprecated pci-dma-compat API.
All patches have been reviewed on the mailing list, and have been in the
last few linux-next releases (as part of our for-next branch) without issues.
Signed-off-by: Moritz Fischer <mdf@kernel.org>
* tag 'fpga-for-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
fpga: dfl: pci: Remove usage of the deprecated "pci-dma-compat.h" API
soundwire: qcom: constify static struct qcom_swrm_data global variables
The qcom_swrm_data structures is only required for setting soundwire
params, so make the qcom_swrm_data structure const to allow the compiler
to put it in read-only memory and avoid unintentional modifications.
Srinivas Kandagatla [Mon, 28 Feb 2022 17:25:28 +0000 (17:25 +0000)]
soundwire: qcom: add in-band wake up interrupt support
Some of the Qualcomm SoundWire Controller instances like the ones that are
connected to RX path along with Headset connections support Waking up
Controller from Low power clock stop state using SoundWire In-band interrupt.
SoundWire Slave on the bus would initiate this by pulling the data line high,
while the clock is stopped.
Srinivas Kandagatla [Mon, 28 Feb 2022 17:25:27 +0000 (17:25 +0000)]
dt-bindings: soundwire: qcom: document optional wake irq
Wake IRQ is optional interrupt that can be wired up on SoundWire controller
instances like RX path along with MBHC(Multi Button Headset connection).
Document this in bindings.
Srinivas Kandagatla [Mon, 28 Feb 2022 17:25:26 +0000 (17:25 +0000)]
soundwire: qcom: add runtime pm support
Add support to runtime PM using SoundWire clock stop Mode0 on supported
controller instances and soft reset on instances that do not support
clock stop.
Bjorn Andersson [Fri, 25 Feb 2022 03:40:49 +0000 (19:40 -0800)]
phy: qcom-snps: Add sc8280xp support
The Qualcomm sc8280xp platform comes with a 5nm femto USB PHY which, in
contrast to previously seen platforms, has the SIDDQ bit in the COMMON0
register default to high.
So make the driver match on the 5nm compatible and make sure to clear
the SIDDQ bit on phy_init.
This reverts commit b3df807e1fb0 ("dt-bindings: soc: grf: add naneng
combo phy register compatible") as that was wrongly merged, so better to
drop the wrong patch
Pratyush Yadav [Tue, 1 Mar 2022 11:16:18 +0000 (16:46 +0530)]
phy: cadence: Add Cadence D-PHY Rx driver
The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode.
Both modes have a different programming sequence and share little among
them. In addition, a PHY configured in Tx mode cannot be used in Rx mode
and vice versa. For this reason, create a separate driver for the Rx
mode to make it easier to read and maintain.
Document USB phy bindings for RZ/V2L SoC. RZ/V2L USB phy is identical to
one found on the RZ/G2L SoC. No driver changes are required as generic
compatible string "renesas,rzg2l-usb2-phy" will be used as a fallback.
While at it, drop the comment "RZ/G2L family" for "renesas,rzg2l-usb2-phy"
compatible string as this will avoid changing the line for every new SoC
addition.
Robert Hancock [Thu, 27 Jan 2022 17:34:50 +0000 (11:34 -0600)]
iio: adc: xilinx-ams: Fix single channel switching sequence
Some of the AMS channels need to be read by switching into single-channel
mode from the normal polling sequence. There was a logic issue in this
switching code that could cause the first read of these channels to read
back as zero.
It appears that the sequencer should be set back to default mode before
changing the channel selection, and the channel should be set before
switching the sequencer back into single-channel mode.
Also, write 1 to the EOC bit in the status register to clear it before
waiting for it to become set, so that we actually wait for a new
conversion to complete, and don't proceed based on a previous conversion
completing.
Fixes: d5c70627a794 ("iio: adc: Add Xilinx AMS driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20220127173450.3684318-5-robert.hancock@calian.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Haibo Chen [Tue, 22 Feb 2022 02:42:21 +0000 (10:42 +0800)]
iio: accel: mma8452: use the correct logic to get mma8452_data
The original logic to get mma8452_data is wrong, the *dev point to
the device belong to iio_dev. we can't use this dev to find the
correct i2c_client. The original logic happen to work because it
finally use dev->driver_data to get iio_dev. Here use the API
to_i2c_client() is wrong and make reader confuse. To correct the
logic, it should be like this
But after commit 8b7651f25962 ("iio: iio_device_alloc(): Remove
unnecessary self drvdata"), the upper logic also can't work.
When try to show the avialable scale in userspace, will meet kernel
dump, kernel handle NULL pointer dereference.
So use dev_to_iio_dev() to correct the logic.
Dual fixes tags as the second reflects when the bug was exposed, whilst
the first reflects when the original bug was introduced.
Fixes: c3cdd6e48e35 ("iio: mma8452: refactor for seperating chip specific data") Fixes: 8b7651f25962 ("iio: iio_device_alloc(): Remove unnecessary self drvdata") Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Martin Kepplinger <martink@posteo.de> Cc: <Stable@vger.kernel.org> Link: https://lore.kernel.org/r/1645497741-5402-1-git-send-email-haibo.chen@nxp.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Billy Tsai [Mon, 21 Feb 2022 01:27:05 +0000 (09:27 +0800)]
iio: adc: aspeed: Add divider flag to fix incorrect voltage reading.
The formula for the ADC sampling period in ast2400/ast2500 is:
ADC clock period = PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0])
When ADC0C[9:0] is set to 0 the sampling voltage will be lower than
expected, because the hardware may not have enough time to
charge/discharge to a stable voltage. This patch use the flag
CLK_DIVIDER_ONE_BASED which will use the raw value read from the
register, with the value of zero considered invalid to conform to the
corrected formula.
Fixes: 573803234e72 ("iio: Aspeed ADC") Reported-by: Konstantin Klubnichkin <kitsok@yandex-team.ru> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220221012705.22008-1-billy_tsai@aspeedtech.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Nuno Sá [Fri, 25 Feb 2022 13:01:27 +0000 (14:01 +0100)]
iio: dac: add support for ltc2688
The LTC2688 is a 16 channel, 16 bit, +-15V DAC with an integrated
precision reference. It is guaranteed monotonic and has built in
rail-to-rail output buffers that can source or sink up to 20 mA.
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