phy: stm32: fix error return in stm32_usbphyc_phy_init
Error code is overridden, in case the PLL doesn't lock. So, the USB
initialization can continue. This leads to a platform freeze.
This can be avoided by returning proper error code to avoid USB probe
freezing the platform. It also displays proper errors in log.
phy: cadence-torrent: Remove unused `regmap` field from state struct
The driver state struct for the sierra PHY driver has a field named
`regmap` that is never referenced. Remove it since it is unused.
Not that there are separate fields of type `struct regmap` for the
individual sections of the device's register map. These other regmaps are
used and not affected by the patch.
phy: cadence: Sierra: Remove unused `regmap` field from state struct
The driver state struct for the sierra PHY driver has a field named
`regmap` that is never referenced. Remove it since it is unused.
Not that there are separate fields of type `struct regmap` for the
individual sections of the device's register map. These other regmaps are
used and not affected by the patch.
Chanho Park [Wed, 6 Jul 2022 02:02:53 +0000 (11:02 +0900)]
phy: samsung-ufs: convert phy clk usage to clk_bulk API
Instead of using separated clock manipulation, this converts the phy
clock usage to be clk_bulk APIs. By using this, we can completely
remove has_symbol_clk check and symbol clk variables.
Furthermore, clk_get should be moved to probe because there is no need
to get them in the phy_init callback.
Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register
without using reglayout. Define corresponding register to be used by
msm8996 PHY tables and use it directly.
phy: qcom-qmp-usb: replace FLL layout writes for msm8996
Other PHYs tables directly reference FLL registers without using
reglayout. Define corresponding registers to be used by msm8996 PHY
tables and use them directly.
phy: qcom-qmp: split PCS_UFS V3 symbols to separate header
Several registers defined in the PCS V3 namespace in reality belong to
the PCS_UFS V3 register space. Move them to the separate header and
rename them to explicitly mention PCS_UFS. While we are at it, correct
one register in the msm8998_usb3_pcs_tbl table to use PCS register name.
phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3
PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols
duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the
IPQ6018 and IPQ8074 tables and drop the custom PCS_COM_*/PCS_PCIE*
names.
phy: qcom-qmp-combo,usb: add support for separate PCS_USB region
Different QMP USB PHYs might have different offset from PCS to PCS_USB
register space, but the same PCS_USB register layout. Add separate
PCS_USB region space and merge related PCS_USB definitions.
phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table
The msm8996_ufs_serdes_tbl table contains write to
QPHY_POWER_DOWN_CONTROL, however this register doesn't belong to the
QSERDES register space. Also the PHY power down is already handled in
the qcom_qmp_phy_ufs_com_init(). Drop this entry completely.
phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4.
The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl)
should use the 0x1a0 register, as stated in the downstream dtsi tree.
drm/msm/dp: delete vdda regulator related functions from eDP/DP controller
Vdda regulators are related to both eDP and DP phy so that it should be
managed at eDP and DP phy driver instead of controller. This patch removes
vdda regulators related functions out of eDP/DP controller.
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1657038556-2231-4-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Jiang Jian [Tue, 21 Jun 2022 12:24:01 +0000 (20:24 +0800)]
phy: phy-brcm-usb: drop unexpected word "the" in the comments
there is an unexpected word "the" in the comments that need to be dropped
file: ./drivers/phy/broadcom/phy-brcm-usb-init.c
line: 864
* Make sure the the second and third memory controller
changed to
* Make sure the second and third memory controller
Peter Geis [Wed, 22 Jun 2022 00:31:40 +0000 (20:31 -0400)]
phy: rockchip-inno-usb2: Sync initial otg state
The initial otg state for the phy defaults to device mode. The actual
state isn't detected until an ID IRQ fires. Fix this by syncing the ID
state during initialization.
Fixes: 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Robert Marko [Tue, 21 Jun 2022 19:55:12 +0000 (21:55 +0200)]
phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
Gen2 one is already supported, so add the support for the Gen3 one.
It uses the same register layout as IPQ6018.
Robert Marko [Tue, 21 Jun 2022 19:55:10 +0000 (21:55 +0200)]
phy: qcom-qmp-pcie: make pipe clock rate configurable
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
like every other PCIe QMP PHY does, so make it configurable as part of the
qmp_phy_cfg.
Johan Hovold [Thu, 23 Jun 2022 11:33:14 +0000 (13:33 +0200)]
phy: qcom-qmp-usb: clean up pipe clock handling
Clean up the pipe clock handling by using dev_err_probe() to handle
probe deferral and dropping the obsolete comment that claimed that the
pipe clock was optional for some other PHY types.
Johan Hovold [Thu, 23 Jun 2022 11:33:13 +0000 (13:33 +0200)]
phy: qcom-qmp-pcie-msm8996: drop obsolete pipe clock type check
Drop the obsolete pipe clock handling which was used to treat the pipe
clock as optional for types other than PCIe and USB and which is no
longer needed since splitting the PHY driver.
Johan Hovold [Thu, 23 Jun 2022 11:33:12 +0000 (13:33 +0200)]
phy: qcom-qmp-pcie: drop obsolete pipe clock type check
Drop the obsolete pipe clock handling which was used to treat the pipe
clock as optional for types other than PCIe and USB and which is no
longer needed since splitting the PHY driver.
Markus Schneider-Pargmann [Fri, 24 Jun 2022 06:27:25 +0000 (14:27 +0800)]
phy: phy-mtk-dp: Add driver for DP phy
This is a new driver that supports the integrated DisplayPort phy for
mediatek SoCs, especially the mt8195. The phy is integrated into the
DisplayPort controller and will be created by the mtk-dp driver. This
driver expects a struct regmap to be able to work on the same registers
as the DisplayPort controller. It sets the device data to be the struct
phy so that the DisplayPort controller can easily work with it.
The driver does not have any devicetree bindings because the datasheet
does not list the controller and the phy as distinct units.
The interaction with the controller can be covered by the configure
callback of the phy framework and its displayport parameters.
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
[Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220624062725.4095-1-rex-bc.chen@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Peter Geis [Sat, 25 Jun 2022 21:27:11 +0000 (17:27 -0400)]
phy: rockchip-inno-usb2: Prevent incorrect error on probe
If a phy supply is designated but isn't available at probe time, an
EPROBE_DEFER is returned. Use dev_err_probe to prevent this from
incorrectly printing during boot.
Jiang Jian [Tue, 21 Jun 2022 12:00:15 +0000 (20:00 +0800)]
phy: dphy: drop unexpected word "the" in the comments
there is an unexpected word "the" in the comments that need to be dropped
file: ./drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
line: 139
* when in RxULPS check state, after the the logic enable the analog,
changed to
* when in RxULPS check state, after the logic enable the analog,
Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220621120015.113682-1-jiangjian@cdjrlc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Vidya Sagar [Wed, 29 Jun 2022 06:04:32 +0000 (11:34 +0530)]
phy: tegra: Add PCIe PIPE2UPHY support for Tegra234
Synopsys DesignWare core based PCIe controllers in Tegra234 SoC
interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U)
module. For each PCIe lane of a controller, there is a P2U unit
instantiated at hardware level. This driver provides support for the
programming required for each P2U that is going to be used for a PCIe
controller.
Vidya Sagar [Wed, 29 Jun 2022 06:04:25 +0000 (11:34 +0530)]
dt-bindings: PHY: P2U: Add support for Tegra234 P2U block
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
module instantiated once for each PCIe lane between Synopsys DesignWare
core based PCIe IP and Universal PHY block.
Jianjun Wang [Fri, 17 Jun 2022 07:02:45 +0000 (15:02 +0800)]
dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220617070246.20142-2-jianjun.wang@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Douglas Anderson [Mon, 25 Apr 2022 21:06:43 +0000 (14:06 -0700)]
dt-bindings: phy: List supplies for qcom,edp-phy
We're supposed to list the supplies in the dt bindings but there are
none in the eDP PHY bindings.
Looking at the driver in Linux, I can see that there seem to be two
relevant supplies: "vdda-phy" and "vdda-pll". Let's add those to the
bindings.
NOTE: from looking at the Qualcomm datasheet for sc7280, it's not
immediately clear how to figure out how to fill in these supplies. The
only two eDP related supplies are simply described as "power for eDP
0.9V circuits" and "power for eDP 1.2V circuits". From guessing and
from comparing how a similar PHY is hooked up on other similar
Qualcomm boards, I'll make the educated guess that the 1.2V supply
goes to "vdda-phy" and the 0.9V supply goes to "vdda-pll" and I'll use
that in the example here.
Dmitry Baryshkov [Tue, 7 Jun 2022 21:31:59 +0000 (00:31 +0300)]
phy: qcom-qmp-usb: drop multi-PHY support
Each USB QMP PHY device provides just a single UFS PHY. Drop support
for handling multiple child PHYs. Use phy->init_count to check if the
PHY was initialized rather than duplicating this count.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-27-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
Dmitry Baryshkov [Tue, 7 Jun 2022 21:31:54 +0000 (00:31 +0300)]
phy: qcom-qmp-pcie-msm8996: cleanup the driver
Remove the conditionals and options that are not used by the MSM8996
PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is
the case for this PHY.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-22-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
Dmitry Baryshkov [Tue, 7 Jun 2022 21:31:39 +0000 (00:31 +0300)]
phy: qcom-qmp-combo: drop all non-combo compatibles support
Drop support for all non-USB+DP compatibles from the new qmp-combo
driver. Currently this will result in duplication (both in terms of code
and in terms of config tables) with USB PHY support. This will be sorted
out later, after fixing the combo PHY init/reinit issues.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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