zhang songyi [Fri, 2 Dec 2022 02:42:04 +0000 (10:42 +0800)]
pxa: Remove dev_err() after platform_get_irq()
There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.
Arnd Bergmann [Wed, 30 Nov 2022 16:52:39 +0000 (17:52 +0100)]
Merge tag 'arm-soc/for-6.2/drivers' of https://github.com/Broadcom/stblinux into soc/drivers
This pull request contains Broadcom SoCs driver changes for 6.2, please
pull the following:
- Yuan uses dev_err_probe() in the Raspberry Pi firmware provider to
simplify the error handling code
- Rafal adds support for initialiazing the BCM47xx NVMEM/NVRAM firmware
provider out of memory-mapped flash devices.
* tag 'arm-soc/for-6.2/drivers' of https://github.com/Broadcom/stblinux:
firmware/nvram: bcm47xx: support init from IO memory
firmware: raspberrypi: Use dev_err_probe() to simplify code
Sven Peter [Fri, 4 Nov 2022 15:39:02 +0000 (16:39 +0100)]
soc: apple: sart: Stop casting function pointer signatures
Fixes: b170143ae111 ("soc: apple: Add SART driver") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
Arnd Bergmann [Wed, 23 Nov 2022 13:21:16 +0000 (14:21 +0100)]
tegra: mark BPMP driver as little-endian only
The BPMP firmware driver never worked on big-endian kernels, and
cannot easily be made portable. Add a dependency to make this clear
in case anyone ever wants to try a big-endian kernel on this hardware.
Arnd Bergmann [Wed, 23 Nov 2022 12:07:02 +0000 (13:07 +0100)]
Merge tag 'ti-driver-soc-for-v6.2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers
TI SoC driver updates for v6.2 v2
* Minor bugfixes for knav_qmss_queue, smartreflex drivers
* API optimizations including using devm, bitmap apis to
ti-sci, soc-info drivers
* k3-ringacc can now be built as modules for certain
distros that mandate such usage.
* k3-socinfo can now detect AM62A SoCs.
* tag 'ti-driver-soc-for-v6.2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
soc: ti: k3-socinfo: Add AM62Ax JTAG ID
soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe
soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe
firmware: ti_sci: Use devm_bitmap_zalloc when applicable
soc: ti: k3-ringacc: Allow the driver to be built as module
firmware: ti_sci: Fix polled mode during system suspend
firmware: ti_sci: Use the non-atomic bitmap API when applicable
firmware: ti_sci: Use the bitmap API to allocate bitmaps
drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as static
Arnd Bergmann [Tue, 22 Nov 2022 21:53:22 +0000 (22:53 +0100)]
Merge tag 'qcom-drivers-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for 6.2
The qcom,msm-id and qcom,board-id DeviceTree properties are documented,
to allow them to be used in configurations or devices requiring these
and the socinfo driver is updated to reuse the introduced identifiers.
The rpmh-rsc driver is extended to register for PM runtime notifications
from the CPU clusters, in order to submit sleep and wake votes the last
core in a cluster is being powered down.
A mechanism for keeping rpmhpd resources voted until sync_state is
introduced, this ensures that power-domains required during boot are
kept enabled. The rpmhpd power-domains for SDM670 are also added.
Support for the new QDU1000/QRU1000 platform is introduced in the rpmhpd
and socinfo drivers.
The APR driver gains missing error handling. QMI message descriptors in
the PDR driver are made const.
Support for the RPM found in SM6375 is added. The SPM driver gains
support for MSM8939 and MSM8976 platforms.
The stats and command-db drvers are marked as not having PM support.
* tag 'qcom-drivers-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits)
dt-bindings: firmware: scm: add sdm670 compatible
soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
soc: qcom: rpmh-rsc: Save base address of drv
PM: domains: Store the next hrtimer wakeup in genpd
soc: qcom: rpmh-rsc: Attach RSC to cluster PM domain
dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rsc
dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976
soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index
soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id table
dt-bindings: arm: qcom,ids: Add SoC IDs for QDU1000/QRU1000
soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domains
dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd binding
dt-bindings: qcom: smp2p: Add WPSS node names to pattern property
soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM
dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2
soc: qcom: llcc: make irq truly optional
soc: qcom: spm: Add MSM8939 SPM register data
dt-bindings: soc: qcom: spm: Add MSM8939 CPU compatible
dt-bindings: soc: qcom: aoss: Add sc8280xp compatible
dt-bindings: firmware: document Qualcomm SM6375 SCM
...
Arnd Bergmann [Tue, 22 Nov 2022 21:38:00 +0000 (22:38 +0100)]
Merge tag 'tegra-for-6.2-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
memory: tegra: Changes for v6.2-rc1
Some cleanups replace open-coded debugfs attributes and memory client
IDs are added for the DLA IP found on Tegra234 SoCs.
* tag 'tegra-for-6.2-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra: Add DLA clients for Tegra234
memory: tegra186-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
memory: tegra210-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
memory: tegra30-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
memory: tegra20-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
dt-bindings: tegra: Update headers for Tegra234
dt-bindings: Add headers for NVDEC on Tegra234
Arnd Bergmann [Tue, 22 Nov 2022 21:14:31 +0000 (22:14 +0100)]
Merge tag 'tegra-for-6.2-firmware-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
firmware: tegra: Changes for v6.2-rc1
This adds new BPMP ABI so that newer features can be enabled.
Furthermore, the BPMP driver is updated to use iosys-map helpers to
allow working with shared memory regions that are located in system
memory.
Apart from that, several minor cleanups are included.
* tag 'tegra-for-6.2-firmware-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
firmware: tegra: Remove surplus dev_err() when using platform_get_irq_byname()
firmware: tegra: Update BPMP ABI
firmware: tegra: bpmp: Do not support big-endian
firmware: tegra: bpmp: Use iosys-map helpers
firmware: tegra: bpmp: Prefer u32 over uint32_t
Arnd Bergmann [Tue, 22 Nov 2022 21:04:37 +0000 (22:04 +0100)]
Merge tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
soc/tegra: Changes for v6.2-rc1
In addition to a number of improvements and cleanups this contains a
fix for the FUSE access on newer chips, adds Tegra234 I/O pad support
and fixes various issues with wake events.
The SoC sysfs revision attribute is updated to include the platform
information so drivers can check for silicon vs. pre-silicon, among
other things.
* tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: cbb: Remove redundant dev_err call
soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_err
firmware: tegra: include IVC header file only once
soc/tegra: cbb: Check firewall before enabling error reporting
soc/tegra: cbb: Add checks for potential out of bound errors
soc/tegra: cbb: Update slave maps for Tegra234
soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194
soc/tegra: fuse: Use platform info with SoC revision
soc/tegra: pmc: Process wake events during resume
soc/tegra: pmc: Fix dual edge triggered wakes
soc/tegra: pmc: Add I/O pad table for Tegra234
soc/tegra: fuse: Add nvmem keepout list
soc/tegra: fuse: Use SoC specific nvmem cells
soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY
Arnd Bergmann [Tue, 22 Nov 2022 14:27:59 +0000 (15:27 +0100)]
Merge tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V SoC drivers for v6.2
SiFive:
- add probe error handling to the ccache driver
* tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()
soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()
Fabien Parent [Mon, 31 Oct 2022 09:33:57 +0000 (10:33 +0100)]
soc: mediatek: pwrap: add support for sys & tmr clocks
MT8365 requires an extra 2 clocks to be enabled to behave correctly.
Add support these 2 clocks, they are made optional since they seem to
be present only on MT8365.
Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221031093401.22916-3-fchiby@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.
dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.
To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Arnd Bergmann [Mon, 21 Nov 2022 12:54:29 +0000 (13:54 +0100)]
Merge tag 'imx-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers
i.MX drivers change for 6.2:
- Improve imx8m-blk-ctrl driver to allow deferred probe in case that
'bus' genpd is not yet ready.
- Add missing USB_1_PHY PD for i.MX scu-pd firmware driver.
- Add GENPD_FLAG_ACTIVE_WAKEUP flag for i.MX8MM/N in GPCv2 driver, so
that the power domain remains on if USB remote wakeup is enabled.
* tag 'imx-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/n
firmware: imx: scu-pd: add missed USB_1_PHY pd
soc: imx: imx8m-blk-ctrl: Defer probe if 'bus' genpd is not yet ready
Peter De Schrijver [Thu, 27 Oct 2022 12:13:55 +0000 (15:13 +0300)]
clk: tegra: Support BPMP-FW ABI deny flags
Support BPMP_CLK_STATE_CHANGE_DENIED by not populating state changing
operations when the flag is set.
Support BPMP_CLK_RATE_PARENT_CHANGE_DENIED by not populating rate or
parent changing operations when the flag is set.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Yang Li [Wed, 26 Oct 2022 05:34:33 +0000 (13:34 +0800)]
firmware: tegra: Remove surplus dev_err() when using platform_get_irq_byname()
There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.
./drivers/firmware/tegra/bpmp-tegra210.c:204:2-9: line 204 is redundant
because platform_get_irq() already prints an error
./drivers/firmware/tegra/bpmp-tegra210.c:216:2-9: line 216 is redundant
because platform_get_irq() already prints an error
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2579 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Peter De Schrijver [Thu, 27 Oct 2022 12:13:53 +0000 (15:13 +0300)]
firmware: tegra: Update BPMP ABI
Update the BPMP ABI to align with the the latest version.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
firmware: tegra: include IVC header file only once
Add the necessary definition to prevent compilation
errors from the ivc.h file being included multiple times.
This does not currently cause any compilation issues,
but fix this anyway.
Zhang Qilong [Tue, 8 Nov 2022 08:03:22 +0000 (16:03 +0800)]
soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe
The pm_runtime_enable will increase power disable depth. Thus
a pairing decrement is needed on the error handling path to
keep it balanced according to context.
Zhang Qilong [Tue, 8 Nov 2022 08:03:21 +0000 (16:03 +0800)]
soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe
The pm_runtime_enable will increase power disable depth. Thus
a pairing decrement is needed on the error handling path to
keep it balanced according to context.
Yinbo Zhu [Fri, 11 Nov 2022 05:42:00 +0000 (13:42 +0800)]
soc: loongson: add GUTS driver for loongson-2 platforms
The global utilities block controls PCIE device enabling, alternate
function selection for multiplexed signals, consistency of HDA, USB
and PCIE, configuration of memory controller, rtc controller, lio
controller, and clock control.
This patch adds a driver to manage and access global utilities block
for LoongArch architecture Loongson-2 SoCs. Initially only reading SVR
and registering soc device are supported. Other guts accesses, such
as reading firmware configuration by default, should eventually be
added into this driver as well.
Arnd Bergmann [Mon, 14 Nov 2022 14:55:42 +0000 (15:55 +0100)]
Merge tag 'renesas-drivers-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v6.2
- Let SOC_RENESAS select GPIOLIB and PINCTRL, so this does not have to
be handled in two (soon three: arm/arm64/riscv), places.
* tag 'renesas-drivers-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS
Sumit Gupta [Wed, 9 Nov 2022 13:57:17 +0000 (19:27 +0530)]
soc/tegra: cbb: Check firewall before enabling error reporting
To enable error reporting for a fabric to CCPLEX, we need to write its
register for enabling error interrupt to CCPLEX during boot and later
clear the error status register after error occurs. If a fabric's
registers are protected and not accessible from CCPLEX, then accessing
the registers will cause CBB firewall error.
Add support to check whether write access from CCPLEX to the registers
of a fabric is not blocked by it's firewall before enabling error
reporting to CCPLEX for that fabric.
Sumit Gupta [Wed, 9 Nov 2022 13:57:16 +0000 (19:27 +0530)]
soc/tegra: cbb: Add checks for potential out of bound errors
Added checks to avoid potential out of bounds errors which can happen if
the 'slave map' and 'CBB errors' arrays are not correct or latest where
some entries are missing.
Sumit Gupta [Wed, 9 Nov 2022 13:57:14 +0000 (19:27 +0530)]
soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194
In Tegra194 SoC, master_id bit range is different between cluster NOC
and CBB NOC. Currently same bit range is used which results in wrong
master_id value. Due to this, illegal accesses from the CCPLEX master
do not result in a crash as expected. Fix this by using the correct
range for the CBB NOC.
Finally, it is only necessary to extract the master_id when the
erd_mask_inband_err flag is set because when this is not set, a crash
is always triggered.
Kartik [Wed, 9 Nov 2022 14:20:22 +0000 (19:50 +0530)]
soc/tegra: fuse: Use platform info with SoC revision
Tegra pre-silicon platforms do not have chip revisions. This makes the
revision SoC attribute meaningless on these platforms.
Instead, populate the revision SoC attribute with a combination of the
platform name and the chip revision for silicon platforms, and simply
with the platform name on pre-silicon platforms.
Assign a big positive integer instead of an negative integer to an
u32 variable. Also remove the check for ">= 0" which doesn't make sense
for unsigned integers.
Maulik Shah [Tue, 18 Oct 2022 15:28:37 +0000 (17:28 +0200)]
soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
The next wakeup timer value needs to be set in always on domain timer
as the arch timer interrupt can not wakeup the SoC if after the deepest
CPUidle states the SoC also enters deepest low power state.
To wakeup the SoC in such scenarios the earliest wakeup time is set in
CONTROL_TCS and the firmware takes care of setting up its own timer in
always on domain with next wakeup time. The timer wakes up the RSC and
sets resources back to wake state.
Maulik Shah [Tue, 18 Oct 2022 15:28:36 +0000 (17:28 +0200)]
soc: qcom: rpmh-rsc: Save base address of drv
Add changes to save drv's base address for rsc. This is
used to read drv's configuration such as solver mode is
supported or to write into CONTROL_TCS registers.
Maulik Shah [Tue, 18 Oct 2022 15:28:35 +0000 (17:28 +0200)]
PM: domains: Store the next hrtimer wakeup in genpd
The arch timer cannot wake up the Qualcomm Technologies, Inc. (QTI) SoCs
from the deeper CPUidle states. To be able to wakeup from these deeper
states, another always-on timer needs to be programmed through the so
called CONTROL_TCS.
As the RSC is part of CPU subsystem and the corresponding APSS RSC device
is attached to the cluster PM domain (through genpd), it holds the
responsibility to program the always-on timer, before entering any of these
deeper CPUidle states.
However, programming the timer requires information about the next hrtimer
wakeup for the cluster PM domain, which is currently only known by genpd.
Therefore, let's share this data through a new genpd helper function,
dev_pm_genpd_get_next_hrtimer().
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
[Ulf: Reworked the code and updated the commit message] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-5-ulf.hansson@linaro.org
Lina Iyer [Tue, 18 Oct 2022 15:28:33 +0000 (17:28 +0200)]
soc: qcom: rpmh-rsc: Attach RSC to cluster PM domain
RSC is part the CPU subsystem and powers off the CPU domains when all
the CPUs and no RPMH transactions are pending from any of the drivers.
The RSC needs to flush the 'sleep' and 'wake' votes that are critical
for saving power when all the CPUs are in idle.
Let's make RSC part of the CPU PM domains, by attaching it to the
cluster power domain. Registering for PM domain notifications, RSC
driver can be notified that the last CPU is powering down. When the last
CPU is powering down the domain, let's flush the 'sleep' and 'wake'
votes that are stored in the data buffers into the hardware and also
write next wakeup in CONTROL_TCS.
Petlozu Pravareshwar [Sun, 2 Oct 2022 14:44:09 +0000 (14:44 +0000)]
soc/tegra: pmc: Process wake events during resume
During system resume, translate tier2 SC7 wake sources back into IRQs
and do generic_handle_irq() to invoke the interrupt handlers for edge
triggered wake events such as SW-wake.
When a wake event is defined to be triggered on both positive and
negative edge of the input wake signal, it is crucial to know the
current state of the signal when going into suspend. The intended way to
obtain the current state of the wake signals is to read the
WAKE_AOWAKE_SW_STATUS register, which should contains the raw state of
the wake signals.
However, this register is edge triggered, an edge will not be generated
for signals that are already asserted prior to the assertion of
WAKE_LATCH_SW.
To workaround this, change the polarity of the wake level from '0' to
'1' while latching the signals, as this will generate an edge for
signals that are set to '1'.
Add I/O pad table for Tegra234 to allow configuring DPD mode and
switching the pins to 1.8V or 3.3V as needed.
On Tegra234, DPD registers are reorganized such that there is a DPD_REQ
register and a DPD_STATUS register per pad group. Update the PMC driver
accordingly.
While at it, use the generated tables from tegra-pinmux-scripts to make
the formatting of these tables more consistent.
Rafał Miłecki [Thu, 3 Nov 2022 08:25:29 +0000 (09:25 +0100)]
firmware/nvram: bcm47xx: support init from IO memory
Provide NVMEM content to the NVRAM driver from a simple
memory resource. This is necessary to use NVRAM in a memory-
mapped flash device. Patch taken from OpenWrts development
tree.
This patch makes it possible to use memory-mapped NVRAM
on the D-Link DWL-8610AP and the D-Link DIR-890L.
Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@vger.kernel.org Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
[Added an export for modules potentially using the init symbol] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20221103082529.359084-1-linus.walleij@linaro.org Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Xinlei Lee [Tue, 8 Nov 2022 18:23:27 +0000 (19:23 +0100)]
soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func
The difference between MT8186 and other ICs is that when modifying the
output format, we need to modify the mmsys_base+0x400 register to take
effect. So when setting the dpi output format, we need to call
mtk_mmsys_ddp_dpi_fmt_config to set it to MT8186 synchronously.
Commit a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi
output for MT8186") lacked some of the possible output formats and also
had a wrong bitmask.
Add the missing output formats and fix the bitmask.
While at it, also update mtk_mmsys_ddp_dpi_fmt_config() to use generic
formats, so that it is slightly easier to extend for other platforms.
Fixes: a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for MT8186") Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: NÃcolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Jiasheng Jiang [Mon, 7 Nov 2022 01:44:03 +0000 (09:44 +0800)]
soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index
As idr_alloc() and of_property_read_string_index() can return negative
numbers, it should be better to check the return value and deal with
the exception.
Therefore, it should be better to use goto statement to stop and return
error.
Manikanta Pubbisetty [Mon, 17 Oct 2022 12:53:45 +0000 (18:23 +0530)]
dt-bindings: qcom: smp2p: Add WPSS node names to pattern property
WLAN firmware uses SMP2P protocol in order to talk to the application
processor (AP) in certain cases like WoW (Wake on Wireless). WLAN
firmware runs on the WPSS Q6 processor (Wireless Processor SubSystem).
Therefore it is required to have sub nodes pertaining to the WPSS Q6
processor and the application processor in the SMP2P node.
Add WPSS Q6 (Wireless Processor SubSystem) node names to the pattern
property required for WPSS Q6 processor to communicate to the
application processor and vice versa over SMP2P protocol.
AngeloGioacchino Del Regno [Fri, 4 Nov 2022 13:34:52 +0000 (14:34 +0100)]
soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM
Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
and APQ variants and while at it also add the configuration for the
MSM8976's little (a53) and big (a72) clusters cache power management.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Marijn: reorder struct definitions to follow high-to-low order] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104133452.131227-3-angelogioacchino.delregno@collabora.com
Arnd Bergmann [Wed, 2 Nov 2022 21:04:17 +0000 (22:04 +0100)]
Merge tag 'memory-controller-drv-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v6.2
1. STM32 FMC2:
a. Correct in bindings the name of property for address
setup duration. The DTS and driver were already using proper name,
so it is only alignment of bindings with real usage.
b. Split off STM32 memory controller bus peripheral properties into
generic ones (re-usable by multiple memory controllers) and STM32 bus
peripheral. This way, the FMC2 controller properties in Micrel
KSZ8851MLL ethernet controller node can be properly validated.
2. Tegra MC: simplify with DEFINE_SHOW_ATTRIBUTE.
3. Renesas RPC IF: add suppor tfor R-Car Gen4.
4. LPDDR bindings: refactor and extend with description of DDR channels.
Add also bindings for LPDDR4 and LPDDR5.
The rationale for (4) above - LPDDR bindings changes, wrote by Julius Werner:
"We (Chromium OS) have been trying to find a way to pass LPDDR memory
chip information that is available to the firmware through the FDT
(mostly for userspace informational purposes, for now). We have been
using and expanding the existing "jedec,lpddr2" and "jedec,lpddr3"
bindings for this (e.g. [1]). The goal is to be able to identify the
memory layout of the system (how the parts look like, how they're tied
together, how much capacity there is in total) as accurately as
possible from software-probed values.
...
The problem with this is that each individual LPDDR chip has its own
set of mode registers (per rank) that only describe the density of
that particular chip (rank). The host memory controller may have
multiple channels (each of which is basically an entirely separate set
of physical LPDDR pins on the board), a single channel may be
connected to multiple LPDDR chips (e.g. if the memory controller has
an outgoing 32-bit channel, that channel could be tied to two 16-bit
LPDDR chips by tying the low 16 bits to one and the high 16 bits to
the other), and then each of those chips may offer multiple
independent ranks (which rank is being accessed at a given time is
controlled by a separate chip select pin).
So if we just have one "io-width" and one "density" field in the FDT,
there's no way to figure out how much memory there's actually
connected in total, because that only describes a single LPDDR chip.
Worse, there may be chips where different ranks have different
densities (e.g. a 6GB dual-rank chip with one 4GB and one 2GB rank),
and different channels could theoretically be connected to chips of
completely different manufacturers."
Link: https://lore.kernel.org/r/CAODwPW9E8wWwxbYKyf4_-JFb4F-JSmLR3qOF_iudjX0f9ndF0A@mail.gmail.com
* tag 'memory-controller-drv-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
dt-bindings: memory-controller: st,stm32: Split off MC properties
dt-bindings: memory: Add jedec,lpddrX-channel binding
dt-bindings: memory: Add jedec,lpddr4 and jedec,lpddr5 bindings
dt-bindings: memory: Add numeric LPDDR compatible string variant
dt-bindings: memory: Factor out common properties of LPDDR bindings
memory: renesas-rpc-if: Add support for R-Car Gen4
memory: renesas-rpc-if: Clear HS bit during hardware initialization
dt-bindings: memory: renesas,rpc-if: Document R-Car V4H support
memory: tegra186-emc: use DEFINE_SHOW_ATTRIBUTE to simplify code
memory: tegra210-emc: use DEFINE_SHOW_ATTRIBUTE to simplify code
memory: tegra30-emc: use DEFINE_SHOW_ATTRIBUTE to simplify code
memory: tegra20-emc: use DEFINE_SHOW_ATTRIBUTE to simplify code
dt-bindings: memory-controller: st,stm32: Fix st,fmc2_ebi-cs-write-address-setup-ns
The GPMC controller has the ability to configure the polarity for the
wait pin. The current properties do not allow this configuration.
This binding directly configures the WAITPIN<X>POLARITY bit
in the GPMC_CONFIG register by setting the "ti,wait-pin-polarity"
dt-property.
Benedikt Niedermayr [Wed, 2 Nov 2022 13:30:46 +0000 (14:30 +0100)]
memory: omap-gpmc: wait pin additions
This patch introduces support for setting the wait-pin polarity as well
as using the same wait-pin for different CS regions.
The waitpin polarity can be configured via the WAITPIN<X>POLARITY bits
in the GPMC_CONFIG register. This is currently not supported by the
driver. This patch adds support for setting the required register bits
with the "ti,wait-pin-polarity" dt-property.
The wait-pin can also be shared between different CS regions for special
usecases. Therefore GPMC must keep track of wait-pin allocations, so it
knows that either GPMC itself or another driver has the ownership.
Commit de67fa80c669 ("dt-bindings: memory-controllers: arm,pl353-smc:
Extend to support 'arm,pl354' SMC") renames the arm,pl353-smc.yaml
memory-controller dt-binding, but misses to adjust its reference in
MAINTAINERS.
Linus Walleij [Thu, 27 Oct 2022 08:11:08 +0000 (10:11 +0200)]
soc: fsl: qe: Avoid using gpio_to_desc()
The qe gpio driver is a custom API combined GPIO and pin control
driver that exist outside of the pin control subsystem for historical
reasons.
We want to get rid of the old GPIO numberspace, so instead of
calling gpio_to_desc() we get the gpio descriptor for the requested
line from the device tree directly without passing through the
GPIO numberspace, and then we get the gpiochip from the descriptor.
Using the reference counting inside the gpio descriptor we can drop
the reference counting code in this driver. A second gpiod_get()
will not succeed.
To obtain the local hardware offset of the GPIO line, the driver
need to include the header from the gpiolib internals. This isn't
pretty but it is the lesser evil compared to keeping the code
as a roadblock to gpiolib refactoring. A proper solution would be
to rewrite the driver as a real pin control driver with a
built-in gpio_chip.
Georgi Vlaev [Fri, 21 Oct 2022 18:57:04 +0000 (21:57 +0300)]
firmware: ti_sci: Fix polled mode during system suspend
Commit b9e8a7d950ff ("firmware: ti_sci: Switch transport to polled
mode during system suspend") uses read_poll_timeout_atomic() macro
in ti_sci_do_xfer() to wait for completion when the system is
suspending. The break condition of the macro is set to "true" which
will cause it break immediately when evaluated, likely before the
TISCI xfer is completed, and always return 0. We want to poll here
until "done_state == true".
1) Change the break condition of read_poll_timeout_atomic() to
the bool variable "done_state".
2) The read_poll_timeout_atomic() returns 0 if the break condition
is met or -ETIMEDOUT if not. Since our break condition has changed
to "done_state", we also don't have to check for "!done_state" when
evaluating the return value.
Rob Herring [Fri, 21 Oct 2022 20:39:28 +0000 (15:39 -0500)]
dt-bindings: memory-controllers: arm,pl353-smc: Extend to support 'arm,pl354' SMC
Add support for the Arm PL354 static memory controller to the existing
Arm PL353 binding. Both are different configurations of the same IP with
support for different types of memory interfaces.
The 'arm,pl354' binding has already been in use upstream for a long time
in Arm development boards. The existing users have only the controller
without any child devices, so drop the required address properties
(ranges, #address-cells, #size-cells). The schema for 'ranges' is too
constrained as the order is not important and the PL354 has 8
chipselects (And the PL353 actually has up to 8 too).
The clocks aren't really correct in either case. There's 1 bus clock and
then a clock for each of the 2 memory interfaces.
Kartik [Fri, 7 Oct 2022 09:51:07 +0000 (15:21 +0530)]
soc/tegra: fuse: Add nvmem keepout list
On Tegra186 and later, various FUSE offsets are restricted and cannot be
accessed from CCPLEX. Currently nvmem binary interface allows reading
such offsets from userspace, which results in RAS errors.
Add nvmem keepout lists to avoid any reads to restricted offsets.
The CPU and BPMP inter-processor communication code is only partially
endian-aware, so it doesn't work properly when run on a big-endian CPU
anyway. Running Tegra SoCs in big-endian mode has also never been
supported, especially not on those with 64-bit ARM processors.
If big-endian support ever becomes necessary this can be added back but
will need additional fixes for completeness.
The shared memory used for inter-processor communication between the CPU
and the BPMP can reside either in system memory or in I/O memory. Use
the iosys-map helpers to abstract these differences away.
projects / users / jedix / linux-maple.git / log