Richard Henderson [Fri, 7 Jan 2022 21:32:24 +0000 (13:32 -0800)]
linux-user/hppa: Use force_sig_fault
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP
and missing si_code for SIGBUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Tue, 11 Jan 2022 11:39:31 +0000 (11:39 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into staging
SD/MMC patches queue
- Add SDHC support for SD card SPI-mode (Frank Chang)
# gpg: Signature made Sat 08 Jan 2022 21:56:02 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/sdmmc-20220108:
hw/sd: Add SDHC support for SD card SPI-mode
hw/sd/sdcard: Rename Write Protect Group variables
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 11 Jan 2022 10:12:29 +0000 (10:12 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio: revert config interrupt changes
Lots of fallout from config interrupt changes. Author wants to rework
the patches. Let's revert quickly so others don't suffer meanwhile.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Mon 10 Jan 2022 21:03:44 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
Revert "virtio: introduce macro IRTIO_CONFIG_IRQ_IDX"
Revert "virtio-pci: decouple notifier from interrupt process"
Revert "virtio-pci: decouple the single vector from the interrupt process"
Revert "vhost: introduce new VhostOps vhost_set_config_call"
Revert "vhost-vdpa: add support for config interrupt"
Revert "virtio: add support for configure interrupt"
Revert "vhost: add support for configure interrupt"
Revert "virtio-net: add support for configure interrupt"
Revert "virtio-mmio: add support for configure interrupt"
Revert "virtio-pci: add support for configure interrupt"
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fixes: 316011b8a7 ("virtio-pci: decouple the single vector from the interrupt process") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: 497679d510 ("virtio-net: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: d48185f1a4 ("virtio-mmio: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: d5d24d859c ("virtio-pci: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Mark Cave-Ayland [Sat, 8 Jan 2022 18:04:53 +0000 (18:04 +0000)]
target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DATA feature enabled
Commit a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") added
a new feature for processors from the 68020 onwards which do not require data
accesses to be word aligned.
Unfortunately the original commit missed an additional case whereby the SP is
still word aligned when setting up an additional format 1 stack frame so add the
necessary M68K_FEATURE_UNALIGNED_DATA feature guard.
Mark Cave-Ayland [Sat, 8 Jan 2022 16:41:47 +0000 (16:41 +0000)]
macfb: fix VRAM dirty memory region logging
The macfb VRAM memory region was configured with coalescing rather than dirty
memory logging enabled, causing some areas of the screen not to redraw after
a full screen update.
Laurent Vivier [Fri, 7 Jan 2022 10:50:49 +0000 (11:50 +0100)]
q800: fix segfault with invalid MacROM
"qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault
in q800_init().
This happens because the code doesn't check that rom_ptr() returned
a non-NULL pointer .
To avoid NULL pointer, don't allow 0 sized file and use bios_size with
rom_ptr().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220107105049.961489-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Richard Henderson [Sat, 8 Jan 2022 17:37:59 +0000 (09:37 -0800)]
Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging
bsd-user: arm (32-bit) support
This series of patches brings in 32-bit arm support for bsd-user. It implements
all the bits needed to do image activation, signal handling, stack management
and threading. This allows us to get to the "Hello World" level. The arm and x86
code are now the same as in the bsd-user fork. For full context, the fork is at
https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz (though the the recent
sig{bus,segv} needed updates are incomplete).
v5 changes:
o Moved to using the CPUArchState typedef and move
set_sigtramp_args, get_mcontext, set_mcontext, and
get_ucontext_sigreturn prototypes to
bsd-user/freebsd/target_os_ucontext.h
o Fix issues with arm's set_mcontext related to masking
and remove an unnecessary check.
We're down to only one hunk needing review:
bsd-user/arm/target_arch_signal.c: arm set_mcontext
Warnings that should be ignored:
o make checkpatch has a couple of complaints about the comments for the
signal trampoline, since it's a false positive IMHO.
WARNING: Block comments use a leading /* on a separate line
+ /* 8 */ sys_sigreturn,
WARNING: Block comments use a leading /* on a separate line
+ /* 9 */ sys_exit
# gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST
# gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100
# gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown]
# gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown]
# gpg: aka "Warner Losh <imp@freebsd.org>" [unknown]
# gpg: aka "Warner Losh <imp@village.org>" [unknown]
# gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100
* tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits)
bsd-user: add arm target build
bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE
bsd-user/arm/signal.c: arm get_ucontext_sigreturn
bsd-user/arm/signal.c: arm set_mcontext
bsd-user/arm/signal.c: arm get_mcontext
bsd-user/arm/signal.c: arm set_sigtramp_args
bsd-user/arm/target_arch_signal.h: Define size of *context_t
bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals
bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack
bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl
bsd-user/arm/target_arch_elf.h: arm get hwcap
bsd-user/arm/target_arch_elf.h: arm defines for ELF
bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread
bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
bsd-user/arm/target_arch_reg.h: Implement core dump register copying
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions
bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions
bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 8 Jan 2022 06:09:24 +0000 (22:09 -0800)]
Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging
Second RISC-V PR for QEMU 7.0
- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions
# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 23:08:04 +0000 (17:08 -0600)]
bsd-user/arm/target_arch_signal.h: Define size of *context_t
Define the native sizes of mcontext_t and ucontext_t so that the tests
in target_os_ucontext.h ensure the size of arm's version of these
structures is correct.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 23 Sep 2021 15:12:12 +0000 (09:12 -0600)]
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
Various parameters describing the layout of the ARM address space. In
addition, define routines to get the stack pointer and to set the second
return value.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 23 Sep 2021 15:08:21 +0000 (09:08 -0600)]
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
Implement the system call dispatch. This implements all three kinds of
system call: direct and the two indirect variants. It handles all the
special cases for thumb as well.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
EXCP_YIELD. The first two generate a signal to the emulated
binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
nops.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Mikaël Urankar <mikael.urankar@gmail.com> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Add a boiler plate CPU loop that does nothing except return an error for
all traps.
Signed-off-by: Sean Bruno <sbruno@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 23 Sep 2021 14:29:39 +0000 (08:29 -0600)]
bsd-user/arm/target_syscall.h: Add copyright and update name
The preferred name for the 32-bit arm is now armv7. Update the name to
reflect that. In addition, add Stacey's copyright to this file and
update the include guards to the new convention.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 22:34:48 +0000 (16:34 -0600)]
bsd-user: create a per-arch signal.c file
Create a place-holder signal.c file for each of the architectures that
are currently built. In the future, some code that's currently inlined
in target_arch_signal.h will live here.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Fri, 29 Oct 2021 14:39:01 +0000 (08:39 -0600)]
bsd-user/freebsd: Create common target_os_ucontext.h file
FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from sys/_ucontext.h with the comments about layout removed
because we don't support ancient FreeBSD binaries.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 22:31:27 +0000 (16:31 -0600)]
bsd-user/mips*: Remove mips support
FreeBSD is dropping support for mips starting with FreeBSD 14. mips
support has been removed from the bsd-user fork because updating it for
new signal requirements will take too much time. Remove it here since it
is a distraction.
Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Mon, 20 Dec 2021 06:49:16 +0000 (16:49 +1000)]
target/riscv: Implement the stval/mtval illegal instruction
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
Alistair Francis [Mon, 20 Dec 2021 06:49:15 +0000 (16:49 +1000)]
target/riscv: Fixup setting GVA
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
Alistair Francis [Mon, 20 Dec 2021 06:49:14 +0000 (16:49 +1000)]
target/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-2-alistair.francis@opensource.wdc.com
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:08 +0000 (22:01 +0100)]
target/riscv: actual functions to realize crs 128-bit insns
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:07 +0000 (22:01 +0100)]
target/riscv: modification of the trans_csrxx for 128-bit support
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-18-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:06 +0000 (22:01 +0100)]
target/riscv: helper functions to wrap calls to 128-bit csr insns
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-17-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:04 +0000 (22:01 +0100)]
target/riscv: support for 128-bit M extension
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:03 +0000 (22:01 +0100)]
target/riscv: support for 128-bit arithmetic instructions
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:00 +0000 (22:01 +0100)]
target/riscv: support for 128-bit bitwise instructions
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-11-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:59 +0000 (22:00 +0100)]
target/riscv: accessors to registers upper part and 128-bit load/store
Get function to retrieve the 64 top bits of a register, stored in the gprh
field of the cpu state. Set function that writes the 128-bit value at once.
The access to the gprh field can not be protected at compile time to make
sure it is accessed only in the 128-bit version of the processor because we
have no way to indicate that the misa_mxl_max field is const.
The 128-bit ISA adds ldu, lq and sq. We provide support for these
instructions. Note that (a) we compute only 64-bit addresses to actually
access memory, cowardly utilizing the existing address translation mechanism
of QEMU, and (b) we assume for now little-endian memory accesses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:58 +0000 (22:00 +0100)]
target/riscv: moving some insns close to similar insns
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-9-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:57 +0000 (22:00 +0100)]
target/riscv: setup everything for rv64 to support rv128 execution
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:55 +0000 (22:00 +0100)]
target/riscv: separation of bitwise logic and arithmetic helpers
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-6-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:54 +0000 (22:00 +0100)]
target/riscv: additional macros to check instruction support
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-5-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:53 +0000 (22:00 +0100)]
qemu/int128: addition of div/rem 128-bit operations
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-4-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:00:51 +0000 (22:00 +0100)]
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philipp Tomsich [Thu, 6 Jan 2022 13:40:20 +0000 (14:40 +0100)]
target/riscv: Fix position of 'experimental' comment
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
them to be enabled by default, the comment about experimental
extensions was kept in place above them. This moves it down a few
lines to only cover experimental extensions.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106134020.1628889-1-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Wed, 5 Jan 2022 02:22:46 +0000 (10:22 +0800)]
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use require_scale_rvf() to check
whether RVF/RVD is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Wed, 5 Jan 2022 02:22:45 +0000 (10:22 +0800)]
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
floating-point, and vfwcvt.f.f.v convert double-width floating-point to
single-width floating-point. Therefore, should use require_scale_rvf() to
check whether RVF/RVD is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Wed, 5 Jan 2022 02:22:44 +0000 (10:22 +0800)]
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 5 Jan 2022 01:42:48 +0000 (09:42 +0800)]
roms/opensbi: Upgrade from v0.9 to v1.0
Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
The v1.0 release includes the following commits:
ec5274b platform: implement K210 system reset 5487cf0 include: sbi: Simplify HSM state define names 8df1f9a lib: sbi: Use SBI_HSM_STATE_xyz defines instead of SBI_STATE_xyz defines 7c867fd lib: sbi: Rename sbi_hsm_hart_started_mask() function 638c948 lib: sbi: Remove redundant sbi_hsm_hart_started() function ca864a9 lib: sbi: Fix error codes returned by HSM start() and stop() functions 6290a22 include: sbi: Add HSM suspend related defines 4b05df6 lib: sbi: Add sbi_hart_reinit() function 807d71c include: sbi: Add hart_suspend() platform callback 7475689 lib: sbi: Implement SBI HSM suspend function b9cf617 include: sbi: Upgrade SBI implementation version to v0.3 50d4fde lib: Remove redundant sbi_platform_ipi_clear() calls ff5bd94 include: sbi: SBI function IDs for RFENCE extension 22d8ee9 firmware: Use lla to access all global symbols 0f20e8a firmware: Support position independent execution ddad02d lib: sbi: illegal CSR 0x306 access in hpm_allowed() bfc85c7 include: headers: Replace __ASSEMBLY__ with __ASSEMBLER__ 9190ad1 lib/utils: Support the official clint DT bindings ca3f358 lib/utils: Drop the 'compat' parameter of fdt_plic_fixup() 4edc822 lib/utils: Support fixing up the official DT bindings of PLIC 4ef2f5d firware: optimize the exception exit code 3d8a952 lib: fix csr detect support e71a7c1 firmware: Remove redundant add instruction from trap restore path d4a94ea include: types: Add __aligned(x) to define the minimum alignement d0e406f include: sbi: Allow direct initialization via SPIN_LOCK_INIT() 4d8e2f1 lib: sbi: Replace test-and-set locks by ticket locks 70ffc3e lib: sbi: fix atomic_add_return 27a16b1 docs: fix link to OpenPiton documentation b1df1ac lib: sbi: Domains can be registered only before finalizing domains 7495bce lib: sbi: Add sbi_domain_memregion_init() API 4dc0001 lib: sbi: Add sbi_domain_root_add_memregion() API 8b56980 lib: utils/sys: Add CLINT memregion in the root domain fc37c97 lib: sbi: Make the root domain instance global variable e7e4bcd lib: utils: Copy over restricted root domain memregions to FDT domains f41196a lib: sbi: Make sbi_domain_memregion_initfw() a local function c5d0645 lib: utils: Implement "64bit-mmio" property parsing 49e422c lib: utils: reset: Add T-HEAD sample platform reset driver 0d56293 lib: sbi: Fix sbi_domain_root_add_memregion() for merging memregions bf3ef53 firmware: Enable FW_PIC by default 1db8436 platform: Remove platform/thead 6d1642f docs: generic: Add T-HEAD C9xx series processors a3689db lib: sbi: Remove domains_root_regions() platform callback 068ca08 lib: sbi: Simplify console platform operations 559a8f1 lib: sbi: Simplify timer platform operations dc39c7b lib: sbi: Simplify ipi platform operations 043d088 lib: sbi: Simplify system reset platform operations a84a1dd lib: sbi: Simplify HSM platform operations e9a27ab lib: sbi: Show devices provided by platform in boot prints 632e27b docs/platform: sifive_fu540: Update U-Boot defconfig name 117fb6d lib: utils/serial: Add support for Gaisler APBUART 552f53f docs: platform: Sort platform names d4177e7 docs: platform: Describe sifive_fu540 as supported generic platform 26998f3 platform: Remove sifive/fu540 platform f90c4c2 lib: sbi: Have spinlock checks return bool e822b75 lib: utils/serial: Support Synopsys DesignWare APB UART 6139ab2 Makefile: unconditionally disable SSP c9ef2bc lib: utils: Add strncpy macro to libfdt_env.h ee7c2b2 lib: utils/fdt: Don't use sbi_string functions fe92347 lib: utils/fdt: Replace strcmp with strncmp b2dbbc0 lib: Check region base for merging in sbi_domain_root_add_memregion() 54d7def lib: utils: Try other FDT drivers when we see SBI_ENODEV d9ba653 docs: debugging OpenSBI 66c4fca lib: utils: consider ':' in stdout-path f30b189 lib: sbi_scratch: remove owner from sbi_scratch_alloc_offset a03ea2e platform: andes/ae350: Cosmetic fixes in plicsw.c b32fac4 docs/platform: andes-ae350: Fix missing spaces de446cc platform: andes/ae350: Drop plicsw_get_pending() 434198e platform: andes/ae350: Drop plicsw_ipi_sync() 1da3d80 lib: sbi_scratch: zero out scratch memory on all harts 360ab88 lib: utils: missing initialization in thead_reset_init 79f9b42 lib: sbi: Fix GET_F64_REG inline assembly eb90e0a lib: utils/libfdt: Upgrade to v1.6.1 release cdcf907 lib: sign conflict in sbi_tlb_entry_process() 9901794 lib: sign conflict in wake_coldboot_harts() 11c345f lib: simplify sbi_fifo_inplace_update() 4519e29 lib: utils/timer: Add ACLINT MTIMER library 5a049fe lib: utils/ipi: Add ACLINT MSWI library bd5d208 lib: utils: Add FDT parsing API common for both ACLINT and CLINT 56fc5f7 lib: utils/ipi: Add FDT based ACLINT MSWI IPI driver 03d6bb5 lib: utils/timer: Add FDT based ACLINT MTIMER driver a731c7e platform: Replace CLINT library usage with ACLINT library b7f2cd2 lib: utils: reset: unify naming of 'sifive_test' device 197e089 docs/platform: thead-c9xx: Remove FW_PIC=y 17e23b6 platform: generic: Terminate platform.name with null 3e8b31a docs: Add device tree bindings for SBI PMU extension fde28fa lib: sbi: Detect mcountinihibit support at runtime d3a96cc lib: sbi: Remove stray '\' character 0829f2b lib: sbi: Detect number of bits implemented in mhpmcounter 9c9b4ad lib: sbi: Disable m/scounteren & enable mcountinhibit 41ae63c include: Add a list empty check function fd9116b lib: sbi: Remove redundant boot time print statement 49966db lib: sbi: Use csr_read/write_num to read/update PMU counters e7cc7a3 lib: sbi: Add PMU specific platform hooks 13d40f2 lib: sbi: Add PMU support ae72ec0 utils: fdt: Add fdt helper functions to parse PMU DT nodes 37f9b0f lib: sbi: Implement SBI PMU extension 764a17d lib: sbi: Implement firmware counters ec1b8bb lib: sbi: Improve TLB function naming 0e12aa8 platform: generic: Add PMU support 14c7f71 firmware: Minor optimization in _scratch_init() dafaa0f docs: Correct a typo in platform_guide.md abfce9b docs: Make <xyz> visible in the rendered platform guide dcb756b firmware: Remove the sanity checks in fw_save_info() b88b366 firmware: Define a macro for version of struct fw_dynamic_info a76ac44 lib: sbi: Fix sbi_pmu_exit() for systems not having MCOUNTINHIBIT csr 7f1be8a fw_base: Don't mark fw_platform_init as both global and weak 397afe5 fw_base: Put data in .data rather than .text a3d328a firmware: Explicitly pass -pie to the linker, not just the driver 09ad811 firmware: Only default FW_PIC to y if supported 2942777 Makefile: Support building with Clang and LLVM binutils 17729d4 lib: utils: Drop dependency on libgcc by importing part of FreeBSD's libquad e931f38 lib: utils/fdt: Add fdt_parse_phandle_with_args() API 36b8eff lib: utils/gpio: Add generic GPIO configuration library c14f1fe lib: utils/gpio: Add simple FDT based GPIO framework 4c3df2a lib: utils/gpio: Add minimal SiFive GPIO driver e3d6919 lib: utils/reset: Add generic GPIO reset driver 7210e90 firmware: use __SIZEOF_LONG__ for field offsets in fw_dynamic.h f3a8f60 include: types: Use __builtin_offsetof when supported 8a1475b firmware: Remove the unhelpful alignment codes before fdt relocation a4555e5 docs: Document parameters passed to firmware and alignment requirement 2c74dc3 docs: Document FW_PIC compile time option 81eb708 README: Update toolchain information 9890391 Makefile: Manually forward RELAX_FLAG to the assembler when linking with LLD 74db0ac firmware: use _fw_start for load address 217d5e4 generic: fu740: add workaround for CIP-1200 errata ce03c88 lib: utils: remove unused variable in fdt_reset_init e928472 lib: utils: support both of gpio-poweroff, gpio-reset d244f3d lib: sbi: Fix bug in strncmp function when count is 0 47a4765 lib: utils/fdt: Change addr and size to uint64_t e0d1b9d lib: utils/timer: Allow separate base addresses for MTIME and MTIMECMP 7a3a0cc lib: utils: Extend fdt_get_node_addr_size() for multiple register sets f3a0eb8 lib: utils/fdt: Extend fdt_parse_aclint_node() function b35f782 lib: utils/timer: Allow ACLINT MTIMER supporting only 32-bit MMIO 7aa6c9a lib: utils/timer: Simplify MTIMER synchronization 33eac76 lib: sbi: Fix bug in sbi_ecall_rfence that misses checking ee27437 lib: sbi_trap: Restore redirect for access faults b1d3e91 payloads/test: Add support for SBI v0.2 ecalls bd316e2 lib: sbi: Correct typo in faults delegation CSR name c262306 lib: sbi: protect dprintf output with spinlock 1718b16 lib: sbi: Checking fifo validness in sbi_fifo_is_empty and is_full bd35521 lib: sbi: Refine the way to construct platform features 0274a96 lib: utils/reset: Sort fdt_reset driver list 395ff7e lib: utils/reset: Add a sunxi watchdog reset driver 3477f08 lib: sbi: fix ctz bug 12753d2 lib: sbi: add some macros to detect BUG at runtime 51113fe lib: sbi: Add BUG() macro for csr_read/write_num() and misa_string() 72154f4 lib: utils/fdt: Add fdt_parse_timebase_frequency() function 12e7af9 lib: sbi: Add timer frequency to struct sbi_timer_device 6355155 lib: sbi: Print timer frequency at boot time 9d0ab35 lib: sbi: Add generic timer delay loop function fa59dd3 lib: utils/reset: use sbi_timer_mdelay() in gpio reset driver 754d511 lib: utils: identify supported GPIO reset methods 516161c lib: sbi: convert reset to list 9283d50 lib: sbi: add priority for reset handler c38973e lib: sbi: Save context for all non-retentive suspend types 67cbbcb lib: sbi: system reset with invalid parameters 422eda4 Makefile: Add build time and compiler info string 78c2b19 lib: utils/irqchip: Automatically delegate T-HEAD PLIC access 309e8bd lib: utils/reset: Register separate GPIO system reset devices 723aa88 lib: sbi: Refine addr format in sbi_printf c891acc include: sbi_utils: Introduce an helper to get fdt base address 013ba4e lib: sbi: Fix GPA passed to __sbi_hfence_gvma_xyz() functions 0979ffd lib: utils/gpio: use list for drivers 2fe2f55 lib: sbi: move sbi_boot_print_general() 57f094e platform: generic: move fdt_reset_init to final_init be245ac lib: sbi: error handling in fdt_reset_init() a74daf2 riscv: Add new CSRs introduced by Sscofpmf[1] extension 7084ad9 lib: sbi: Update csr_read/write_num for PMU 867c653 lib: sbi: Detect Sscofpmf extension at run time 9134c36 lib: sbi: Delegate PMU counter overflow interrupt to S mode 730f01b lib: sbi: Support sscofpmf extension in OpenSBI 2363f95 lib: sbi: Always enable access for all counters 0c304b6 lib: sbi: Allow programmable counters to monitor cycle/instret events 1e14732 lib: sbi: Reset the mhpmevent value upon counter reset b628cfd lib: sbi: Counter info width should be zero indexed b28f070 lib: sbi: Enable PMU extension for platforms without mcountinhibit 15906a3 lib: utils: Rename the prefix in PMU DT properties b8845e4 lib: sbi: Fix initial value mask while updating the counters 31fe5a7 lib: sbi: Fix PMP address bits detection 94eba23 lib: utils/reset: add priority to gpio reset 1d462e0 lib: utils/reset: separate driver init func 2c964a2 lib: utils/i2c: Add generic I2C configuration library 6ca6bca lib: utils/i2c: Add simple FDT based I2C framework 13a1158 lib: utils/i2c: Add minimal SiFive I2C driver f374496 platform: sifive_fu740: add platform reset driver d335a17 lib: sbi: clear pmpcfg.A before setting in pmp_set() 52af6e4 lib: utils: Add LiteX UART support 22d556d lib: sbi: Fix spelling of "address" in sbi_domain.c 7a22c78 lib: sbi: Fix missing space 7e77706 lib: sbi: Resolve the uninitialized complaint in sbi_pmu 14faee6 lib: sbi: Improve fatal error handling 2428987 lib: pmu: support the event ID encoded by a bitmap. 66fbcc0 docs/platform: spike: Enhance Spike examples 460041c lib: pmu: check SSCOF before masking 69d7e53 Makefile: Fix -msave-restore compile warning with CLANG-10 (or lower) d249d65 lib: sbi: Fix compile errors using -Os option f270359 Makefile: Improve the method to disable -m(no-)save-restore option 2082153 lib: sbi: simplify pmp_set(), pmp_get() d30bde3 firmware: Move memcpy/memset mapping to fw_base.S 48f91ee include: Bump-up version to 1.0
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Alistair Francis [Wed, 5 Jan 2022 21:39:36 +0000 (07:39 +1000)]
hw/riscv: Use error_fatal for SoC realisation
When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.
Currently a user can see this:
$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display none -drive if=pflash
QEMU 6.1.93 monitor - type 'help' for more information
(qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_u_otp.c:229:
qemu-system-riscv64: OTP drive size < 16K
Aborted (core dumped)
Which this patch addresses
Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com>
Alistair Francis [Wed, 5 Jan 2022 21:39:35 +0000 (07:39 +1000)]
target/riscv: Enable the Hypervisor extension by default
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com>
Alistair Francis [Wed, 5 Jan 2022 21:39:33 +0000 (07:39 +1000)]
hw/intc: sifive_plic: Cleanup remaining functions
We can remove the original sifive_plic_irqs_pending() function and
instead just use the sifive_plic_claim() function (renamed to
sifive_plic_claimed()) to determine if any interrupts are pending.
This requires move the side effects outside of sifive_plic_claimed(),
but as they are only invoked once that isn't a problem.
We have also removed all of the old #ifdef debugging logs, so let's
cleanup the last remaining debug function while we are here.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-5-alistair.francis@opensource.wdc.com>
Alistair Francis [Wed, 5 Jan 2022 21:39:32 +0000 (07:39 +1000)]
hw/intc: sifive_plic: Cleanup the read function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-4-alistair.francis@opensource.wdc.com>
Alistair Francis [Wed, 5 Jan 2022 21:39:31 +0000 (07:39 +1000)]
hw/intc: sifive_plic: Cleanup the write function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-3-alistair.francis@opensource.wdc.com>
Alistair Francis [Wed, 5 Jan 2022 21:39:30 +0000 (07:39 +1000)]
hw/intc: sifive_plic: Add a reset function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-2-alistair.francis@opensource.wdc.com>
Jim Shu [Tue, 4 Jan 2022 06:34:08 +0000 (14:34 +0800)]
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220104063408.658169-3-jim.shu@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
projects / users / dwmw2 / qemu.git / log