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6 months agoclk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
Varadarajan Narayanan [Fri, 13 Dec 2024 10:58:08 +0000 (16:28 +0530)]
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks

Use the icc-clk framework to enable few clocks to be able to
create paths and use the peripherals connected on those NoCs.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241213105808.674620-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: interconnect: Add Qualcomm IPQ5424 support
Varadarajan Narayanan [Fri, 13 Dec 2024 10:58:07 +0000 (16:28 +0530)]
dt-bindings: interconnect: Add Qualcomm IPQ5424 support

Add master/slave ids for Qualcomm IPQ5424 Network-On-Chip
interfaces. This will be used by the gcc-ipq5424 driver
for providing interconnect services using the icc-clk framework.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241213105808.674620-1-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: Add SM6115 LPASSCC
Konrad Dybcio [Thu, 12 Dec 2024 00:25:51 +0000 (00:25 +0000)]
clk: qcom: Add SM6115 LPASSCC

SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.

Add the required code to support them.

[alexey.klimov] fixed compilation errors after rebase,
slightly changed the commit message

Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241212002551.2902954-3-alexey.klimov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
Konrad Dybcio [Thu, 12 Dec 2024 00:25:50 +0000 (00:25 +0000)]
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller

SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.

Add bindings for it.

Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[alexey.klimov slightly changed the commit message]
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org
[bjorn: Adjusted Konrad's address]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
Amit Pundir [Mon, 9 Dec 2024 17:49:12 +0000 (23:19 +0530)]
clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs

Similar to the earlier fixes meant for sm8x50 and x1e platforms,
we have to stop using the shared clk ops for sdm845 QUPs as well.

As Stephen Boyd pointed out in earlier fixes, there wasn't a problem
to mark QUP clks shared until we started parking shared RCGs at clk
registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs
upon registration"). Parking at init is actually harmful to the UART
when earlycon is used. If the device is pumping out data while the
frequency changes and we see garbage on the serial console until the
driver can probe and actually set a proper frequency.

This patch reverts the QUP clk sharing ops part of commit 06391eddb60a
("clk: qcom: Add Global Clock controller (GCC) driver for SDM845"), so
that the QUPs on sdm845 don't get parked during clk registration and
break UART operations.

Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration")
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Link: https://lore.kernel.org/r/20241209174912.2526928-1-amit.pundir@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: gcc-sdm845: Add general purpose clock ops
Dzmitry Sankouski [Mon, 18 Nov 2024 10:15:21 +0000 (13:15 +0300)]
clk: qcom: gcc-sdm845: Add general purpose clock ops

SDM845 has "General Purpose" clocks that can be muxed to
SoC pins to clock various external devices.
Those clocks may be used as e.g. PWM sources for external peripherals.

GPCLK can in theory have arbitrary value depending on the use case, so
the concept of frequency tables, used in rcg2 clock driver, is not
efficient, because it allows only defined frequencies.

Introduce clk_rcg2_gp_ops, which automatically calculate clock
mnd values for arbitrary clock rate. The calculation done as follows:
- upon determine rate request, we calculate m/n/pre_div as follows:
  - find parent(from our client's assigned-clock-parent) rate
  - find scaled rates by dividing rates on its greatest common divisor
  - assign requested scaled rate to m
  - factorize scaled parent rate, put multipliers to n till max value
    (determined by mnd_width)
- validate calculated values with *_width:
  - if doesn't fit, delete divisor and multiplier by 2 until fit
- return determined rate

Limitations:
- The driver doesn't select a parent clock (it may be selected by client
  in device tree with assigned-clocks, assigned-clock-parents properties)

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-3-ac8e36a3aa65@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: clk-rcg2: split __clk_rcg2_configure function
Dzmitry Sankouski [Mon, 18 Nov 2024 10:15:20 +0000 (13:15 +0300)]
clk: qcom: clk-rcg2: split __clk_rcg2_configure function

__clk_rcg2_configure function does 2 things -
configures parent and mnd values. In order to
be able to add new clock options, we should split.

Move __clk_rcg2_configure logic on 2 functions:
- __clk_rcg2_configure_parent which configures clock parent
- __clk_rcg2_configure_mnd which configures mnd values

__clk_rcg2_configure delegates to mentioned functions.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-2-ac8e36a3aa65@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: clk-rcg2: document calc_rate function
Dzmitry Sankouski [Mon, 18 Nov 2024 10:15:19 +0000 (13:15 +0300)]
clk: qcom: clk-rcg2: document calc_rate function

Update calc_rate docs to reflect, that pre_div
is not pure divisor, but a register value, and requires conversion.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-1-ac8e36a3aa65@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
Abel Vesa [Tue, 7 Jan 2025 15:55:23 +0000 (17:55 +0200)]
clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC

Allowing the usb_2 controller GDSC to be turned off during system suspend
renders the controller unable to resume.

So use PWRSTS_RET_ON instead in order to make sure this the GDSC doesn't
go down.

Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Cc: stable@vger.kernel.org # 6.8
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250107-x1e80100-clk-gcc-fix-usb2-gdsc-pwrsts-v1-1-e15d1a5e7d80@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: ipq5424: add gcc_xo_clk
Manikanta Mylavarapu [Tue, 10 Dec 2024 06:41:10 +0000 (12:11 +0530)]
clk: qcom: ipq5424: add gcc_xo_clk

The gcc_xo_clk is required for the functionality of the WiFi
copy engine block. Therefore, add the gcc_xo_clk in gcc driver.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20241210064110.130466-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
Manikanta Mylavarapu [Tue, 10 Dec 2024 06:41:09 +0000 (12:11 +0530)]
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro

The GCC_XO_CLK is required for the functionality of the WiFi
copy engine block. Therefore, add the GCC_XO_CLK macro.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241210064110.130466-2-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
Manikanta Mylavarapu [Tue, 17 Dec 2024 11:39:09 +0000 (17:09 +0530)]
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro

The gcc_apss_dbg clk is access protected by trust zone, and accessing
it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk macro.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20241217113909.3522305-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: ipq5424: remove apss_dbg clock
Manikanta Mylavarapu [Tue, 17 Dec 2024 11:39:08 +0000 (17:09 +0530)]
clk: qcom: ipq5424: remove apss_dbg clock

The gcc_apss_dbg clk is access protected by trust zone, and accessing
it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk
from the gcc driver.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20241217113909.3522305-2-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
Richard Acayan [Wed, 18 Dec 2024 23:17:31 +0000 (18:17 -0500)]
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible

The camera clocks on SDM670 and SDM845 have no significant differences
that would require a change in the clock controller driver. The only
difference is the clock frequency at each level of the power domains,
which is not specified in the clock driver. There should still be a
compatible specific to the SoC, so add the compatible for SDM670 with
the SDM845 compatible as fallback.

Link: https://android.googlesource.com/kernel/msm/+/d4dc50c0a9291bd99895d4844f973421c047d267/drivers/clk/qcom/camcc-sdm845.c#2048
Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Suggested-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/7d26a62b-b898-4737-bd53-f49821e3b471@linaro.org
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241218231729.270137-8-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: mmcc-msm8960: handle LVDS clock
Dmitry Baryshkov [Tue, 24 Dec 2024 10:12:16 +0000 (12:12 +0200)]
clk: qcom: mmcc-msm8960: handle LVDS clock

On APQ8064 the DSI2_PIXEL_SRC clock can be used either to drive the
second DSI host or to drive the LCDC controller. Add LVDS PLL as
possible source to the clock and LVDS output clock. The DSI2_PIXEL_SRC
clock has separate path to be used for the LVDS clock.  To represent
both DSI and LVDS clocks properly, add intermediate clock which toggles
the enable bit and make DSI2_PIXEL_CLK clock just check for the HALT
bit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-4-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: rcg: add 1/1 pixel clock ratio
Dmitry Baryshkov [Tue, 24 Dec 2024 10:12:15 +0000 (12:12 +0200)]
clk: qcom: rcg: add 1/1 pixel clock ratio

LVDS clocks require 1:1 ration support in the table used by
clk_rcg_pixel_ops. Add corresponding divider to the table.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-3-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom,mmcc-msm8960: add LCDC-related clocks
Dmitry Baryshkov [Tue, 24 Dec 2024 10:12:14 +0000 (12:12 +0200)]
dt-bindings: clock: qcom,mmcc-msm8960: add LCDC-related clocks

APQ8064 / MSM8960 have separate LVDS / LCDC clock, driving the MDP4 LCD
controller. Add corresponding indices to clock controller bindings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-2-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom,mmcc: support LVDS PLL input for apq8064
Dmitry Baryshkov [Tue, 24 Dec 2024 10:12:13 +0000 (12:12 +0200)]
dt-bindings: clock: qcom,mmcc: support LVDS PLL input for apq8064

APQ8064 / MSM8960 have separate LVDS PLL driving the LVDS / LCDC clock.
Add corresponding input to clock controller bindings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-1-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: Add CMN PLL clock controller driver for IPQ SoC
Luo Jie [Fri, 3 Jan 2025 07:31:35 +0000 (15:31 +0800)]
clk: qcom: Add CMN PLL clock controller driver for IPQ SoC

The CMN PLL clock controller supplies clocks to the hardware
blocks that together make up the Ethernet function on Qualcomm
IPQ SoCs and to GCC. The driver is initially supported for
IPQ9574 SoC.

The CMN PLL clock controller expects a reference input clock
from the on-board Wi-Fi block acting as clock source. The input
reference clock needs to be configured to one of the supported
clock rates.

The controller supplies a number of fixed-rate output clocks.
For the IPQ9574, there is one output clock of 353 MHZ to PPE
(Packet Process Engine) hardware block, three 50 MHZ output
clocks and an additional 25 MHZ output clock supplied to the
connected Ethernet devices. The PLL also supplies a 24 MHZ
clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25
MHZ clock to PCS.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoMerge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into clk-for...
Bjorn Andersson [Mon, 6 Jan 2025 23:41:49 +0000 (17:41 -0600)]
Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into clk-for-6.14

Merge the IPQ CMN PLL clock binding through a topic branch to make it
available to DeviceTree source branches as well.

6 months agodt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC
Luo Jie [Fri, 3 Jan 2025 07:31:34 +0000 (15:31 +0800)]
dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC

The CMN PLL controller provides clocks to networking hardware blocks
and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
on-chip Wi-Fi, and produces output clocks at fixed rates. These output
rates are predetermined, and are unrelated to the input clock rate.
The primary purpose of CMN PLL is to supply clocks to the networking
hardware such as PPE (packet process engine), PCS and the externally
connected switch or PHY device. The CMN PLL block also outputs fixed
rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
clock supplied to GCC.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: dispcc-sm8750: Add SM8750 Display clock controller
Krzysztof Kozlowski [Mon, 6 Jan 2025 13:44:31 +0000 (14:44 +0100)]
clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller

Add driver for Display clock controller (DISPCC) in Qualcomm SM8750.
The device has several differences against SM8650, including new Pongo
PLLs and different clock parents, thus no compatibility or driver
re-usage.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-3-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: clk-alpha-pll: Add Pongo PLL
Krzysztof Kozlowski [Mon, 6 Jan 2025 13:44:30 +0000 (14:44 +0100)]
clk: qcom: clk-alpha-pll: Add Pongo PLL

Add support for Pongo type of PLL clocks, used in Qualcomm SM8750 SoC.
Notable difference comparing to other PLLs is the need for calibration
for internally generated clock followed by wait_for_pll().  This is done
in configure call and at this time clocks are not yet registered, thus
wait_for_pll() cannot use clk_hw_get_name.  Locking during this
calibration requires much more time, thus increase the timeout in
wait_for_pll().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-2-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoMerge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into clk-for-6.14
Bjorn Andersson [Mon, 6 Jan 2025 16:30:24 +0000 (10:30 -0600)]
Merge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into clk-for-6.14

Merge SM8750 display clock controller bindings through topic branch, to
make available to DeviceTree source branch as well.

6 months agodt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCC
Krzysztof Kozlowski [Mon, 6 Jan 2025 13:44:29 +0000 (14:44 +0100)]
dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCC

Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC).
Bindings are similar to existing SM8550 and SM8650 (same clock inputs),
but the clock hierarchy is quite different and these are not compatible
devices.

The binding header was copied from downstream sources, so I retained
original copyrights.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: Add TCSR clock driver for SM8750
Taniya Das [Wed, 4 Dec 2024 19:37:20 +0000 (11:37 -0800)]
clk: qcom: Add TCSR clock driver for SM8750

The TCSR clock controller found on SM8750 provides refclks
for PCIE, USB and UFS. Add clock driver for it.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-8-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: Add support for GCC on SM8750
Taniya Das [Wed, 4 Dec 2024 19:37:18 +0000 (11:37 -0800)]
clk: qcom: Add support for GCC on SM8750

Add support for GCC for SM8750 platform.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-6-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs
Taniya Das [Wed, 4 Dec 2024 19:37:16 +0000 (11:37 -0800)]
clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs

Add clock ops for Taycan PLL, add the register offsets for supporting
the PLL.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-4-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: rpmh: Add support for SM8750 rpmh clocks
Taniya Das [Wed, 4 Dec 2024 19:37:15 +0000 (11:37 -0800)]
clk: qcom: rpmh: Add support for SM8750 rpmh clocks

Add the RPMH clocks present in SM8750 SoC.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-3-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: rpmh: Sort the match table alphabetically
Taniya Das [Wed, 4 Dec 2024 19:37:14 +0000 (11:37 -0800)]
clk: qcom: rpmh: Sort the match table alphabetically

Update the match table for SC7280 to sort it in alphabetical order.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-2-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom-rpmhcc: Add RPMHCC for SM8750
Taniya Das [Wed, 4 Dec 2024 19:37:13 +0000 (11:37 -0800)]
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for SM8750

Update the documentation for clock rpmh driver on SM8750 SoCs.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-1-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoMerge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' into clk...
Bjorn Andersson [Mon, 6 Jan 2025 16:27:11 +0000 (10:27 -0600)]
Merge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' into clk-for-6.14

Merge the SM8750 GCC and TCSR clock bindings through topic branch, to
allow merging into DeviceTree source branch as well.

6 months agodt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller
Taniya Das [Wed, 4 Dec 2024 19:37:19 +0000 (11:37 -0800)]
dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller

Add bindings documentation for the SM8750 Clock Controller.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agodt-bindings: clock: qcom: Add SM8750 GCC
Taniya Das [Wed, 4 Dec 2024 19:37:17 +0000 (11:37 -0800)]
dt-bindings: clock: qcom: Add SM8750 GCC

Add device tree bindings for the global clock controller on Qualcomm
SM8750 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: gcc-mdm9607: Fix cmd_rcgr offset for blsp1_uart6 rcg
Satya Priya Kakitapalli [Fri, 20 Dec 2024 09:50:48 +0000 (15:20 +0530)]
clk: qcom: gcc-mdm9607: Fix cmd_rcgr offset for blsp1_uart6 rcg

Fix cmd_rcgr offset for blsp1_uart6_apps_clk_src on mdm9607 platform.

Fixes: 48b7253264ea ("clk: qcom: Add MDM9607 GCC driver")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220095048.248425-1-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: camcc-x1e80100: Set titan_top_gdsc as the parent GDSC of subordinate GDSCs
Bryan O'Donoghue [Fri, 27 Dec 2024 13:23:03 +0000 (13:23 +0000)]
clk: qcom: camcc-x1e80100: Set titan_top_gdsc as the parent GDSC of subordinate GDSCs

The Titan TOP GDSC is the parent GDSC for all other GDSCs in the CAMCC
block. None of the subordinate blocks will switch on without the parent
GDSC switched on.

Fixes: 76126a5129b5 ("clk: qcom: Add camcc clock driver for x1e80100")
Acked-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20241227-b4-linux-next-24-12-16-titan-top-gdsc-v1-1-c96ef62fc307@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: Make GCC_8150 depend on QCOM_GDSC
Konrad Dybcio [Sat, 26 Oct 2024 10:58:13 +0000 (12:58 +0200)]
clk: qcom: Make GCC_8150 depend on QCOM_GDSC

Like all other non-ancient Qualcomm clock drivers, QCOM_GDSC is
required, as the GCC driver defines and instantiates a bunch of GDSCs.

Add the missing dependency.

Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Closes: https://lore.kernel.org/linux-arm-msm/ab85f2ae-6c97-4fbb-a15b-31cc9e1f77fc@linaro.org/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20241026-topic-8150gcc_kconfig-v1-1-3772013d8804@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: clk-alpha-pll: fix alpha mode configuration
Gabor Juhos [Mon, 21 Oct 2024 17:32:48 +0000 (19:32 +0200)]
clk: qcom: clk-alpha-pll: fix alpha mode configuration

Commit c45ae598fc16 ("clk: qcom: support for alpha mode configuration")
added support for configuring alpha mode, but it seems that the feature
was never working in practice.

The value of the alpha_{en,mode}_mask members of the configuration gets
added to the value parameter passed to the regmap_update_bits() function,
however the same values are not getting applied to the bitmask. As the
result, the respective bits in the USER_CTL register are never modifed
which leads to improper configuration of several PLLs.

The following table shows the PLL configurations where the 'alpha_en_mask'
member is set and which are passed as a parameter for the
clk_alpha_pll_configure() function. In the table the 'expected rate' column
shows the rate the PLL should run at with the given configuration, and
the 'real rate' column shows the rate the PLL runs at actually. The real
rates has been verified on hardwareOn IPQ* platforms, on other platforms,
those are computed values only.

      file                 pll         expected rate   real rate
  dispcc-qcm2290.c     disp_cc_pll0      768.0 MHz     768.0 MHz
  dispcc-sm6115.c      disp_cc_pll0      768.0 MHz     768.0 MHz
  gcc-ipq5018.c        ubi32_pll        1000.0 MHz !=  984.0 MHz
  gcc-ipq6018.c        nss_crypto_pll   1200.0 MHz    1200.0 MHz
  gcc-ipq6018.c        ubi32_pll        1497.6 MHz != 1488.0 MHz
  gcc-ipq8074.c        nss_crypto_pll   1200.0 MHz != 1190.4 MHz
  gcc-qcm2290.c        gpll11            532.0 MHz !=  518.4 MHz
  gcc-qcm2290.c        gpll8             533.2 MHz !=  518.4 MHz
  gcc-qcs404.c         gpll3             921.6 MHz     921.6 MHz
  gcc-sm6115.c         gpll11            600.0 MHz !=  595.2 MHz
  gcc-sm6115.c         gpll8             800.0 MHz !=  787.2 MHz
  gpucc-sdm660.c       gpu_cc_pll0       800.0 MHz !=  787.2 MHz
  gpucc-sdm660.c       gpu_cc_pll1       740.0 MHz !=  729.6 MHz
  gpucc-sm6115.c       gpu_cc_pll0      1200.0 MHz != 1190.4 MHz
  gpucc-sm6115.c       gpu_cc_pll1       640.0 MHz !=  633.6 MHz
  gpucc-sm6125.c       gpu_pll0         1020.0 MHz != 1017.6 MHz
  gpucc-sm6125.c       gpu_pll1          930.0 MHz !=  921.6 MHz
  mmcc-sdm660.c        mmpll8            930.0 MHz !=  921.6 MHz
  mmcc-sdm660.c        mmpll5            825.0 MHz !=  806.4 MHz

As it can be seen from the above, there are several PLLs which are
configured incorrectly.

Change the code to apply both 'alpha_en_mask' and 'alpha_mode_mask'
values to the bitmask in order to configure the alpha mode correctly.

Applying the 'alpha_en_mask' fixes the initial rate of the PLLs showed
in the table above. Since the 'alpha_mode_mask' is not used by any driver
currently, that part of the change causes no functional changes.

Cc: stable@vger.kernel.org
Fixes: c45ae598fc16 ("clk: qcom: support for alpha mode configuration")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20241021-fix-alpha-mode-config-v1-1-f32c254e02bc@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: dispcc-sm6115: remove alpha values from disp_cc_pll0_config
Gabor Juhos [Mon, 28 Oct 2024 18:48:19 +0000 (19:48 +0100)]
clk: qcom: dispcc-sm6115: remove alpha values from disp_cc_pll0_config

Since both the 'alpha' and 'alpha_hi' members of the configuration is
initialized (the latter is implicitly) with zero values, the output
rate of the PLL will be the same whether alpha mode is enabled or not.

Remove the initialization of the alpha* members to make it clear that
the alpha mode is not required to get the desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the clk_alpha_pll_set_rate()
function will get reset the ALPHA_EN bit when the PLL's rate changes,
so dropping 'alpha_en_mask' is safe.

No functional changes intended, compile tested only.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-5-9bc6d712bd76@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: dispcc-qcm2290: remove alpha values from disp_cc_pll0_config
Gabor Juhos [Mon, 28 Oct 2024 18:48:18 +0000 (19:48 +0100)]
clk: qcom: dispcc-qcm2290: remove alpha values from disp_cc_pll0_config

Since both the 'alpha' and 'alpha_hi' members of the configuration is
initialized (the latter is implicitly) with zero values, the output
rate of the PLL will be the same whether alpha mode is enabled or not.

Remove the initialization of the alpha* members to make it clear that
the alpha mode is not required to get the desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the clk_alpha_pll_set_rate()
function will get reset the ALPHA_EN bit when the PLL's rate changes,
so dropping 'alpha_en_mask' is safe.

No functional changes intended, compile tested only.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-4-9bc6d712bd76@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: gcc-ipq6018: remove alpha values from NSS Crypto PLL's config
Gabor Juhos [Mon, 28 Oct 2024 18:48:17 +0000 (19:48 +0100)]
clk: qcom: gcc-ipq6018: remove alpha values from NSS Crypto PLL's config

Since both the 'alpha' and 'alpha_hi' members of the configuration is
initialized with zero values, the output rate of the PLL will be the
same whether alpha mode is enabled or not.

Remove the initialization of the alpha* members to make it clear that
alpha mode is not required to get the desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the clk_alpha_pll_set_rate()
function will get reset the ALPHA_EN bit when the PLL's rate changes,
so dropping 'alpha_en_mask' is safe.

While at it, also add a comment to indicate the frequency the PLL runs
at with the current configuration.

No functional changes, the PLL runs at 1.2 GHz both before and after
the change.

Tested on Xiaomi Mi Router AX1800 (IPQ6018, out-of-tree board).

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-3-9bc6d712bd76@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: apps-ipq-pll: drop 'alpha_en_mask' from IPQ5332 PLL config
Gabor Juhos [Mon, 28 Oct 2024 18:48:16 +0000 (19:48 +0100)]
clk: qcom: apps-ipq-pll: drop 'alpha_en_mask' from IPQ5332 PLL config

Since neither 'alpha' nor 'alpha_hi' is defined in the configuration,
those will be initialized with zero values implicitly. By using zero
alpha values, the output rate of the PLL will be the same whether
alpha mode is enabled or not.

Remove the superfluous initialization of the 'alpha_en_mask' member
to make it clear that enabling alpha mode is not required to get the
desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the
clk_alpha_pll_stromer_plus_set_rate() function will get reset the
ALPHA_EN bit when the PLL's rate changes, so dropping 'alpha_en_mask'
is safe.

While at it, also add a comment to indicate the frequency the PLL
runs at with the current configuration.

No functional changes, the initial rate of the PLL is the same both
before and after the patch.

Tested on Xiaomi Router BE3600 2.5G (IPQ5312, out-of-tree board).

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-2-9bc6d712bd76@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: apss-ipq-pll: drop 'alpha_en_mask' from IPQ5018 PLL config
Gabor Juhos [Mon, 28 Oct 2024 18:48:15 +0000 (19:48 +0100)]
clk: qcom: apss-ipq-pll: drop 'alpha_en_mask' from IPQ5018 PLL config

Since neither 'alpha' nor 'alpha_hi' is defined in the configuration,
those will be initialized with zero values  implicitly. By using zero
alpha values, the output rate of the PLL will be the same whether
alpha mode is enabled or not.

Remove the superfluous initialization of the 'alpha_en_mask' member
to make it clear that enabling alpha mode is not required to get the
desired output rate.

Despite that enabling alpha mode is not needed for the initial
configuration, the set_rate() op might require that it is enabled
already. In this particular case however, the
clk_alpha_pll_stromer_set_rate() function will get reset the
ALPHA_EN bit when the PLL's rate changes, so dropping 'alpha_en_mask'
is safe.

No functional changes, the initial rate of the PLL is the same both
before and after the patch.

Tested on TP-Link Archer AX55 v1 (IPQ5018).

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-1-9bc6d712bd76@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: dispcc-sm6350: Add missing parent_map for a clock
Luca Weiss [Fri, 20 Dec 2024 09:03:31 +0000 (10:03 +0100)]
clk: qcom: dispcc-sm6350: Add missing parent_map for a clock

If a clk_rcg2 has a parent, it should also have parent_map defined,
otherwise we'll get a NULL pointer dereference when calling clk_set_rate
like the following:

  [    3.388105] Call trace:
  [    3.390664]  qcom_find_src_index+0x3c/0x70 (P)
  [    3.395301]  qcom_find_src_index+0x1c/0x70 (L)
  [    3.399934]  _freq_tbl_determine_rate+0x48/0x100
  [    3.404753]  clk_rcg2_determine_rate+0x1c/0x28
  [    3.409387]  clk_core_determine_round_nolock+0x58/0xe4
  [    3.421414]  clk_core_round_rate_nolock+0x48/0xfc
  [    3.432974]  clk_core_round_rate_nolock+0xd0/0xfc
  [    3.444483]  clk_core_set_rate_nolock+0x8c/0x300
  [    3.455886]  clk_set_rate+0x38/0x14c

Add the parent_map property for the clock where it's missing and also
un-inline the parent_data as well to keep the matching parent_map and
parent_data together.

Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350")
Cc: stable@vger.kernel.org
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-2-64f3d04cb2eb@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: gcc-sm6350: Add missing parent_map for two clocks
Luca Weiss [Fri, 20 Dec 2024 09:03:30 +0000 (10:03 +0100)]
clk: qcom: gcc-sm6350: Add missing parent_map for two clocks

If a clk_rcg2 has a parent, it should also have parent_map defined,
otherwise we'll get a NULL pointer dereference when calling clk_set_rate
like the following:

  [    3.388105] Call trace:
  [    3.390664]  qcom_find_src_index+0x3c/0x70 (P)
  [    3.395301]  qcom_find_src_index+0x1c/0x70 (L)
  [    3.399934]  _freq_tbl_determine_rate+0x48/0x100
  [    3.404753]  clk_rcg2_determine_rate+0x1c/0x28
  [    3.409387]  clk_core_determine_round_nolock+0x58/0xe4
  [    3.421414]  clk_core_round_rate_nolock+0x48/0xfc
  [    3.432974]  clk_core_round_rate_nolock+0xd0/0xfc
  [    3.444483]  clk_core_set_rate_nolock+0x8c/0x300
  [    3.455886]  clk_set_rate+0x38/0x14c

Add the parent_map property for two clocks where it's missing and also
un-inline the parent_data as well to keep the matching parent_map and
parent_data together.

Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver")
Cc: stable@vger.kernel.org
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-1-64f3d04cb2eb@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 months agoclk: qcom: clk-rpmh: prevent integer overflow in recalc_rate
Anastasia Belova [Tue, 3 Dec 2024 08:42:31 +0000 (11:42 +0300)]
clk: qcom: clk-rpmh: prevent integer overflow in recalc_rate

aggr_state and unit fields are u32. The result of their
multiplication may not fit in this type.

Add explicit casting to prevent overflow.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: 04053f4d23a4 ("clk: qcom: clk-rpmh: Add IPA clock support")
Cc: stable@vger.kernel.org # 5.4+
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
Link: https://lore.kernel.org/r/20241203084231.6001-1-abelova@astralinux.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: gcc: Add support for QCS615 GCC clocks
Taniya Das [Tue, 22 Oct 2024 11:52:53 +0000 (17:22 +0530)]
clk: qcom: gcc: Add support for QCS615 GCC clocks

Add the global clock controller support for QCS615 SoC.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-4-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: rpmhcc: Add support for QCS615 Clocks
Taniya Das [Tue, 22 Oct 2024 11:52:51 +0000 (17:22 +0530)]
clk: qcom: rpmhcc: Add support for QCS615 Clocks

Add the RPMHCC clocks required for QCS615 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-2-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agodt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for QCS615
Taniya Das [Tue, 22 Oct 2024 11:52:50 +0000 (17:22 +0530)]
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for QCS615

Add bindings and update documentation for clock rpmh driver on QCS615
SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-1-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: spmi-pmic-div: simplify locking with guard()
Krzysztof Kozlowski [Fri, 23 Aug 2024 15:38:45 +0000 (17:38 +0200)]
clk: qcom: spmi-pmic-div: simplify locking with guard()

Simplify error handling (less gotos) over locks with guard().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240823-cleanup-h-guard-clk-qcom-v1-3-68bb9601c9dd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: smd-rpm: simplify locking with guard()
Krzysztof Kozlowski [Fri, 23 Aug 2024 15:38:44 +0000 (17:38 +0200)]
clk: qcom: smd-rpm: simplify locking with guard()

Simplify error handling (less gotos) over locks with guard().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240823-cleanup-h-guard-clk-qcom-v1-2-68bb9601c9dd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: rpm: simplify locking with guard()
Krzysztof Kozlowski [Fri, 23 Aug 2024 15:38:43 +0000 (17:38 +0200)]
clk: qcom: rpm: simplify locking with guard()

Simplify error handling (less gotos) over locks with guard().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240823-cleanup-h-guard-clk-qcom-v1-1-68bb9601c9dd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: gcc-sm8650: Do not turn off PCIe GDSCs during gdsc_disable()
Manivannan Sadhasivam [Thu, 19 Dec 2024 17:00:11 +0000 (22:30 +0530)]
clk: qcom: gcc-sm8650: Do not turn off PCIe GDSCs during gdsc_disable()

With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of PCIe controllers from suspend.

So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.

Cc: stable@vger.kernel.org # 6.8
Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1")
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on QRD8650
Link: https://lore.kernel.org/r/20241219170011.70140-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: gcc-sm8550: Do not turn off PCIe GDSCs during gdsc_disable()
Manivannan Sadhasivam [Thu, 19 Dec 2024 17:00:10 +0000 (22:30 +0530)]
clk: qcom: gcc-sm8550: Do not turn off PCIe GDSCs during gdsc_disable()

With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of PCIe controllers from suspend.

So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.

Cc: stable@vger.kernel.org # 6.2
Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550")
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on QRD8550
Link: https://lore.kernel.org/r/20241219170011.70140-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoclk: qcom: Add X1P42100 GPUCC driver
Konrad Dybcio [Sat, 21 Dec 2024 12:24:11 +0000 (13:24 +0100)]
clk: qcom: Add X1P42100 GPUCC driver

The 8-core X1s have a different GPU subsystem compared to their bigger
cousins, including the clocks part. Add the GPU clock controller driver
to drive these.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-3-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agodt-bindings: clock: qcom,x1e80100-gcc: Add X1P42100
Konrad Dybcio [Sat, 21 Dec 2024 12:24:09 +0000 (13:24 +0100)]
dt-bindings: clock: qcom,x1e80100-gcc: Add X1P42100

X1P42100 is based on X1E80100 and largely reuses the X1E80100's GCC
block, adding a couple wires here and there.

Add a compatible for the X1P4 with a fallback to X1E80100. There are
some additions in the smaller one, that will be added in the future.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-1-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoMerge branch '20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com' into clk...
Bjorn Andersson [Thu, 26 Dec 2024 03:56:50 +0000 (21:56 -0600)]
Merge branch '20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com' into clk-for-6.14

Merge the X1P42100 GPUCC binding through a topic branch to make
available for the DeviceTree branch as well.

7 months agodt-bindings: clock: qcom,x1e80100-gpucc: Extend for X1P42100
Konrad Dybcio [Sat, 21 Dec 2024 12:24:10 +0000 (13:24 +0100)]
dt-bindings: clock: qcom,x1e80100-gpucc: Extend for X1P42100

To make it easier for X1P4 and X1E to share a common device tree base,
extend the existing latter's GPUCC bindings and reuse them on the
former platform.

While not in the same file, it only makes sense to introduce the new
compatible in this commit as well.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agodt-bindings: clock: qcom,sc7280-lpasscorecc: add top-level constraints
Krzysztof Kozlowski [Sat, 17 Aug 2024 09:46:05 +0000 (11:46 +0200)]
dt-bindings: clock: qcom,sc7280-lpasscorecc: add top-level constraints

Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".  Add missing top-level constraints
for reg, clocks and clock-names.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240817094605.27185-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agodt-bindings: clock: qcom,sc7280-lpasscorecc: order properties to match convention
Krzysztof Kozlowski [Sat, 17 Aug 2024 09:46:04 +0000 (11:46 +0200)]
dt-bindings: clock: qcom,sc7280-lpasscorecc: order properties to match convention

By convention we expect first "compatible", then "reg" and then rest.
Order properties to match convention and what is in "required:" block.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240817094605.27185-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoMerge branch '20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com' into clk...
Bjorn Andersson [Mon, 2 Dec 2024 04:04:46 +0000 (22:04 -0600)]
Merge branch '20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com' into clk-for-6.14

Merge QCS615 global clock controller binding through topic branch to
allow constant to be merged into DeviceTree branch as well.

7 months agodt-bindings: clock: qcom: Add QCS615 GCC clocks
Taniya Das [Tue, 22 Oct 2024 11:52:52 +0000 (17:22 +0530)]
dt-bindings: clock: qcom: Add QCS615 GCC clocks

Add device tree bindings for global clock controller on QCS615 SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 months agoLinux 6.13-rc1
Linus Torvalds [Sun, 1 Dec 2024 22:28:56 +0000 (14:28 -0800)]
Linux 6.13-rc1

7 months agoMerge tag 'i2c-for-6.13-rc1-part3' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 1 Dec 2024 21:38:24 +0000 (13:38 -0800)]
Merge tag 'i2c-for-6.13-rc1-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c component probing support from Wolfram Sang:
 "Add OF component probing.

  Some devices are designed and manufactured with some components having
  multiple drop-in replacement options. These components are often
  connected to the mainboard via ribbon cables, having the same signals
  and pin assignments across all options. These may include the display
  panel and touchscreen on laptops and tablets, and the trackpad on
  laptops. Sometimes which component option is used in a particular
  device can be detected by some firmware provided identifier, other
  times that information is not available, and the kernel has to try to
  probe each device.

  Instead of a delicate dance between drivers and device tree quirks,
  this change introduces a simple I2C component probe function. For a
  given class of devices on the same I2C bus, it will go through all of
  them, doing a simple I2C read transfer and see which one of them
  responds. It will then enable the device that responds"

* tag 'i2c-for-6.13-rc1-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  MAINTAINERS: fix typo in I2C OF COMPONENT PROBER
  of: base: Document prefix argument for of_get_next_child_with_prefix()
  i2c: Fix whitespace style issue
  arm64: dts: mediatek: mt8173-elm-hana: Mark touchscreens and trackpads as fail
  platform/chrome: Introduce device tree hardware prober
  i2c: of-prober: Add GPIO support to simple helpers
  i2c: of-prober: Add simple helpers for regulator support
  i2c: Introduce OF component probe function
  of: base: Add for_each_child_of_node_with_prefix()
  of: dynamic: Add of_changeset_update_prop_string

7 months agoMerge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
Linus Torvalds [Sun, 1 Dec 2024 21:10:51 +0000 (13:10 -0800)]
Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull bprintf() removal from Steven Rostedt:

 - Remove unused bprintf() function, that was added with the rest of the
   "bin-printf" functions.

   These are functions that are used by trace_printk() that allows to
   quickly save the format and arguments into the ring buffer without
   the expensive processing of converting numbers to ASCII. Then on
   output, at a much later time, the ring buffer is read and the string
   processing occurs then. The bprintf() was added for consistency but
   was never used. It can be safely removed.

* tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace:
  printf: Remove unused 'bprintf'

7 months agoMerge tag 'timers_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 1 Dec 2024 20:41:21 +0000 (12:41 -0800)]
Merge tag 'timers_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer fixes from Borislav Petkov:

 - Fix a case where posix timers with a thread-group-wide target would
   miss signals if some of the group's threads are exiting

 - Fix a hang caused by ndelay() calling the wrong delay function
   __udelay()

 - Fix a wrong offset calculation in adjtimex(2) when using ADJ_MICRO
   (microsecond resolution) and a negative offset

* tag 'timers_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  posix-timers: Target group sigqueue to current task only if not exiting
  delay: Fix ndelay() spuriously treated as udelay()
  ntp: Remove invalid cast in time offset math

7 months agoMerge tag 'irq_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 1 Dec 2024 20:37:58 +0000 (12:37 -0800)]
Merge tag 'irq_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Borislav Petkov:

 - Move the ->select callback to the correct ops structure in
   irq-mvebu-sei to fix some Marvell Armada platforms

 - Add a workaround for Hisilicon ITS erratum 162100801 which can cause
   some virtual interrupts to get lost

 - More platform_driver::remove() conversion

* tag 'irq_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: Switch back to struct platform_driver::remove()
  irqchip/gicv3-its: Add workaround for hip09 ITS erratum 162100801
  irqchip/irq-mvebu-sei: Move misplaced select() callback to SEI CP domain

7 months agoMerge tag 'x86_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 1 Dec 2024 20:35:37 +0000 (12:35 -0800)]
Merge tag 'x86_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Borislav Petkov:

 - Add a terminating zero end-element to the array describing AMD CPUs
   affected by erratum 1386 so that the matching loop actually
   terminates instead of going off into the weeds

 - Update the boot protocol documentation to mention the fact that the
   preferred address to load the kernel to is considered in the
   relocatable kernel case too

 - Flush the memory buffer containing the microcode patch after applying
   microcode on AMD Zen1 and Zen2, to avoid unnecessary slowdowns

 - Make sure the PPIN CPU feature flag is cleared on all CPUs if PPIN
   has been disabled

* tag 'x86_urgent_for_v6.13_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/CPU/AMD: Terminate the erratum_1386_microcode array
  x86/Documentation: Update algo in init_size description of boot protocol
  x86/microcode/AMD: Flush patch buffer mapping after application
  x86/mm: Carve out INVLPG inline asm for use by others
  x86/cpu: Fix PPIN initialization

7 months agostrscpy: write destination buffer only once
Linus Torvalds [Sun, 1 Dec 2024 17:23:33 +0000 (09:23 -0800)]
strscpy: write destination buffer only once

The point behind strscpy() was to once and for all avoid all the
problems with 'strncpy()' and later broken "fixed" versions like
strlcpy() that just made things worse.

So strscpy not only guarantees NUL-termination (unlike strncpy), it also
doesn't do unnecessary padding at the destination.  But at the same time
also avoids byte-at-a-time reads and writes by _allowing_ some extra NUL
writes - within the size, of course - so that the whole copy can be done
with word operations.

It is also stable in the face of a mutable source string: it explicitly
does not read the source buffer multiple times (so an implementation
using "strnlen()+memcpy()" would be wrong), and does not read the source
buffer past the size (like the mis-design that is strlcpy does).

Finally, the return value is designed to be simple and unambiguous: if
the string cannot be copied fully, it returns an actual negative error,
making error handling clearer and simpler (and the caller already knows
the size of the buffer).  Otherwise it returns the string length of the
result.

However, there was one final stability issue that can be important to
callers: the stability of the destination buffer.

In particular, the same way we shouldn't read the source buffer more
than once, we should avoid doing multiple writes to the destination
buffer: first writing a potentially non-terminated string, and then
terminating it with NUL at the end does not result in a stable result
buffer.

Yes, it gives the right result in the end, but if the rule for the
destination buffer was that it is _always_ NUL-terminated even when
accessed concurrently with updates, the final byte of the buffer needs
to always _stay_ as a NUL byte.

[ Note that "final byte is NUL" here is literally about the final byte
  in the destination array, not the terminating NUL at the end of the
  string itself. There is no attempt to try to make concurrent reads and
  writes give any kind of consistent string length or contents, but we
  do want to guarantee that there is always at least that final
  terminating NUL character at the end of the destination array if it
  existed before ]

This is relevant in the kernel for the tsk->comm[] array, for example.
Even without locking (for either readers or writers), we want to know
that while the buffer contents may be garbled, it is always a valid C
string and always has a NUL character at 'comm[TASK_COMM_LEN-1]' (and
never has any "out of thin air" data).

So avoid any "copy possibly non-terminated string, and terminate later"
behavior, and write the destination buffer only once.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
7 months agoprintf: Remove unused 'bprintf'
Dr. David Alan Gilbert [Wed, 2 Oct 2024 17:31:47 +0000 (18:31 +0100)]
printf: Remove unused 'bprintf'

bprintf() is unused. Remove it. It was added in the commit 4370aa4aa753
("vsprintf: add binary printf") but as far as I can see was never used,
unlike the other two functions in that patch.

Link: https://lore.kernel.org/20241002173147.210107-1-linux@treblig.org
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Acked-by: Petr Mladek <pmladek@suse.com>
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
7 months agoMerge tag 'turbostat-2024.11.30' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 1 Dec 2024 02:30:22 +0000 (18:30 -0800)]
Merge tag 'turbostat-2024.11.30' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull turbostat updates from Len Brown:

 - assorted minor bug fixes

 - assorted platform specific tweaks

 - initial RAPL PSYS (SysWatt) support

* tag 'turbostat-2024.11.30' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power turbostat: 2024.11.30
  tools/power turbostat: Add RAPL psys as a built-in counter
  tools/power turbostat: Fix child's argument forwarding
  tools/power turbostat: Force --no-perf in --dump mode
  tools/power turbostat: Add support for /sys/class/drm/card1
  tools/power turbostat: Cache graphics sysfs file descriptors during probe
  tools/power turbostat: Consolidate graphics sysfs access
  tools/power turbostat: Remove unnecessary fflush() call
  tools/power turbostat: Enhance platform divergence description
  tools/power turbostat: Add initial support for GraniteRapids-D
  tools/power turbostat: Remove PC3 support on Lunarlake
  tools/power turbostat: Rename arl_features to lnl_features
  tools/power turbostat: Add back PC8 support on Arrowlake
  tools/power turbostat: Remove PC7/PC9 support on MTL
  tools/power turbostat: Honor --show CPU, even when even when num_cpus=1
  tools/power turbostat: Fix trailing '\n' parsing
  tools/power turbostat: Allow using cpu device in perf counters on hybrid platforms
  tools/power turbostat: Fix column printing for PMT xtal_time counters
  tools/power turbostat: fix GCC9 build regression

7 months agoMerge tag 'pci-v6.13-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Linus Torvalds [Sun, 1 Dec 2024 02:23:05 +0000 (18:23 -0800)]
Merge tag 'pci-v6.13-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull PCI fix from Bjorn Helgaas:

 - When removing a PCI device, only look up and remove a platform device
   if there is an associated device node for which there could be a
   platform device, to fix a merge window regression (Brian Norris)

* tag 'pci-v6.13-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
  PCI/pwrctrl: Unregister platform device only if one actually exists

7 months agoMerge tag 'lsm-pr-20241129' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/lsm
Linus Torvalds [Sun, 1 Dec 2024 02:14:56 +0000 (18:14 -0800)]
Merge tag 'lsm-pr-20241129' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/lsm

Pull ima fix from Paul Moore:
 "One small patch to fix a function parameter / local variable naming
  snafu that went up to you in the current merge window"

* tag 'lsm-pr-20241129' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/lsm:
  ima: uncover hidden variable in ima_match_rules()

7 months agoMerge tag 'block-6.13-20242901' of git://git.kernel.dk/linux
Linus Torvalds [Sat, 30 Nov 2024 23:47:29 +0000 (15:47 -0800)]
Merge tag 'block-6.13-20242901' of git://git.kernel.dk/linux

Pull more block updates from Jens Axboe:

 - NVMe pull request via Keith:
      - Use correct srcu list traversal (Breno)
      - Scatter-gather support for metadata (Keith)
      - Fabrics shutdown race condition fix (Nilay)
      - Persistent reservations updates (Guixin)

 - Add the required bits for MD atomic write support for raid0/1/10

 - Correct return value for unknown opcode in ublk

 - Fix deadlock with zone revalidation

 - Fix for the io priority request vs bio cleanups

 - Use the correct unsigned int type for various limit helpers

 - Fix for a race in loop

 - Cleanup blk_rq_prep_clone() to prevent uninit-value warning and make
   it easier for actual humans to read

 - Fix potential UAF when iterating tags

 - A few fixes for bfq-iosched UAF issues

 - Fix for brd discard not decrementing the allocated page count

 - Various little fixes and cleanups

* tag 'block-6.13-20242901' of git://git.kernel.dk/linux: (36 commits)
  brd: decrease the number of allocated pages which discarded
  block, bfq: fix bfqq uaf in bfq_limit_depth()
  block: Don't allow an atomic write be truncated in blkdev_write_iter()
  mq-deadline: don't call req_get_ioprio from the I/O completion handler
  block: Prevent potential deadlock in blk_revalidate_disk_zones()
  block: Remove extra part pointer NULLify in blk_rq_init()
  nvme: tuning pr code by using defined structs and macros
  nvme: introduce change ptpl and iekey definition
  block: return bool from get_disk_ro and bdev_read_only
  block: remove a duplicate definition for bdev_read_only
  block: return bool from blk_rq_aligned
  block: return unsigned int from blk_lim_dma_alignment_and_pad
  block: return unsigned int from queue_dma_alignment
  block: return unsigned int from bdev_io_opt
  block: req->bio is always set in the merge code
  block: don't bother checking the data direction for merges
  block: blk-mq: fix uninit-value in blk_rq_prep_clone and refactor
  Revert "block, bfq: merge bfq_release_process_ref() into bfq_put_cooperator()"
  md/raid10: Atomic write support
  md/raid1: Atomic write support
  ...

7 months agoMerge tag 'io_uring-6.13-20242901' of git://git.kernel.dk/linux
Linus Torvalds [Sat, 30 Nov 2024 23:43:02 +0000 (15:43 -0800)]
Merge tag 'io_uring-6.13-20242901' of git://git.kernel.dk/linux

Pull more io_uring updates from Jens Axboe:

 - Remove a leftover struct from when the cqwait registered waiting was
   transitioned to regions.

 - Fix for an issue introduced in this merge window, where nop->fd might
   be used uninitialized. Ensure it's always set.

 - Add capping of the task_work run in local task_work mode, to prevent
   bursty and long chains from adding too much latency.

 - Work around xa_store() leaving ->head non-NULL if it encounters an
   allocation error during storing. Just a debug trigger, and can go
   away once xa_store() behaves in a more expected way for this
   condition. Not a major thing as it basically requires fault injection
   to trigger it.

 - Fix a few mapping corner cases

 - Fix KCSAN complaint on reading the table size post unlock. Again not
   a "real" issue, but it's easy to silence by just keeping the reading
   inside the lock that protects it.

* tag 'io_uring-6.13-20242901' of git://git.kernel.dk/linux:
  io_uring/tctx: work around xa_store() allocation error issue
  io_uring: fix corner case forgetting to vunmap
  io_uring: fix task_work cap overshooting
  io_uring: check for overflows in io_pin_pages
  io_uring/nop: ensure nop->fd is always initialized
  io_uring: limit local tw done
  io_uring: add io_local_work_pending()
  io_uring/region: return negative -E2BIG in io_create_region()
  io_uring: protect register tracing
  io_uring: remove io_uring_cqwait_reg_arg

7 months agoMerge tag 'dma-mapping-6.13-2024-11-30' of git://git.infradead.org/users/hch/dma...
Linus Torvalds [Sat, 30 Nov 2024 23:36:17 +0000 (15:36 -0800)]
Merge tag 'dma-mapping-6.13-2024-11-30' of git://git.infradead.org/users/hch/dma-mapping

Pull dma-mapping fix from Christoph Hellwig:

 - fix physical address calculation for struct dma_debug_entry (Fedor
   Pchelkin)

* tag 'dma-mapping-6.13-2024-11-30' of git://git.infradead.org/users/hch/dma-mapping:
  dma-debug: fix physical address calculation for struct dma_debug_entry

7 months agoMerge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Linus Torvalds [Sat, 30 Nov 2024 22:51:08 +0000 (14:51 -0800)]
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull more kvm updates from Paolo Bonzini:

 - ARM fixes

 - RISC-V Svade and Svadu (accessed and dirty bit) extension support for
   host and guest

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test
  RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
  dt-bindings: riscv: Add Svade and Svadu Entries
  RISC-V: Add Svade and Svadu Extensions Support
  KVM: arm64: Use MDCR_EL2.HPME to evaluate overflow of hyp counters
  KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status
  KVM: arm64: Mark set_sysreg_masks() as inline to avoid build failure
  KVM: arm64: vgic-its: Add stronger type-checking to the ITS entry sizes
  KVM: arm64: vgic: Kill VGIC_MAX_PRIVATE definition
  KVM: arm64: vgic: Make vgic_get_irq() more robust
  KVM: arm64: vgic-v3: Sanitise guest writes to GICR_INVLPIR

7 months agoMerge tag 'sh-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubi...
Linus Torvalds [Sat, 30 Nov 2024 22:45:29 +0000 (14:45 -0800)]
Merge tag 'sh-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux

Pull sh updates from John Paul Adrian Glaubitz:
 "Two small fixes.

  The first one by Huacai Chen addresses a runtime warning when
  CONFIG_CPUMASK_OFFSTACK and CONFIG_DEBUG_PER_CPU_MAPS are selected
  which occurs because the cpuinfo code on sh incorrectly uses NR_CPUS
  when iterating CPUs instead of the runtime limit nr_cpu_ids.

  A second fix by Dan Carpenter fixes a use-after-free bug in
  register_intc_controller() which occurred as a result of improper
  error handling in the interrupt controller driver code when
  registering an interrupt controller during plat_irq_setup() on sh"

* tag 'sh-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux:
  sh: intc: Fix use-after-free bug in register_intc_controller()
  sh: cpuinfo: Fix a warning for CONFIG_CPUMASK_OFFSTACK

7 months agoMerge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Linus Torvalds [Sat, 30 Nov 2024 22:33:44 +0000 (14:33 -0800)]
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:

 - Deselect ARCH_CORRECT_STACKTRACE_ON_KRETPROBE so that tests depending
   on it don't run (and fail) on arm64

 - Fix lockdep assert in the Arm SMMUv3 PMU driver

 - Fix the port and device ID bits setting in the Arm CMN perf driver

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  perf/arm-cmn: Ensure port and device id bits are set properly
  perf/arm-smmuv3: Fix lockdep assert in ->event_init()
  arm64: disable ARCH_CORRECT_STACKTRACE_ON_KRETPROBE tests

7 months agotools/power turbostat: 2024.11.30
Len Brown [Sat, 30 Nov 2024 21:22:00 +0000 (16:22 -0500)]
tools/power turbostat: 2024.11.30

since 2024.07.26:

assorted minor bug fixes
assorted platform specific tweaks
initial RAPL PSYS (SysWatt) support

Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Add RAPL psys as a built-in counter
Patryk Wlazlyn [Wed, 2 Oct 2024 13:05:15 +0000 (15:05 +0200)]
tools/power turbostat: Add RAPL psys as a built-in counter

Introduce the counter as a part of global, platform counters structure.
We open the counter for only one cpu, but otherwise treat it as an
ordinary RAPL counter, allowing for grouped perf read.

The counter is disabled by default, because it's interpretation may
require additional, platform specific information, making it unsuitable
for general use.

Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Fix child's argument forwarding
Patryk Wlazlyn [Wed, 13 Nov 2024 14:48:22 +0000 (15:48 +0100)]
tools/power turbostat: Fix child's argument forwarding

Add '+' to optstring when early scanning for --no-msr and --no-perf.
It causes option processing to stop as soon as a nonoption argument is
encountered, effectively skipping child's arguments.

Fixes: 3e4048466c39 ("tools/power turbostat: Add --no-msr option")
Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Force --no-perf in --dump mode
Patryk Wlazlyn [Thu, 24 Oct 2024 13:17:45 +0000 (15:17 +0200)]
tools/power turbostat: Force --no-perf in --dump mode

Force the --no-perf early to prevent using it as a source. User asks for
raw values, but perf returns them relative to the opening of the file
descriptor.

Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Add support for /sys/class/drm/card1
Zhang Rui [Thu, 14 Nov 2024 07:59:46 +0000 (15:59 +0800)]
tools/power turbostat: Add support for /sys/class/drm/card1

On some machines, the graphics device is enumerated as
/sys/class/drm/card1 instead of /sys/class/drm/card0. The current
implementation does not handle this scenario, resulting in the loss of
graphics C6 residency and frequency information.

Add support for /sys/class/drm/card1, ensuring that turbostat can
retrieve and display the graphics columns for these platforms.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Cache graphics sysfs file descriptors during probe
Zhang Rui [Thu, 14 Nov 2024 07:59:45 +0000 (15:59 +0800)]
tools/power turbostat: Cache graphics sysfs file descriptors during probe

Snapshots of the graphics sysfs knobs are taken based on file
descriptors. To optimize this process, open the files and cache the file
descriptors during the graphics probe phase. As a result, the previously
cached pathnames become redundant and are removed.

This change aims to streamline the code without altering its functionality.

No functional change intended.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Consolidate graphics sysfs access
Zhang Rui [Thu, 14 Nov 2024 07:59:44 +0000 (15:59 +0800)]
tools/power turbostat: Consolidate graphics sysfs access

Currently, there is an inconsistency in how graphics sysfs knobs are
accessed: graphics residency sysfs knobs are opened and closed for each
read, while graphics frequency sysfs knobs are opened once and remain
open until turbostat exits. This inconsistency is confusing and adds
unnecessary code complexity.

Consolidate the access method by opening the sysfs files once and
reusing the file pointers for subsequent accesses. This approach
simplifies the code and ensures a consistent method for accessing
graphics sysfs knobs.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Remove unnecessary fflush() call
Zhang Rui [Thu, 14 Nov 2024 07:59:43 +0000 (15:59 +0800)]
tools/power turbostat: Remove unnecessary fflush() call

The graphics sysfs knobs are read-only, making the use of fflush()
before reading them redundant.

Remove the unnecessary fflush() call.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Enhance platform divergence description
Zhang Rui [Thu, 14 Nov 2024 07:59:42 +0000 (15:59 +0800)]
tools/power turbostat: Enhance platform divergence description

In various generations, platforms often share a majority of features,
diverging only in a few specific aspects. The current approach of using
hardcoded values in 'platform_features' structure fails to effectively
represent these divergences.

To improve the description of platform divergence:
1. Each newly introduced 'platform_features' structure must have a base,
   typically derived from the previous generation.
2. Platform feature values should be inherited from the base structure
   rather than being hardcoded.
This approach ensures a more accurate and maintainable representation of
platform-specific features across different generations.

Converts `adl_features` and `lnl_features` to follow this new scheme.

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Add initial support for GraniteRapids-D
Zhang Rui [Thu, 14 Nov 2024 07:59:41 +0000 (15:59 +0800)]
tools/power turbostat: Add initial support for GraniteRapids-D

Add initial support for GraniteRapids-D. It shares the same features
with SapphireRapids.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Remove PC3 support on Lunarlake
Zhang Rui [Thu, 14 Nov 2024 07:59:40 +0000 (15:59 +0800)]
tools/power turbostat: Remove PC3 support on Lunarlake

Lunarlake supports CC1/CC6/CC7/PC2/PC6/PC10.

Remove PC3 support on Lunarlake.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Rename arl_features to lnl_features
Zhang Rui [Thu, 14 Nov 2024 07:59:39 +0000 (15:59 +0800)]
tools/power turbostat: Rename arl_features to lnl_features

As ARL shares the same features with ADL/RPL/MTL, now 'arl_features' is
used by Lunarlake platform only.

Rename 'arl_features' to 'lnl_features'.

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Add back PC8 support on Arrowlake
Zhang Rui [Thu, 14 Nov 2024 07:59:38 +0000 (15:59 +0800)]
tools/power turbostat: Add back PC8 support on Arrowlake

Similar to ADL/RPL/MTL, ARL supports CC1/CC6/CC7/PC2/PC3/PC6/PC8/PC10.

Add back PC8 support on Arrowlake.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Remove PC7/PC9 support on MTL
Zhang Rui [Thu, 14 Nov 2024 07:59:37 +0000 (15:59 +0800)]
tools/power turbostat: Remove PC7/PC9 support on MTL

Similar to ADL/RPL, MTL support CC1/CC6/CC7/PC2/PC3/PC6/PC8/CP10.

Remove PC7/PC9 support on MTL.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Honor --show CPU, even when even when num_cpus=1
Patryk Wlazlyn [Tue, 17 Sep 2024 20:33:26 +0000 (22:33 +0200)]
tools/power turbostat: Honor --show CPU, even when even when num_cpus=1

Honor --show CPU and --show Core when "topo.num_cpus == 1".
Previously turbostat assumed that on a 1-CPU system, these
columns should never appear.

Honoring these flags makes it easier for several programs
that parse turbostat output.

Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Fix trailing '\n' parsing
Zhang Rui [Tue, 27 Aug 2024 05:07:51 +0000 (13:07 +0800)]
tools/power turbostat: Fix trailing '\n' parsing

parse_cpu_string() parses the string input either from command line or
from /sys/fs/cgroup/cpuset.cpus.effective to get a list of CPUs that
turbostat can run with.

The cpu string returned by /sys/fs/cgroup/cpuset.cpus.effective contains
a trailing '\n', but strtoul() fails to treat this as an error.

That says, for the code below
val = ("\n", NULL, 10);
val returns 0, and errno is also not set.

As a result, CPU0 is erroneously considered as allowed CPU and this
causes failures when turbostat tries to run on CPU0.

 get_counters: Could not migrate to CPU 0
 ...
 turbostat: re-initialized with num_cpus 8, allowed_cpus 5
 get_counters: Could not migrate to CPU 0

Add a check to return immediately if '\n' or '\0' is detected.

Fixes: 8c3dd2c9e542 ("tools/power/turbostat: Abstrct function for parsing cpu string")
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Allow using cpu device in perf counters on hybrid platforms
Patryk Wlazlyn [Tue, 20 Aug 2024 16:47:59 +0000 (18:47 +0200)]
tools/power turbostat: Allow using cpu device in perf counters on hybrid platforms

Intel hybrid platforms expose different perf devices for P and E cores.
Instead of one, "/sys/bus/event_source/devices/cpu" device, there are
"/sys/bus/event_source/devices/{cpu_core,cpu_atom}".

This, however makes it more complicated for the user,
because most of the counters are available on both and had to be
handled manually.

This patch allows users to use "virtual" cpu device that is seemingly
translated to cpu_core and cpu_atom perf devices, depending on the type
of a CPU we are opening the counter for.

Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: Fix column printing for PMT xtal_time counters
Patryk Wlazlyn [Wed, 7 Aug 2024 11:43:39 +0000 (13:43 +0200)]
tools/power turbostat: Fix column printing for PMT xtal_time counters

If the very first printed column was for a PMT counter of type xtal_time
we would misalign the column header, because we were always printing the
delimiter.

Signed-off-by: Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agotools/power turbostat: fix GCC9 build regression
Todd Brandt [Wed, 31 Jul 2024 16:24:09 +0000 (12:24 -0400)]
tools/power turbostat: fix GCC9 build regression

Fix build regression seen when using old gcc-9 compiler.

Signed-off-by: Todd Brandt <todd.e.brandt@intel.com>
Reviewed-by: Chen Yu <yu.c.chen@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
7 months agoMerge tag 'kbuild-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy...
Linus Torvalds [Sat, 30 Nov 2024 21:41:50 +0000 (13:41 -0800)]
Merge tag 'kbuild-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild

Pull Kbuild updates from Masahiro Yamada:

 - Add generic support for built-in boot DTB files

 - Enable TAB cycling for dialog buttons in nconfig

 - Fix issues in streamline_config.pl

 - Refactor Kconfig

 - Add support for Clang's AutoFDO (Automatic Feedback-Directed
   Optimization)

 - Add support for Clang's Propeller, a profile-guided optimization.

 - Change the working directory to the external module directory for M=
   builds

 - Support building external modules in a separate output directory

 - Enable objtool for *.mod.o and additional kernel objects

 - Use lz4 instead of deprecated lz4c

 - Work around a performance issue with "git describe"

 - Refactor modpost

* tag 'kbuild-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (85 commits)
  kbuild: rename .tmp_vmlinux.kallsyms0.syms to .tmp_vmlinux0.syms
  gitignore: Don't ignore 'tags' directory
  kbuild: add dependency from vmlinux to resolve_btfids
  modpost: replace tdb_hash() with hash_str()
  kbuild: deb-pkg: add python3:native to build dependency
  genksyms: reduce indentation in export_symbol()
  modpost: improve error messages in device_id_check()
  modpost: rename alias symbol for MODULE_DEVICE_TABLE()
  modpost: rename variables in handle_moddevtable()
  modpost: move strstarts() to modpost.h
  modpost: convert do_usb_table() to a generic handler
  modpost: convert do_of_table() to a generic handler
  modpost: convert do_pnp_device_entry() to a generic handler
  modpost: convert do_pnp_card_entries() to a generic handler
  modpost: call module_alias_printf() from all do_*_entry() functions
  modpost: pass (struct module *) to do_*_entry() functions
  modpost: remove DEF_FIELD_ADDR_VAR() macro
  modpost: deduplicate MODULE_ALIAS() for all drivers
  modpost: introduce module_alias_printf() helper
  modpost: remove unnecessary check in do_acpi_entry()
  ...

7 months agoMerge tag 'rtc-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Linus Torvalds [Sat, 30 Nov 2024 19:18:16 +0000 (11:18 -0800)]
Merge tag 'rtc-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

Pull RTC updates from Alexandre Belloni:
 "New drivers:
   - Amlogic A4 and A5 RTC
   - Marvell 88PM886 PMIC RTC
   - Renesas RTCA-3 for Renesas RZ/G3S

  Driver updates:
   - ab-eoz9: fix temperature and alarm support
   - cmos: improve locking behaviour
   - isl12022: add alarm support
   - m48t59: improve epoch handling
   - mt6359: add range
   - rzn1: fix BCD conversions and simplify driver"

* tag 'rtc-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (38 commits)
  rtc: ab-eoz9: don't fail temperature reads on undervoltage notification
  rtc: rzn1: reduce register access
  rtc: rzn1: drop superfluous wday calculation
  m68k: mvme147, mvme16x: Adopt rtc-m48t59 platform driver
  rtc: brcmstb-waketimer: don't include 'pm_wakeup.h' directly
  rtc: m48t59: Use platform_data struct for year offset value
  rtc: ab-eoz9: fix abeoz9_rtc_read_alarm
  rtc: rv3028: fix RV3028_TS_COUNT type
  rtc: rzn1: update Michel's email
  rtc: rzn1: fix BCD to rtc_time conversion errors
  rtc: amlogic-a4: fix compile error
  rtc: amlogic-a4: drop error messages
  MAINTAINERS: Add an entry for Amlogic RTC driver
  rtc: support for the Amlogic on-chip RTC
  dt-bindings: rtc: Add Amlogic A4 and A5 RTC
  rtc: add driver for Marvell 88PM886 PMIC RTC
  rtc: check if __rtc_read_time was successful in rtc_timer_do_work()
  rtc: pcf8563: Switch to regmap
  rtc: pcf8563: Sort headers alphabetically
  rtc: abx80x: Fix WDT bit position of the status register
  ...