Nícolas F. R. A. Prado [Wed, 2 Nov 2022 18:20:02 +0000 (14:20 -0400)]
arm64: dts: qcom: sc7180-trogdor: Remove VBAT supply from rt5682s
These devicetrees override a rt5682 node to use the rt5682s compatible,
however, unlike rt5682, rt5682s doesn't have a VBAT supply. Remove the
inexistent supply in the rt5682s nodes.
There are three UFS reference clocks on SC8280XP which are used as
follows:
- The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
to either controller.
- The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
provide reference clocks to the two PHYs.
Note that this depends on first updating the clock driver to reflect
that all three clocks are sourced from CXO. Specifically, the UFS
controller driver expects the device reference clock to have a valid
frequency:
The devices on the SC8280XP PCIe buses are cache coherent and must be
marked as such to avoid data corruption.
A coherent device can, for example, end up snooping stale data from the
caches instead of using data written by the CPU through the
non-cacheable mapping which is used for consistent DMA buffers for
non-coherent devices.
Note that this is much more likely to happen since commit c44094eee32f
("arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()")
that was added in 6.1 and which removed the cache invalidation when
setting up the non-cacheable mapping.
Marking the PCIe devices as coherent specifically fixes the intermittent
NVMe probe failures observed on the Thinkpad X13s, which was due to
corruption of the submission and completion queues. This was typically
observed as corruption of the admin submission queue (with well-formed
completion):
could not locate request for tag 0x0
nvme nvme0: invalid id 0 completed on queue 0
or corruption of the admin or I/O completion queues (malformed
completion):
could not locate request for tag 0x45f
nvme nvme0: invalid id 25695 completed on queue 25965
presumably as these queues are small enough to not be allocated using
CMA which in turn make them more likely to be cached (e.g. due to
accesses to nearby pages through the cacheable linear map). Increasing
the buffer sizes to two pages to force CMA allocation also appears to
make the problem go away.
Konrad Dybcio [Mon, 14 Nov 2022 14:36:41 +0000 (15:36 +0100)]
arm64: dts: qcom: sm8350-sagami: Add most RPMh regulators
Configure most RPMh-controlled regulators on SoMC Sagami. The missing
ones (on pm8350b and pm8008[ij]) will be configured when driver support
is added. Thankfully, it looks like PDX215 and PDX214 don't have any
differences when it comes to PM8350/PM8350C/PMR735a.
Douglas Anderson [Tue, 15 Nov 2022 00:28:28 +0000 (16:28 -0800)]
arm64: dts: qcom: sc7280: Make herobrine-audio-rt5682 mic dtsi's match more
The 1-mic and 3-mic dtsi still had two minor cosmetic differences
after commit '3d11e7e120ee ("arm64: dts: qcom: sc7280: sort out the
"Status" to last property with
sc7280-herobrine-audio-rt5682.dtsi")'. Let's fix them so the two files
diff better. This is expected to have no effect though it will
slightly change the generated dtb by removing an unnecessary 'status =
"okay"' from the sound node.
Sibi Sankar [Thu, 10 Nov 2022 07:08:13 +0000 (12:38 +0530)]
arm64: dts: qcom: sc7280: Add Google Herobrine WIFI SKU dts fragment
The Google Herobrine WIFI SKU can save 256M by not having modem/mba/rmtfs
memory regions defined. Add the dts fragment and mark all the board files
appropriately.
Sibi Sankar [Thu, 10 Nov 2022 07:08:12 +0000 (12:38 +0530)]
arm64: dts: qcom: sc7280: Mark all Qualcomm reference boards as LTE
When the modem node was re-located to a separate LTE source file
"sc7280-herobrine-lte-sku.dtsi", some of the previous LTE users
weren't marked appropriately. Fix this by marking all Qualcomm
reference devices as LTE.
Suggested-by: Douglas Anderson <dianders@chromium.org> Fixes: d42fae738f3a ("arm64: dts: qcom: Add LTE SKUs for sc7280-villager family") Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221110070813.1777-1-quic_sibis@quicinc.com
Fairphone 4 uses sdhc_2 for the SD card, configure the pins for it and
enable it.
The regulators which are exclusively used for SDHCI have their maximum
voltage decreased to what downstream sets on the consumer side, like on
many other platforms and allowed to set the load.
Remove redundant and undocumented property qcom,port-offset in
soundwire controller nodes.
This patch is required to avoid dtbs_check errors with
qcom,soundwire.yaml
Fixes: 12ef689f09ab ("arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro codecs") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Signed-off-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1667918763-32445-4-git-send-email-quic_srivasam@quicinc.com
Remove redundant and undocumented property qcom,port-offset in
soundwire controller nodes.
This patch is required to avoid dtbs_check errors with
qcom,soundwire.yaml
Fixes: 24f52ef0c4bf ("arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Signed-off-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1667918763-32445-3-git-send-email-quic_srivasam@quicinc.com
In "sc7280-idp.dts", the IPA node is modified after being defined.
However that file includes "sc7280-idp.dtsi", which also modifies
the IPA node (in the same way). This only needs to be done in
"sc7280-idp.dtsi".
Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221108201625.1220919-1-elder@linaro.org
Konrad Dybcio [Mon, 7 Nov 2022 12:09:19 +0000 (13:09 +0100)]
arm64: dts: qcom: Add device tree for Sony Xperia 10 IV
Add support for Sony Xperia 10 IV, a.k.a PDX225. This device is a part
of the SoMC SM6375 Murray platform and currently it is the only
device based on that board, so no -common DTSI is created until (if?)
other Murray devices appear.
This commit brings support for:
* USB (only USB2 for now)
* Display via simplefb
To create a working boot image, you need to run:
cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm6375-sony-xperia-\
murray-pdx225.dtb > .Image.gz-dtb
Then, you need to flash it on the device and get rid of all the
vendor_boot/dtbo mess:
First, you need to get rid of vendor_boot. However, the bootloader
is utterly retarded and it will not let you neither flash nor erase it.
There are a couple ways to handle this: you can either dd /dev/zero to
it from Android (if you have root) or a custom recovery or from fastbootd
(fastboot/adb reboot fastboot). You will not be able to boot Android
images on your phone unless you lock the bootloader (fastboot oem lock)
and restore the factory image with Xperia Companion
Windows-and-macOS-only software.
The best way so far is probably to use the second (_b) slot and flash
mainline there. This will however require you to flash some partitions
manually, as they are not populated from factory:
(boot_b, dtbo_b, vendor_boot_b, vbmeta_b, vbmeta_system_b) - these we
don't really care about as we nuke/replace them
(dsp_b, imagefv_b, modem_b, oem_b, rdimage_b) - these you NEED to populate
to get a successful boot on slot B, otherwise you will have limited / no
functionality.
To switch slots, simply run:
fastboot --set-active=a //or =b
The rest assumes you are on slot A.
// You have to either pull vbmeta{"","_system"} from
// /dev/block/bootdevice/by-name/ or build one as a part of AOSP
fastboot --disable-verity --disable-verification flash vbmeta_b vbmeta.img
fastboot --disable-verity --disable-verification flash vbmeta_system_b \
vbmeta_system.img
Where emptything.img is a tiny file that consists of 2 bytes (all zeroes),
doing a "fastboot erase" won't cut it, the bootloader will go crazy and
things will fall apart when it tries to overlay random bytes from an empty
partition onto a perfectly good appended DTB.
From there on you can flash new mainline builds by simply flashing
boot.img that you create after each kernel rebuild.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107120920.12593-4-konrad.dybcio@linaro.org
Stephen Boyd [Mon, 7 Nov 2022 19:15:35 +0000 (11:15 -0800)]
arm64: dts: qcom: sc7180: Fully describe fingerprint node on Trogdor
Update the fingerprint node on Trogdor to match the fingerprint DT
binding. This will allow us to drive the reset and boot gpios from the
driver when it is re-attached after flashing. We'll also be able to boot
the fingerprint processor if the BIOS isn't doing it for us.
Cc: Douglas Anderson <dianders@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107191535.624371-3-swboyd@chromium.org
Stephen Boyd [Mon, 7 Nov 2022 19:15:34 +0000 (11:15 -0800)]
arm64: dts: qcom: sc7280: Fully describe fingerprint node on Herobrine
Update the fingerprint node on Herobrine to match the fingerprint DT
binding. This will allow us to drive the reset and boot gpios from the
driver when it is re-attached after flashing. We'll also be able to boot
the fingerprint processor if the BIOS isn't doing it for us.
Cc: Douglas Anderson <dianders@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107191535.624371-2-swboyd@chromium.org
Konrad Dybcio [Mon, 7 Nov 2022 14:55:12 +0000 (15:55 +0100)]
arm64: dts: qcom: msm/apq8x96-*: Fix up comments
Switch '//' comments to C-style /* */ and fix up the contents of some.
Make sure all multiline C-style commends begin with just '/*' with
the comment text starting on a new line.
Also, fix up a single raw '2' to PM8994_GPIO_S4 while at it.
Konrad Dybcio [Mon, 7 Nov 2022 14:55:11 +0000 (15:55 +0100)]
arm64: dts: qcom: msm/apq8x16-*: Fix up comments
Switch '//' comments to C-style /* */ and fix up the contents of some.
Make sure all multiline C-style commends begin with just '/*' with
the comment text starting on a new line.
Robert Marko [Mon, 7 Nov 2022 09:29:30 +0000 (10:29 +0100)]
arm64: dts: qcom: hk01: use GPIO flags for tlmm
Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
harcoding the cell value.
Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
Robert Marko [Mon, 7 Nov 2022 09:29:29 +0000 (10:29 +0100)]
arm64: dts: qcom: hk10: use GPIO flags for tlmm
Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
harcoding the cell value.
Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107092930.33325-2-robimarko@gmail.com
Robert Marko [Mon, 7 Nov 2022 09:29:28 +0000 (10:29 +0100)]
arm64: dts: qcom: hk10: use "okay" instead of "ok"
Use "okay" instead of "ok" in USB nodes as "ok" is deprecated.
Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107092930.33325-1-robimarko@gmail.com
Sheng-Liang Pan [Mon, 7 Nov 2022 09:43:44 +0000 (17:43 +0800)]
arm64: dts: qcom: sc7280: add sc7280-herobrine-audio-rt5682-3mic3.dtsi for evoker
add specific 3mic setting as sc7280-herobrine-audio-rt5682-3mic.dtsi,
so we can include sc7280-herobrine-audio-rt5682-3mic.dtsi for evoker
as it uses rt5682 with 3 mics.
Marijn Suijten [Sun, 30 Oct 2022 07:32:32 +0000 (08:32 +0100)]
arm64: dts: qcom: sm6350: Add apps_smmu with streamID to SDHCI 1/2 nodes
When enabling the APPS SMMU the mainline driver reconfigures the SMMU
from its bootloader configuration, losing the stream mapping for (among
which) the SDHCI hardware and breaking its ADMA feature. This feature
can be disabled with:
sdhci.debug_quirks=0x40
But it is of course desired to have this feature enabled and working
through the SMMU.
Marijn Suijten [Sun, 30 Oct 2022 07:32:29 +0000 (08:32 +0100)]
arm64: dts: qcom: sm6350-lena: Provide power to SDHCI 2 (SDCard slot)
Without power the SDCard slot / hardware remains dormant.
Like many other platforms these regulators are used exclusively by
SDHCI, and have their maximum voltage decreased to what downstream sets
on the consumer side. Additionally the SDHCI driver supports setting a
load, for which the regulator definition is extended much the same.
Luca Weiss [Fri, 28 Oct 2022 07:54:05 +0000 (09:54 +0200)]
arm64: dts: qcom: pm6150l: add temp sensor and thermal zone config
Add temp-alarm device tree node and a default configuration for the
corresponding thermal zone for this PMIC. Temperatures are based on
downstream values, except for trip2 where 125°C is used instead of 145°C
due to limitations without a configured ADC.
Luca Weiss [Fri, 28 Oct 2022 07:54:04 +0000 (09:54 +0200)]
arm64: dts: qcom: pm6350: add temp sensor and thermal zone config
Add temp-alarm device tree node and a default configuration for the
corresponding thermal zone for this PMIC. Temperatures are based on
downstream values, except for trip2 where 125°C is used instead of 145°C
due to limitations without a configured ADC.
Douglas Anderson [Tue, 25 Oct 2022 23:52:39 +0000 (16:52 -0700)]
arm64: dts: qcom: sc7280: Villager doesn't have NVME
The sc7280-herobrine-villager derivative doesn't have NVME enabled so
we shouldn't mark the PCIe nodes as "okay" since they're just for
boards that have NVME.
Stephen Boyd [Tue, 25 Oct 2022 18:07:03 +0000 (11:07 -0700)]
arm64: dts: qcom: Remove fingerprint node from herobrine-r1
It turns out that only a few people have the fingerprint sensor hooked
up on their board. Leaving this enabled is slowing down boot for
everyone else because the driver slowly fails to probe while trying to
communicate with a sensor that isn't there. Remove the node to speed up
boot, developers with the board can manually enable it themselves.
Reported-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221025180703.1806234-1-swboyd@chromium.org
Krzysztof Kozlowski [Tue, 18 Oct 2022 15:54:48 +0000 (11:54 -0400)]
arm64: dts: qcom: msm8994: Correct SPI10 CS pin
The GPIO55 is part of SPI10 pins, not its chip-select. Probably the
intention was to use one of dedicated chip-select GPIOs: 47 or 67.
GPIO47 is used for UART2, so choose GPIO67.
Manivannan Sadhasivam [Thu, 3 Nov 2022 09:58:10 +0000 (15:28 +0530)]
arm64: dts: qcom: sc8280xp-x13s: Add thermal zone support
Add thermal zone support by making use of the thermistor SYS_THERM6.
Based on experiments, this thermistor seems to reflect the actual
surface temperature of the laptop.
For the cooling device, all BIG CPU cores are throttled down to keep the
temperature at a sane level.
Add ADC_TM5 channels of PM8280_{1/2} for monitoring the temperature from
external thermistors connected to AMUX pins. The temperature measurements
are collected from the PMK8280's VADC channels that expose the
measurements from secondary PMICs PM8280_{1/2}.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221103095810.64606-12-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Thu, 3 Nov 2022 09:58:01 +0000 (15:28 +0530)]
arm64: dts: qcom: sc8280xp-pmics: Add thermal zones for PM8280_{1/2} PMICs
Add thermal zones for the PM8280_{1/2} PMICs by using the temperature
alarm blocks as the thermal sensors. Temperature trip points are
inherited from PM8350 PMIC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221103095810.64606-4-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Thu, 3 Nov 2022 09:57:59 +0000 (15:27 +0530)]
dt-bindings: iio: qcom: adc7-pm8350: Allow specifying SID for channels
As per the new ADC7 architecture used by the Qualcomm PMICs, each PMIC
has the static Slave ID (SID) assigned by default. The primary PMIC
PMK8350 is responsible for collecting the temperature/voltage data from
the slave PMICs and exposing them via it's registers.
For getting the measurements from the slave PMICs, PMK8350 uses the
channel ID encoded with the SID of the relevant PMIC. So far, the
dt-binding for the slave PMIC PM8350 assumed that there will be only
one PM8350 in a system. So it harcoded SID 1 with channel IDs.
But this got changed in platforms such as Lenovo X13s where there are a
couple of PM8350 PMICs available. So to address multiple PM8350s, change
the binding to accept the SID specified by the user and use it for
encoding the channel ID.
It should be noted that, even though the SID is static it is not
globally unique. Only the primary PMIC has the unique SID id 0.
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