Daniel Vetter [Mon, 3 Apr 2023 07:20:51 +0000 (09:20 +0200)]
Merge tag 'drm-misc-next-2023-03-31' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v6.4-rc1:
Cross-subsystem Changes:
- DT bindings update for adding Mali MT81xx devices.
- Assorted DT binding updates.
Core Changes:
- Documentation update to scheduler.
Driver Changes:
- Add support for the same mali devices.
- Add support for speed binning to panfrost.
- Add B133UAN01.0 eDP panel.
- Assorted small fixes to bridge/ps8640, bridge/it6505, panel/magnachip.
- Use of_property_read_bool in ps8622 and ofdrm.
Caio Novais [Wed, 29 Mar 2023 18:05:34 +0000 (15:05 -0300)]
drm/amd/display: Mark function 'optc3_wait_drr_doublebuffer_pending_clear' as static
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’ [-Wmissing-prototypes]
Get rid of it by marking the function as static
Signed-off-by: Caio Novais <caionovais@usp.br> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Amber Lin [Mon, 6 Dec 2021 09:22:42 +0000 (17:22 +0800)]
drm/amdkfd: Set TG_CHUNK_SIZE for GC 9.4.3
On GC 9.4.3, DW 41 in MQD is repurposed as compute_tg_chunk_size
for cooperative dispatch. When it's a AQL queue, set compute_tg_chunk_size
as 1 to spread work groups evenly among XCCs. If it's PM4 queue, unset
compute_tg_chunk_size to disable cooperative mode.
v3: set compute_tg_chunk_size as 1 instead of #CUs per XCC
v2: set compute_tg_chunk_size as #CUs per XCC instead of total wave
slots per XCC
Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Sean Keely <Sean.Keely@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sat, 23 Jul 2022 09:29:43 +0000 (17:29 +0800)]
drm/amdkfd: Trap handler changes for GC 9.4.3 v2
v1:
Check new exception bits in TRAPSTS register
Remove single step exception workaround, now part of
exception bits
v2:
GC 9.4.3 uses ttmp11 to store {1’b0, dispatch index [24:0],
wave_id_in_workgroup[5:0]}, so use ttmp13 instead of ttmp11 to
preserve ib_sts. (Laurent)
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Laurent Morichetti <Laurent.Morichetti@amd.com> Reviewed-by: Laurent Morichetti <laurent.morichetti@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c: In function ‘dml_rq_dlg_get_dlg_params’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14: warning: variable ‘scl_enable’ set but not used [-Wunused-but-set-variable]
Get rid of it by removing the variable 'scl_enable'.
Signed-off-by: Caio Novais <caionovais@usp.br> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Amber Lin [Wed, 9 Jun 2021 16:36:35 +0000 (12:36 -0400)]
drm/amdkfd: Set noretry/xnack for GC 9.4.3
For GC 9.4.3, disable retry as default and XNACK can be different
modes per process.
Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 18 Mar 2023 15:17:16 +0000 (11:17 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.160.0
- New parameter to define extra vblank stretch required when
doing FPO + Vactive
- Pass in pipe index for FPO
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peichen Huang [Mon, 20 Mar 2023 01:34:23 +0000 (09:34 +0800)]
drm/amd/display: skip CLEAR_PAYLOAD_ID_TABLE if device mst_en is 0
[Why]
Some dock and mst monitor don't like to receive CLEAR_PAYLOAD_ID_TABLE
when mst_en is set to 0. It doesn't make sense to do so in source
side, either.
[How]
Don't send CLEAR_PAYLOAD_ID_TABLE if mst_en is 0
Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 17 Mar 2023 19:18:03 +0000 (15:18 -0400)]
drm/amd/display: Enable FPO optimization
[Description]
Enable optimization for preferring FPO if it achieves
a lower voltage level
Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 17 Mar 2023 18:08:55 +0000 (14:08 -0400)]
drm/amd/display: Only keep cursor p-state force for FPO
[Description]
If transitioning from an FPO config -> FPO config, we want
to keep cursor P-State force disallowed. Any other transition
from FPO config -> non FPO config should unforce the cursor
P-State disallow
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Artem Grishin [Wed, 15 Mar 2023 22:17:59 +0000 (18:17 -0400)]
drm/amd/display: Conditionally enable 6.75 GBps link rate
[Why]
The 6.75 GBps link rate is part of the new eDP specification
version 1.5 is going to be supported in the future.
Since this standard is very new and there are no existing 6.75 GBps
panels on the market yet, we should put a condition in the driver
on enabling this feature until we can validate it with real hardware.
[How]
- Add boolean flag support_eDP1_5 in struct dc_debug_options.
- Enable the 6.75 link rate in reduce_link_rate(...) only when
the flag is true.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Artem Grishin <Artem.Grishin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ayush Gupta [Thu, 16 Mar 2023 19:57:30 +0000 (15:57 -0400)]
drm/amd/display: fixed dcn30+ underflow issue
[Why]
Observing underflow on dcn30+ system config at 4k144hz
[How]
We set the UCLK hardmax on AC/DC switch if softmax is enabled
and also on boot. While booting up the UCLK Hardmax is set
to softmax before the init sequence and the init sequence
resets the hardmax to UCLK max which enables P-state switching.
Just added a conditional check to avoid setting hardmax on init.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Ayush Gupta <ayugupta@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Wed, 15 Mar 2023 21:40:49 +0000 (17:40 -0400)]
drm/amd/display: Use per pipe P-State force for FPO
[Description]
* Pass in pipe index for FPO cmd to DMCUB
- This change will pass in the pipe index for each stream
that is using FPO
- This change is in preparation to enable FPO + VActive
* Use per pipe P-State force for FPO
- For FPO, instead of using max watermarks value for P-State disallow,
use per pipe p-state force instead
- This is in preparation to enable FPO + VActive
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Sat, 11 Mar 2023 02:18:06 +0000 (21:18 -0500)]
drm/amd/display: update dig enable sequence
[why]
HW delta follow up
Reviewed-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Tue, 14 Mar 2023 13:27:20 +0000 (09:27 -0400)]
drm/amd/display: fix double memory allocation
[Why & How]
when trying to fix a nullptr dereference on VMs,
accidentally doubly allocated memory for the non VM
case. removed the extra link_srv creation since
dc_construct_ctx is called in both VM and non VM cases
Also added a proper fail check for if kzalloc fails
Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Leo Ma <Hanghong.Ma@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Martin Leung <Martin.Leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Mon, 13 Mar 2023 17:23:45 +0000 (13:23 -0400)]
drm/amd/display: Fix 4to1 MPC black screen with DPP RCO
[Why]
DPP Root clock optimization when combined with 4to1 MPC combine results
in the screen turning black.
This is because the DPPCLK is stopped during the middle of an
optimize_bandwidth sequence during commit_minimal_transition without
going through plane power down/power up.
[How]
The intent of a 0Hz DPP clock through update_clocks is to disable the
DTO. This differs from the behavior of stopping the DPPCLK entirely
(utilizing a 0Hz clock on some ASIC) so it's better to move this logic
to reside next to plane power up/power down where we gate the HUBP/DPP
DOMAIN.
The new sequence should be:
Power down: PG enabled -> RCO on
Power up: RCO off -> PG disabled
Rename power_on_plane to power_on_plane_resources to reflect the
actual operation that's occurring.
Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 13 Mar 2023 22:06:34 +0000 (18:06 -0400)]
drm/amd/display: Update FCLK change latency
[Descrtipion]
- Driver hardcoded FCLK P-State latency was incorrect
- Use the value provided by PMFW header instead
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 13 Mar 2023 16:54:49 +0000 (12:54 -0400)]
drm/amd/display: Enable FPO for configs that could reduce vlevel
[Description]
- On high refresh rate DRR displays that support VBLANK naturally,
UCLK could be idling at DPM1 instead of DPM0 since it doesn't use
FPO
- To achieve DPM0, enable FPO on these configs even though it can
support P-State without FPO
- Default disable for now, have debug option to enable
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Sat, 11 Mar 2023 14:11:29 +0000 (09:11 -0500)]
drm/amd/display: Add NULL plane_state check for cursor disable logic
[Why]
While scanning the top_pipe connections we can run into a case where
the bottom pipe is still connected to a top_pipe but with a NULL
plane_state.
[How]
Treat a NULL plane_state the same as the plane being invisible for
pipe cursor disable logic.
Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Srinivasan Shanmugam [Mon, 27 Mar 2023 17:58:47 +0000 (23:28 +0530)]
drm/amd/amdgpu: Remove initialisation of globals to 0 or NULL
Global variables do not need to be initialized to 0 or NULL and checkpatch
flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:
ERROR: do not initialise globals to NULL
+char *amdgpu_disable_cu = NULL;
+char *amdgpu_virtual_display = NULL;
Fix this checkpatch error.
Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:38 +0000 (10:37 +0100)]
drm/radeon: Only build fbdev if DRM_FBDEV_EMULATION is set
Make building fbdev emulation depend on DRM_FBDEV_EMULATION. Also
rename the source file to radeon_fbdev.c to align with other fbdev
files.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Implement fbdev emulation on top of struct drm_client and its helpers.
Replaces ad-hoc interfaces for restoring and closing fbdev emulation with
per-client callbacks for hotplugging, restoring and unregistering.
A single function, radeon_fbdev_setup(), starts fbdev emulation after
the DRM device has been registered. Hence, fbdev acts like a regular
DRM client.
The setup call prepares the fbdev emulation and invokes connector
hotplugging. The first successful hotplug event initializes fbdev
emulation with a framebuffer, device file, etc.
Unregistering depends on the hotplug status. Fully initialized emulation
is cleaned up through drm_fb_helper_unregister_info() and fb_destroy.
For prepared-only setups, unregistering unprepares the emulation and
releases all resources. In both cases, fbdev emulation will be cleaned
up.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:36 +0000 (10:37 +0100)]
drm/radeon: Correctly clean up failed display probing
Improve the fbdev probing function to fully clean up if it failed.
Allows to remove special cases from fb_destroy as well.
This change is reorders the operations within radeonfb_probe(). It
first allocates a buffer object, then builds a DRM framebuffer for
the object and finally creates the fbdev device. If every step
succeeded, the probe function clears the framebuffer memory. This
is the optimal order to rollback any changes if any of the steps
fails.
No functional changes.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:35 +0000 (10:37 +0100)]
drm/radeon: Move fbdev cleanup code into fb_destroy callback
Fbdev calls struct fb_ops.fb_destroy after cleaning up the final
reference to an fbdev framebuffer. Move radeon's fbdev cleanup code
there.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:34 +0000 (10:37 +0100)]
drm/radeon: Fix coding style in fbdev emulation
Fix the coding style in several places in the fbdev-emulation
code. Also rename functions and structure file by comments. No
functional changes.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:33 +0000 (10:37 +0100)]
drm/radeon: Move fbdev object helpers before struct fb_ops et al
Move the helpers for creating and destroying fbdev GEM objects
to the top of the source file. Makes them available to fb_ops
functions. This will allow to implement framebuffer cleanup in
fb_destroy. No functional changes.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:32 +0000 (10:37 +0100)]
drm/radeon: Remove test for !screen_base in fbdev probing
The screen_base field comes from the fbdev BO and contains the fbdev
framebuffer base address. We get the BO memory via radeon_bo_kmap(),
which already reports the error -ENOMEM if the buffer could not be
mapped. So remove the later test for screen_base, which will never
be NULL at this point.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:31 +0000 (10:37 +0100)]
drm/radeon: Remove struct radeon_fbdev
Both data fields in struct radeon_fbdev, the framebuffer and the
device, are already available in struct drm_fb_helper. Simplify
radeon by converting all callers and removing struct radeon_fbdev.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:30 +0000 (10:37 +0100)]
drm/radeon: Improve fbdev object-test helper
Look up the framebuffer GEM object in fbdev object test with the
respective helper drm_gem_fb_get_obj(). The look-up helper warns if
no GEM object has been installed. Upcasting types prevents runtime
type checking, so avoid upcast to struct radeon_bo.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thomas Zimmermann [Thu, 16 Mar 2023 09:37:29 +0000 (10:37 +0100)]
drm/radeon: Move radeon_align_pitch() next to dumb-buffer helpers
Move radeon_align_pitch() next to its caller in the dumb-buffer
code. Removes the only dependency on the radeon's fbdev source file
that is not related to fbdev emulation. No functional changes.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Srinivasan Shanmugam [Mon, 27 Mar 2023 17:05:33 +0000 (22:35 +0530)]
drm/amd/amdgpu: Fix error do not initialise globals to 0
Global variables do not need to be initialized to 0 and checkpatch
flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:
ERROR: do not initialise globals to 0
+int amdgpu_no_queue_eviction_on_vm_fault = 0;
Fix this checkpatch error.
Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Thu, 23 Mar 2023 05:46:41 +0000 (01:46 -0400)]
drm/amdgpu: Return from switch early for EEPROM I2C address
As soon as control->i2c_address is set, return; remove the "break;" from the
switch--it is unnecessary. This mimics what happens when for some cases in the
switch, we call helper functions with "return <helper function>".
Remove final function "return true;" to indicate that the switch is final and
terminal, and that there should be no code after the switch.
Cc: Candice Li <candice.li@amd.com> Cc: Kent Russell <kent.russell@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Thu, 23 Mar 2023 04:56:26 +0000 (00:56 -0400)]
drm/amdgpu: Remove second moot switch to set EEPROM I2C address
Remove second switch since it already has its own function and case in the
first switch. This also avoids requalifying the EEPROM I2C address for VEGA20,
SIENNA CICHLID, and ALDEBARAN, as those have been set by the first switch and
shouldn't match SMU v13.0.x.
Cc: Candice Li <candice.li@amd.com> Cc: Kent Russell <kent.russell@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Fixes: 158225294683 ("drm/amdgpu: Add EEPROM I2C address for smu v13_0_0") Fixes: c9bdc6c3cf39 ("drm/amdgpu: Add EEPROM I2C address support for ip discovery") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hans de Goede [Sun, 12 Mar 2023 19:17:51 +0000 (20:17 +0100)]
drm/amd/display/amdgpu_dm: Pass proper parent for backlight device registration v3
The parent for the backlight device should be the drm-connector object,
not the PCI device.
Userspace relies on this to be able to detect which backlight class device
to use on hybrid gfx devices where there may be multiple native (raw)
backlight devices registered.
Specifically gnome-settings-daemon expects the parent device to have
an "enabled" sysfs attribute (as drm_connector devices do) and tests
that this returns "enabled" when read.
This aligns the parent of the backlight device with i915, nouveau, radeon.
Note that drivers/gpu/drm/amd/amdgpu/atombios_encoders.c also already
uses the drm_connector as parent, only amdgpu_dm.c used the PCI device
as parent before this change.
Changes in v3:
Make amdgpu_dm_register_backlight_device() check bl_idx != 1 before
registering the backlight since amdgpu_dm_connector_late_register()
now calls it for _all_ connectors.
Changes in v2:
Together with changing the parent, also move the registration to
drm_connector_funcs.late_register() this is necessary because the parent
device (which now is the drm_connector) must be registered before
the backlight class device is, otherwise the backlight class device ends
up without any parent set at all.
This brings the backlight class device registration timing inline with
nouveau and i915 which also use drm_connector_funcs.late_register()
for this.
Note this slightly changes backlight_device_register() error handling,
instead of not increasing dm->num_of_edps and re-using the current
bl_idx for a potential other backlight device, dm->backlight_dev[bl_idx]
is now simply left NULL on failure. This is ok because all code
looking at dm->backlight_dev[i] also checks it is not NULL.
Link: https://gitlab.gnome.org/GNOME/gnome-settings-daemon/-/issues/730 Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hans de Goede [Sun, 12 Mar 2023 19:17:50 +0000 (20:17 +0100)]
drm/amd/display/amdgpu_dm: Make amdgpu_dm_register_backlight_device() take an amdgpu_dm_connector
Make amdgpu_dm_register_backlight_device() take an amdgpu_dm_connector
pointer to the connector for which it should register the backlight
as its only argument.
This is a preparation patch for moving the actual backlight class device
registering to drm_connector_funcs.late_register.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hans de Goede [Sun, 12 Mar 2023 19:17:49 +0000 (20:17 +0100)]
drm/amd/display/amdgpu_dm: Move most backlight setup into setup_backlight_device()
Rename register_backlight_device() to setup_backlight_device()
and move all backlight setup related calls from
amdgpu_dm_register_backlight_device() and from
amdgpu_dm_initialize_drm_device() there.
This leaves amdgpu_dm_register_backlight_device() dealing purely
with registering the actual backlight class device.
This is a preparation patch for moving the actual backlight class device
registering to drm_connector_funcs.late_register.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hans de Goede [Sun, 12 Mar 2023 19:17:48 +0000 (20:17 +0100)]
drm/amd/display/amdgpu_dm: Add a bl_idx to amdgpu_dm_connector
Currently functions like update_connector_ext_caps() and
amdgpu_dm_connector_destroy() are iterating over dm->backlight_link[i]
to find the index of the (optional) backlight_dev associated with
the connector.
Instead make register_backlight_device() store the dm->backlight_dev[]
index used for the connector inside the amdgpu_dm_connector struct.
This removes the need to iterate over the dm->backlight_link[]
array and this is necessary as a preparation patch for moving
the actual backlight_device_register()
call to drm_connector_funcs.late_register.
While reworking update_connector_ext_caps() also remove the aconnector
and aconnector->dc_link NULL checks in this function. These are both
never NULL and are unconditionally derefed in its callers.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
AngeloGioacchino Del Regno [Thu, 23 Mar 2023 09:08:22 +0000 (10:08 +0100)]
drm/panfrost: Add basic support for speed binning
Some SoCs implementing ARM Mali GPUs are subject to speed binning:
this means that some versions of the same SoC model may need to be
limited to a slower frequency compared to the other:
this is being addressed by reading nvmem (usually, an eFuse array)
containing a number that identifies the speed binning of the chip,
which is usually related to silicon quality.
To address such situation, add basic support for reading the
speed-bin through nvmem, as to make it possible to specify the
supported hardware in the OPP table for GPUs.
This commit also keeps compatibility with any platform that does
not specify (and does not even support) speed-binning.
AngeloGioacchino Del Regno [Thu, 23 Mar 2023 09:08:21 +0000 (10:08 +0100)]
dt-bindings: gpu: mali-bifrost: Document nvmem for speedbin support
Some SoCs implementing ARM Mali GPUs may be subject to speed binning
and the usable bin is read from nvmem: document the addition of nvmem
and nvmem-cells for 'speed-bin'.
Rob Herring [Fri, 10 Mar 2023 14:47:05 +0000 (08:47 -0600)]
drm: Use of_property_read_bool() for boolean properties
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties.
Convert reading boolean properties to of_property_read_bool().
The nt36672a bindings were added with a mistake on VDDIO supply calling
it in one place vddio and in other vddi0. Typical name is rather vddio
which is also now used by DTS (sdm845-xiaomi-beryllium-common.dtsi) and
Linux driver.
Fixes: c2abcf30efb8 ("dt-bindings: display: novatek,nt36672a: Fix unevaluated properties warning") Fixes: 9528a02430df ("dt-bindings: display: panel: Add bindings for Novatek nt36672a") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
Daniel Vetter [Wed, 29 Mar 2023 14:00:23 +0000 (16:00 +0200)]
Merge v6.3-rc4 into drm-next
I just landed the fence deadline PR from Rob that a bunch of drivers
want/need to apply driver-specific patches. Backmerge -rc4 so that
they don't have to be stuck on -rc2 for no reason at all.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 29 Mar 2023 13:45:37 +0000 (15:45 +0200)]
Merge tag 'dma-fence-deadline' of https://gitlab.freedesktop.org/drm/msm into drm-next
This series adds a deadline hint to fences, so realtime deadlines
such as vblank can be communicated to the fence signaller for power/
frequency management decisions.
This is partially inspired by a trick i915 does, but implemented
via dma-fence for a couple of reasons:
1) To continue to be able to use the atomic helpers
2) To support cases where display and gpu are different drivers
See https://patchwork.freedesktop.org/series/93035/
This does not yet add any UAPI, although this will be needed in
a number of cases:
1) Workloads "ping-ponging" between CPU and GPU, where we don't
want the GPU freq governor to interpret time stalled waiting
for GPU as "idle" time
2) Cases where the compositor is waiting for fences to be signaled
before issuing the atomic ioctl, for example to maintain 60fps
cursor updates even when the GPU is not able to maintain that
framerate.
Rob Clark [Tue, 21 Sep 2021 16:35:50 +0000 (09:35 -0700)]
drm/scheduler: Add fence deadline support
As the finished fence is the one that is exposed to userspace, and
therefore the one that other operations, like atomic update, would
block on, we need to propagate the deadline from from the finished
fence to the actual hw fence.
v2: Split into drm_sched_fence_set_parent() (ckoenig)
v3: Ensure a thread calling drm_sched_fence_set_deadline_finished() sees
fence->parent set before drm_sched_fence_set_parent() does this
test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT).
Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Rob Clark [Tue, 28 Feb 2023 18:10:11 +0000 (10:10 -0800)]
dma-buf/sync_file: Surface sync-file uABI
We had all of the internal driver APIs, but not the all important
userspace uABI, in the dma-buf doc. Fix that. And re-arrange the
comments slightly as otherwise the comments for the ioctl nr defines
would not show up.
v2: Fix docs build warning coming from newly including the uabi header
in the docs build
Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Rob Herring [Fri, 10 Mar 2023 14:47:05 +0000 (08:47 -0600)]
drm: Use of_property_present() for testing DT property presence
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties. As
part of this, convert of_get_property/of_find_property calls to the
recently added of_property_present() helper when we just want to test
for presence of a property and nothing more.
Daniel Vetter [Tue, 28 Mar 2023 17:23:05 +0000 (19:23 +0200)]
Merge tag 'exynos-drm-next-for-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
A patch series for moving MIPI-DSI driver for Exynos DRM to drm/bridge
directory so that I.MX SoC family can also share the same device driver.
Samsung MIPI DSIM device is a common IP that can be used by Exynos and I.MX8M
Mini/Nano/Plus SoC. Regarding this, this patch series has added several
things below to existing MIPI DSI driver,
- Add exynos_dsi_type enum type to provide controller data from different
platforms.
- Add two pipeline detection ways support - existing Exynos DSI child node
and I.MX family of-graph port or ports.
- Consider component and bridged based DRM drivers.
- Add device tree binding support of I.MX family.
Marek Vasut [Wed, 8 Mar 2023 16:39:53 +0000 (22:09 +0530)]
drm: bridge: samsung-dsim: Add i.MX8M Plus support
Add extras to support i.MX8M Plus. The main change is the removal of
HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise
the implementation of this IP in i.MX8M Plus is very much compatible
with the i.MX8M Mini/Nano one.
Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <m.szyprowski@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:49 +0000 (22:09 +0530)]
drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.
In order to access this DSI controller between various platform SoCs,
the ideal way to incorporate this in the drm stack is via the drm bridge
driver.
We already have a consolidated code for supporting component and bridge
based DRM drivers, so keep the exynos component based code in existing
exynos_drm_dsi.c and move generic bridge code as part of samsung-dsim.c
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:48 +0000 (22:09 +0530)]
drm: exynos: dsi: Add host helper for te_irq_handler
IRQ handler for te-gpio seems to be common across DSIM host.
However, Exynos is handling this via CRTC drivers but there is no clear
evidence on how the same has been handled in i.MX8MM. Keeping the handler
as-it-is can be a viable option but adding DSIM bridge core in upcoming
patches is not possible to call Exynos CRTC handler as DSIM bridge has
to be common across DRM bridge core instead of platform specific DRM
drivers like Exynos here.
So, this patch handles the handler via platform host helper, so-that
handling platform specific hook across Exynos and generic can be
reasonable till it makes it generic across all platforms.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:47 +0000 (22:09 +0530)]
drm: exynos: dsi: Consolidate component and bridge
DSI host registration, attach and detach operations are quite
different for the component and bridge-based DRM drivers.
Supporting generic bridge driver to use both component and bridge
based DRM drivers can be tricky and would require additional host
related operation hooks.
Add host operation hooks for registering and unregistering Exynos
and generic drivers, where Exynos hooks are used in existing Exynos
component based DRM drivers and generic hooks are used in i.MX8M
bridge based DRM drivers.
Add host attach and detach operation hooks for Exynos component
DRM drivers and those get invoked while DSI core host attach and
detach gets called.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:46 +0000 (22:09 +0530)]
drm: exynos: dsi: Add atomic_get_input_bus_fmts
Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
proper input format from list of supported output formats.
This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the other component closer to pipeline
components.
List of Pixel formats are taken from,
AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
3.7.4 Pixel formats
Table 14. DSI pixel packing formats
Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:45 +0000 (22:09 +0530)]
drm: exynos: dsi: Add input_bus_flags
LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting
the i.MX8M Mini/Nano DSI host to add additional Data Enable signal
active low (DE_LOW). This makes the valid data transfer on each
horizontal line.
So, add additional bus flags DE_LOW setting via input_bus_flags
for i.MX8M Mini/Nano platforms.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Jagan Teki [Wed, 8 Mar 2023 16:39:44 +0000 (22:09 +0530)]
drm: exynos: dsi: Add atomic check
Look like an explicit fixing up of mode_flags is required for DSIM IP
present in i.MX8M Mini/Nano SoCs.
At least the LCDIF + DSIM needs active low sync polarities in order
to correlate the correct sync flags of the surrounding components in
the chain to make sure the whole pipeline can work properly.
On the other hand the i.MX 8M Mini Applications Processor Reference Manual,
Rev. 3, 11/2020 says.
"13.6.3.5.2 RGB interface
Vsync, Hsync, and VDEN are active high signals."
i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
3.6.3.5.2 RGB interface
i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
13.6.2.7.2 RGB interface
both claim "Vsync, Hsync, and VDEN are active high signals.", the
LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
No clear evidence about whether it can be documentation issues or
something, so added proper comments on the code.
Comments are suggested by Marek Vasut.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Host transfer() in the DSI master will invoke only when the DSI commands
are sent from DSI devices like DSI Panel or DSI bridges and this host
the transfer wouldn't invoke for I2C-based-DSI bridge drivers.
Handling DSI host initialization in transfer calls misses the controller
setup for I2C configured DSI bridges.
This patch updates the DSI host initialization by calling host to init
from bridge pre_enable as the bridge pre_enable API is invoked by core
as it is common across all classes of DSI device drivers.
The host init during pre_enable is conditional and not invoked for Exynos
as existing downstream drm panels and bridges in Exynos are expecting
the host initialization during DSI transfer.
Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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