Stephen Boyd [Tue, 29 Jun 2021 20:33:10 +0000 (13:33 -0700)]
Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'clk-imx' into clk-next
* clk-legacy:
clkdev: remove unused clkdev_alloc() interfaces
clkdev: remove CONFIG_CLKDEV_LOOKUP
m68k: coldfire: remove private clk_get/clk_put
m68k: coldfire: use clkdev_lookup on most coldfire
mips: ralink: convert to CONFIG_COMMON_CLK
mips: ar7: convert to CONFIG_COMMON_CLK
mips: ar7: convert to clkdev_lookup
* clk-vc5:
clk: vc5: fix output disabling when enabling a FOD
* clk-allwinner:
clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audio
* clk-nvidia:
clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator
clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()
clk: tegra: Add stubs needed for compile-testing
clk: tegra: Don't deassert reset on enabling clocks
clk: tegra: Mark external clocks as not having reset control
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
clk: tegra: Don't allow zero clock rate for PLLs
clk: tegra: Halve SCLK rate on Tegra20
clk: tegra: Ensure that PLLU configuration is applied properly
clk: tegra: Fix refcounting of gate clocks
clk: tegra30: Use 300MHz for video decoder by default
* clk-imx:
clk: imx8mq: remove SYS PLL 1/2 clock gates
clk: imx: scu: Do not enable runtime PM for CPU clks
clk: imx: scu: add parent save and restore
clk: imx: scu: Only save DC SS clock using non-cached clock rate
clk: imx: scu: Add A72 frequency scaling support
clk: imx: scu: Add A53 frequency scaling support
clk: imx: scu: bypass pi_pll enable status restore
clk: imx: scu: detach pd if can't power up
clk: imx: scu: bypass cpu clock save and restore
clk: imx: scu: add parallel port clock ops
clk: imx: scu: add more scu clocks
clk: imx: scu: add enet rgmii gpr clocks
clk: imx8qm: add clock valid resource checking
clk: imx8qxp: add clock valid checking mechnism
clk: imx: scu: add gpr clocks support
clk: imx: scu: remove legacy scu clock binding support
dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
clk: imx: Remove the audio ipg clock from imx8mp
Jonathan Marek [Wed, 9 Jun 2021 02:20:48 +0000 (22:20 -0400)]
clk: qcom: Add camera clock controller driver for SM8250
Add support for the camera clock controller found on SM8250.
Based on the downstream driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca
[sboyd@kernel.org: Add UL to avoid decimal problems] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pu Lehui [Wed, 9 Jun 2021 06:18:48 +0000 (14:18 +0800)]
clk/qcom: Remove unused variables
Fix gcc '-Wunused-const-variable' warnings:
drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined
but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map'
defined but not used [-Wunused-const-variable=]
clk: qcom: gcc: Add support for Global Clock controller found on MSM8226
Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies
which are different in this older chip. Register all the clocks to the
framework for the clients to be able to request for them.
Konrad Dybcio [Sat, 5 Jun 2021 12:10:38 +0000 (14:10 +0200)]
clk: qcom: Add SM6125 (TRINKET) GCC driver
Add the clocks supported in global clock controller, which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: Mark gcc_sm6125_hws array static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Alexandru Ardelean [Thu, 24 Jun 2021 08:47:37 +0000 (11:47 +0300)]
clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator
The purpose of the device-managed functions is to bind the life-time of an
object to that of a parent device object.
This is not the case for the 'vdd-cpu' regulator in this driver. A
reference is obtained via devm_regulator_get() and immediately released
with devm_regulator_put().
In this case, the usage of devm_ functions is slightly excessive, as the
un-managed versions of these functions is a little cleaner (and slightly
more economical in terms of allocation).
This change converts the devm_regulator_{get,put}() to
regulator_{get,put}() in the get_alignment_from_regulator() function of
this driver.
Lokesh Vutla [Fri, 28 May 2021 04:57:43 +0000 (10:27 +0530)]
clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk
AM64 has 9 instances of EPWM modules. And each instance has a clk to
Timer-Base sub-module that can be controlled by Control module. Update
the driver with all the 9 instance of clocks associated to
ti,am64-epwm-tbclk.
Stephen Boyd [Mon, 21 Jun 2021 23:39:34 +0000 (16:39 -0700)]
Merge tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Remove audio ipg clock from i.MX8MP
- Fix naming typo of clock compatible string
- Remove deprecated legacy clock binding for SCU clock driver
- Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM
- Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio,
parallel interface)
- Add dedicated clock ops for paralel interface
- Different fixes for clocks controlled by ATF
- Fix different issues related to parallel interface clocks
- Add A53/A72 frequency scaling support clk-scu driver
- Add special case for DCSS clock on suspend for clk-scu driver
- Add parent save/restore on suspend/resume to clk-scu driver
- Skip runtime PM enablement for CPU clocks in clk-scu driver
- Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their
bindings
* tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx8mq: remove SYS PLL 1/2 clock gates
clk: imx: scu: Do not enable runtime PM for CPU clks
clk: imx: scu: add parent save and restore
clk: imx: scu: Only save DC SS clock using non-cached clock rate
clk: imx: scu: Add A72 frequency scaling support
clk: imx: scu: Add A53 frequency scaling support
clk: imx: scu: bypass pi_pll enable status restore
clk: imx: scu: detach pd if can't power up
clk: imx: scu: bypass cpu clock save and restore
clk: imx: scu: add parallel port clock ops
clk: imx: scu: add more scu clocks
clk: imx: scu: add enet rgmii gpr clocks
clk: imx8qm: add clock valid resource checking
clk: imx8qxp: add clock valid checking mechnism
clk: imx: scu: add gpr clocks support
clk: imx: scu: remove legacy scu clock binding support
dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
clk: imx: Remove the audio ipg clock from imx8mp
Stephen Boyd [Mon, 21 Jun 2021 23:36:46 +0000 (16:36 -0700)]
Merge tag 'for-5.14-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia
Pull Tegra clk driver updates from Thierry Reding:
This contains a few fixes across the board and adds stubs to allow
certain drivers to be compile-tested. One other notable change added
here is that clock enabling no longer deasserts the reset. Drivers are
now supposed to do that explicitly because doing it implicitly can get
in the way of certain power-up sequences.
* tag 'for-5.14-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()
clk: tegra: Add stubs needed for compile-testing
clk: tegra: Don't deassert reset on enabling clocks
clk: tegra: Mark external clocks as not having reset control
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
clk: tegra: Don't allow zero clock rate for PLLs
clk: tegra: Halve SCLK rate on Tegra20
clk: tegra: Ensure that PLLU configuration is applied properly
clk: tegra: Fix refcounting of gate clocks
clk: tegra30: Use 300MHz for video decoder by default
Stephen Boyd [Mon, 21 Jun 2021 23:33:56 +0000 (16:33 -0700)]
Merge tag 'sunxi-clk-fixes-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull one Allwinner clk driver update from Maxime Ripard:
- One patch to fix a divider on the v3s Audio PLL
* tag 'sunxi-clk-fixes-for-5.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audio
Lucas Stach [Fri, 28 May 2021 18:01:35 +0000 (20:01 +0200)]
clk: imx8mq: remove SYS PLL 1/2 clock gates
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.
Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Nitin Garg [Fri, 4 Jun 2021 09:09:43 +0000 (17:09 +0800)]
clk: imx: scu: Do not enable runtime PM for CPU clks
Since CPU clocks are managed by CPUFREQ and ATF, do not enable
runtime PM otherwise rpm gets out of status as cpufreq
also manages clock states.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Anson Huang [Fri, 4 Jun 2021 09:09:41 +0000 (17:09 +0800)]
clk: imx: scu: Only save DC SS clock using non-cached clock rate
Display sub-system has special clock settings in SCFW, the
bypassed clock is used instead of PLL in Linux kernel clock
tree, so when saving clock rate, need to save non-cached clock
rate for Display sub-system's bypass clocks, and other clocks
still use the cached clock rate which is with runtime PM ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Anson Huang [Fri, 4 Jun 2021 09:09:40 +0000 (17:09 +0800)]
clk: imx: scu: Add A72 frequency scaling support
Add A72 clock to support cpufreq on A72 cluster.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Anson Huang [Fri, 4 Jun 2021 09:09:39 +0000 (17:09 +0800)]
clk: imx: scu: Add A53 frequency scaling support
Add i.MX8QM cpufreq support for A53 cluster.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Guoniu.zhou [Fri, 4 Jun 2021 09:09:35 +0000 (17:09 +0800)]
clk: imx: scu: add parallel port clock ops
Because digital pll for parallel interface is on by default, and
not provide enable/disable function by scu, so add the related ops
for this kind of clocks.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Dong Aisheng [Fri, 21 May 2021 03:12:47 +0000 (11:12 +0800)]
clk: imx: scu: add enet rgmii gpr clocks
enet tx clk actually is sourced from a gpr divider, not default enet
clk. Add enet grp clocks for user to use correctly.
Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
clk-imx8qxp is a common SCU clock driver used by both QM and QXP
platforms. The clock numbers vary a bit between those two platforms.
This patch introduces a mechanism to only register the valid clocks
for one platform by checking the clk resource id table.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
SCU clock protocol supports a few clocks based on GPR controller
registers including mux/divider/gate.
Add a generic clock register API to support them all.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
clk: imx: scu: remove legacy scu clock binding support
Legacy scu clock binding are not maintained anymore, it has a very
limited clocks supported during initial upstreaming and obviously
unusable by products. So it's meaningless to keep it in
kernel which worse the code readability.
Remove it to keep code much cleaner.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
The legacy clock binding are not maintained anymore. It has only
a very preliminary supported clocks during initial upstream and
meaningless for users. So drop it from binding doc now.
Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
There is a typo in binding doc that the name of compatible string of
scu clock should be "fsl,xxx-clk" rather than "fsl,xxx-clock".
In reality, both example and dts using "fsl,xxx-clk", so fixing the doc
is enough.
Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Luca Ceresoli [Thu, 27 May 2021 21:16:47 +0000 (23:16 +0200)]
clk: vc5: fix output disabling when enabling a FOD
On 5P49V6965, when an output is enabled we enable the corresponding
FOD. When this happens for the first time, and specifically when writing
register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs
are stopped for a short time and then restarted.
According to Renesas support this is intended: "The reason for that is VC6E
has synced up all output function".
This behaviour can be disabled at least on VersaClock 6E devices, of which
only the 5P49V6965 is currently implemented by this driver. This requires
writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50. Those registers
are named "Unused Factory Reserved Register", and the bits are documented
as "Skip VDDO<N> verification", which does not clearly explain the relation
to FOD sync. However according to Renesas support as well as my testing
setting this bit does prevent disabling of all clock outputs when enabling
a FOD.
See "VersaClock ® 6E Family Register Descriptions and Programming Guide"
(August 30, 2018), Table 116 "Power Up VDD check", page 58:
https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-descriptions-and-programming-guide
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Reviewed-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20210527211647.1520720-1-luca@lucaceresoli.net Fixes: 2bda748e6ad8 ("clk: vc5: Add support for IDT VersaClock 5P49V6965") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dario Binacchi [Sun, 6 Jun 2021 20:22:53 +0000 (22:22 +0200)]
clk: ti: add am33xx/am43xx spread spectrum clock support
The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for
the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for
DDR, PER, and CORE PLLs.
Calculating the required values and setting the registers accordingly
was taken from the set_mpu_spreadspectrum routine contained in the
arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.
In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
SSC enabled, the reference manual explains that there is a restriction
of range of M values. Since the omap2_dpll_round_rate routine attempts
to select the minimum possible N, the value of M obtained is not
guaranteed to be within the range required. With the new "ti,min-div"
parameter it is possible to increase N and consequently M to satisfy the
constraint imposed by SSC.
Dario Binacchi [Sun, 6 Jun 2021 20:22:52 +0000 (22:22 +0200)]
ARM: dts: am43xx-clocks: add spread spectrum support
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruhl7x RM, SSC is supported only for LCD
and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and
PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field
in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE,
MPU, DDR, PER, DISP, EXTDEV).
Dario Binacchi [Sun, 6 Jun 2021 20:22:51 +0000 (22:22 +0200)]
ARM: dts: am33xx-clocks: add spread spectrum support
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for LCD
and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and
CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the
CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR,
PER, DISP).
Stephen Boyd [Tue, 8 Jun 2021 22:30:18 +0000 (15:30 -0700)]
Merge tag 'clkdev-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic into clk-legacy
Pull "clean up legacy clock interfaces" series from Arnd Bergmann:
A recent discussion about legacy clk interface users revealed
that there are only two platforms remaining that provide their own
clk_get()/clk_put() implementations, MIPS ar7 and and m68k coldfire.
I managed to rework both of these to just use the normal clkdev code,
and fold CONFIG_CLKDEV_LOOKUP into CONFIG_HAVE_CLK as it is now shared
among all users.
As I noticed that the ar7 clock implementation and the ralink version
are rather trivial, I ended up converting those to use the common-clk
interfaces as well, though this is unrelated to the other changes.
Arnd Bergmann [Mon, 31 May 2021 09:48:49 +0000 (11:48 +0200)]
clkdev: remove CONFIG_CLKDEV_LOOKUP
This option is now synonymous with CONFIG_HAVE_CLK, so use
the latter globally. Any out-of-tree platform ports that
still use a private clk_get()/clk_put() implementation should
move to CONFIG_COMMON_CLK.
Arnd Bergmann [Mon, 31 May 2021 09:43:22 +0000 (11:43 +0200)]
m68k: coldfire: remove private clk_get/clk_put
Only three SoCs remain that use the custom clk_get/clk_put.
Move these over to clkdev_lookup tables as well. As before,
treat the "sys.0" and "pll.0" clocks as system-wide clocks,
and all the other ones as device specific.
The "name" field in 'struct clock' is now unused, so rename
that as well as a cleanup and to reduce the object code size.
The DEFINE_CLK macro could be changed the same way, but it
is less churn to just leave those in place, that can be
done as a follow-up later if someone is interested.
Arnd Bergmann [Mon, 31 May 2021 09:12:55 +0000 (11:12 +0200)]
m68k: coldfire: use clkdev_lookup on most coldfire
Coldfire is now the only target that implements the clk_get()/clk_put()
helpers itself rather than using the common implementation.
Most coldfire variants only have two distinct clocks and use the clk
code purely for lookup. Change those over to use clkdev_lookup instead
but leave the custom clk interface for those two clocks.
Arnd Bergmann [Mon, 31 May 2021 11:51:18 +0000 (13:51 +0200)]
mips: ralink: convert to CONFIG_COMMON_CLK
ralink only has a very trivial clock implementation, with everything
being fixed clocks.
Convert it to CONFIG_COMMON_CLK to reduce the number of platforms
that rely on legacy clocks. Of course, the clocks really should
be read from the device tree instead, but this is a step into that
direction.
This adds about 50KB to the kernel image size, which is an unfortunate
increase, but not as bad as I had feared:
Arnd Bergmann [Mon, 31 May 2021 13:22:37 +0000 (15:22 +0200)]
mips: ar7: convert to CONFIG_COMMON_CLK
Perform a minimal conversion of the ar7 clock implementation to the common
clock framework. While the hardware can control the rates, this is left
unchanged, and all clocks are registered as fixed-rate or fixed-divider
clocks. Similarly, the clkdev lookup information is left unchanged but
moved from the table format into individual allocations.
There is a small increase in code size:
text data bss dec hex filename 4757116 596640 91328 5445084 5315dc vmlinux-before 4806159 602360 91344 5499863 53ebd7 vmlinux-after
Konrad Dybcio [Mon, 24 May 2021 22:54:55 +0000 (00:54 +0200)]
clk: qcom: smd-rpm: Switch to parent_data
Switch to parent_data and with that fix the longstanding issue where
if there wasn't a clock precisely named "xo_board", rpmcc would not play
along well. This started to show lately when "xo_board" was being changed to
"xo-board" so as to align with DTS naming spec.
Stephen Boyd [Wed, 2 Jun 2021 02:01:21 +0000 (19:01 -0700)]
Merge tag 'renesas-clk-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for CPU core clock boost modes on R-Car Gen3
- Add ISPCS (Image Signal Processor) clocks on R-Car V3U
- Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate()
and improve support for multiple parents
- Switch RZ/N1 divider clocks to .determine_rate()
- Add ZA2 (Audio Clock Generator) clock on R-Car D3
- Minor fixes and improvements
* tag 'renesas-clk-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a77995: Add ZA2 clock
clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
clk: renesas: r9a06g032: Switch to .determine_rate()
clk: renesas: div6: Implement range checking
clk: renesas: div6: Consider all parents for requested rate
clk: renesas: div6: Switch to .determine_rate()
clk: renesas: div6: Simplify src mask handling
clk: renesas: div6: Use clamp() instead of clamp_t()
clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()
clk: renesas: r8a779a0: Add ISPCS clocks
clk: renesas: rcar-gen3: Add boost support to Z clocks
clk: renesas: rcar-gen3: Add custom clock for PLLs
clk: renesas: rcar-gen3: Increase Z clock accuracy
clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/
clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()
clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32
clk: renesas: rcar-gen3: Update Z clock rate formula in comments
Peter Collingbourne [Thu, 20 May 2021 16:17:02 +0000 (17:17 +0100)]
clk: versatile: remove dependency on ARCH_*
It is now possible to build a modular kernel for vexpress by
not setting CONFIG_ARCH_VEXPRESS=y and instead setting =m on the
drivers that it normally implies. This is with the exception of
CLK_VEXPRESS_OSC which is currently hidden behind a dependency on
one of several ARCH_* variables. Remove that dependency so that
CLK_VEXPRESS_OSC may be enabled without it.
Dan Carpenter [Tue, 11 May 2021 07:09:08 +0000 (10:09 +0300)]
clk: qcom: cleanup some dev_err_probe() calls
The dev_err_probe() function prints an error message if the error
code is not -EPROBE_DEFER. If we know the error code in is -ENODEV
then there is no reason to check.
dev_err_probe() returns the error code passed as second parameter. Also if
the error code is -EPROBE_DEFER dev_err_probe() is silent, so there is no
need to check for this value before calling dev_err_probe().
Dmitry Osipenko [Sun, 16 May 2021 16:30:40 +0000 (19:30 +0300)]
clk: tegra: Don't deassert reset on enabling clocks
The Tegra clock driver contains legacy code which deasserts hardware reset
when peripheral clocks are enabled. This behaviour comes from a pre-CCF
era of the Tegra drivers. This is unacceptable for modern kernel drivers
which use generic CCF and reset-control APIs because it breaks assumptions
of the drivers about clk/reset sequences and about reset-propagation
delays. Hence remove the awkward legacy behaviour from the clk driver.
In particular PMC driver assumes that hardware blocks remains in reset
while power domain is turning on, but the clk driver deasserts the reset
before power clamp is removed, hence breaking the driver's assumption.
Dmitry Osipenko [Sun, 16 May 2021 16:30:38 +0000 (19:30 +0300)]
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
Check whether thermal DIV2 throttle is active in order to report
the CPU frequency properly. This very useful for userspace tools
like cpufreq-info which show actual frequency asserted from hardware.
Dmitry Osipenko [Sun, 16 May 2021 16:30:37 +0000 (19:30 +0300)]
clk: tegra: Don't allow zero clock rate for PLLs
Zero clock rate doesn't make sense for PLLs and tegra-clk driver enters
into infinite loop on trying to calculate PLL parameters for zero rate.
Make code to error out if requested rate is zero.
Originally this trouble was found by Robert Yang while he was trying to
bring up upstream kernel on Samsung Galaxy Tab, which happened due to a
bug in Tegra DRM driver that erroneously sets PLL rate to zero. This
issues came over again recently during of kernel bring up on ASUS TF700T.
Dmitry Osipenko [Sun, 16 May 2021 16:30:36 +0000 (19:30 +0300)]
clk: tegra: Halve SCLK rate on Tegra20
Higher SCLK rates on Tegra20 require high core voltage. The higher
clock rate may have a positive performance effect only for AHB DMA
transfers and AVP CPU, but both aren't used by upstream kernel at all.
Halve SCLK rate on Tegra20 in order to remove the high core voltage
requirement.
Dmitry Osipenko [Sun, 16 May 2021 16:30:35 +0000 (19:30 +0300)]
clk: tegra: Ensure that PLLU configuration is applied properly
The PLLU (USB) consists of the PLL configuration itself and configuration
of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114,
where T114 immediately bails out if PLLU is enabled and T30 re-enables
a potentially already enabled PLL (left after bootloader) and then fully
reprograms it, which could be unsafe to do. The correct way should be to
skip enabling of the PLL if it's already enabled and then apply
configuration to the outputs. This patch doesn't fix any known problems,
it's a minor improvement.
Dmitry Osipenko [Sun, 16 May 2021 16:30:34 +0000 (19:30 +0300)]
clk: tegra: Fix refcounting of gate clocks
The refcounting of the gate clocks has a bug causing the enable_refcnt
to underflow when unused clocks are disabled. This happens because clk
provider erroneously bumps the refcount if clock is enabled at a boot
time, which it shouldn't be doing, and it does this only for the gate
clocks, while peripheral clocks are using the same gate ops and the
peripheral clocks are missing the initial bump. Hence the refcount of
the peripheral clocks is 0 when unused clocks are disabled and then the
counter is decremented further by the gate ops, causing the integer
underflow.
Fix this problem by removing the erroneous bump and by implementing the
disable_unused() callback, which disables the unused gates properly.
The visible effect of the bug is such that the unused clocks are never
gated if a loaded kernel module grabs the unused clocks and starts to use
them. In practice this shouldn't cause any real problems for the drivers
and boards supported by the kernel today.
Dmitry Osipenko [Sun, 16 May 2021 16:30:33 +0000 (19:30 +0300)]
clk: tegra30: Use 300MHz for video decoder by default
The 600MHz is a too high clock rate for some SoC versions for the video
decoder hardware and this may cause stability issues. Use 300MHz for the
video decoder by default, which is supported by all hardware versions.
Kuninori Morimoto [Thu, 27 May 2021 04:36:38 +0000 (13:36 +0900)]
clk: renesas: r8a77995: Add ZA2 clock
R-Car D3 ZA2 clock is from PLL0D3 or S0,
and it can be controlled by ZA2CKCR.
It is needed for R-Car Sound, but is not used so far.
Using default settings is very enough at this point.
This patch adds it by DEF_FIXED().
Geert Uytterhoeven [Tue, 4 May 2021 09:17:22 +0000 (11:17 +0200)]
clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
Make the style of the comment block for the Software Reset Clearing
Register offsets consistent with the comment blocks for the other
register offsets.
The Realtime Module Stop Control Register definitions (RMSTPCR(i)) are
incorrect for i >= 8 on R-Car Gen2 and Gen3.
As these are unused, and not planned to be used, just like the
corresponding Modem Module Stop Control Register definitions (MMSTPCR())
on R-Mobile APE6 (they are intended for the software running on the
Real-Time and Modem CPU cores), they can just be removed.
Taniya Das [Sun, 25 Apr 2021 07:08:22 +0000 (12:38 +0530)]
clk: qcom: clk-rcg2: Add support for duty-cycle for RCG
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.
Tobias Schramm [Thu, 13 May 2021 13:13:15 +0000 (15:13 +0200)]
clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audio
Commit 46060be6d840 ("clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll")
changed the audio pll on the Allwinner V3s and V3 SoCs to use
sigma-delta modulation. In the process the declaration of fixed postdivider
providing "pll-audio" was adjusted to provide the desired clock rates from
the now sigma-delta modulated pll.
However, while the divider used for calculations by the clock framework
was adjusted the actual divider programmed into the hardware in
sun8i_v3_v3s_ccu_init was left at "divide by four". This broke the
"pll-audio" clock, now only providing quater the expected clock rate.
It would in general be desirable to program the postdivider for
"pll-audio" to four, such that a broader range of frequencies were
available on the pll outputs. But the clock for the integrated codec
"ac-dig" does not feature a mux that allows to select from all pll outputs
as it is just a simple clock gate connected to "pll-audio". Thus we need
to set the postdivider to one to be able to provide the 22.5792MHz and
24.576MHz rates required by the internal sun4i codec.
This patches fixes the incorrect clock rate by forcing the postdivider to
one in sun8i_v3_v3s_ccu_init.
clk: renesas: r9a06g032: Switch to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long. Hence switch the divider clocks on RZ/N1 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.
Consider the minimum and maximum clock rates imposed by clock users when
calculating the most appropriate clock rate in the .determine_rate()
callback.
clk: renesas: div6: Consider all parents for requested rate
Currently the .determine_rate() callback considers only the current
parent clock, limiting the range of achievable clock rates on DIV6
clocks with multiple parents, as found on SH/R-Mobile SoCs.
Extend the callback to consider all available parent clocks.
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long. Hence switch the DIV6 clocks on SH/R-Mobile and R-Car
SoCs from the old .round_rate() callback to the newer .determine_rate()
callback, which does not suffer from this limitation.
clk: renesas: div6: Use clamp() instead of clamp_t()
As "div" is already "unsigned int", adding "U" suffixes to the constants
"1" and "64" allows us to replace the call to clamp_t() by a call to
clamp(). This removes hidden casts, and thus helps the compiler doing a
better job at type-checking.
Geert Uytterhoeven [Fri, 26 Mar 2021 12:00:59 +0000 (13:00 +0100)]
clk: renesas: rcar-gen3: Add custom clock for PLLs
Currently the PLLs are modeled as fixed factor clocks, based on initial
settings. However, enabling CPU boost clock rates requires increasing
the PLL clock rates.
Add a custom clock driver to model the PLL clocks. This will allow the
Z (CPU) clock driver to request changing the PLL clock rate.
Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.
Geert Uytterhoeven [Fri, 26 Mar 2021 12:00:58 +0000 (13:00 +0100)]
clk: renesas: rcar-gen3: Increase Z clock accuracy
Improve accuracy in the .determine_rate() callback for Z and Z2 clocks
by using rounded divisions. This is similar to the calculation of rates
and multipliers in the .recalc_rate() resp. set_rate() callbacks.
Sample impact for a few requested clock rates:
- R-Car H3:
- Z 500 MHz: 468 MHz => 515 MHz
- Z2 1000 MHz: 973 MHz => 1011 MHz
- R-Car M3-W:
- Z 500 MHz: 422 MHz => 516 MHz
- Z2 800 MHz: 750 MHz => 788 MHz
projects / users / jedix / linux-maple.git / log