From: Julia Filipchuk Date: Fri, 2 May 2025 22:39:24 +0000 (-0700) Subject: drm/i915/guc: Enable DUAL_QUEUE_WA for newer platforms X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=ff868667a4f9c6e349f4a4f0dcc3ff60d6ea8a73;p=users%2Fjedix%2Flinux-maple.git drm/i915/guc: Enable DUAL_QUEUE_WA for newer platforms For newer platforms (post DG2) hardware intentionally stalls on submisstion of concurrent submissions on RCS and CCS of different address spaces. With this workaround GuC will never schedule such conlicting contexts; preventing detection of a stall as a hang. GuC specs recommend to enable this for all platforms starting from MTL supporting CCS. v2: Use existing macros for version check. (Jani) v3: Reword explanation for clarity. Remove unneeded parens. Remove accidental comment change. (Daniele) Signed-off-by: Julia Filipchuk Cc: Daniele Ceraolo Spurio Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Daniele Ceraolo Spurio Link: https://lore.kernel.org/r/20250502223924.94628-1-julia.filipchuk@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 5949ff0b0161f..553daf32c0b54 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -313,8 +313,13 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) * * The same WA bit is used for both and 22011391025 is applicable to * all DG2. + * + * Platforms post DG2 prevent this issue in hardware by stalling + * submissions. With this flag GuC will schedule as to avoid such + * stalls. */ - if (IS_DG2(gt->i915)) + if (IS_DG2(gt->i915) || + (CCS_MASK(gt) && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))) flags |= GUC_WA_DUAL_QUEUE; /* Wa_22011802037: graphics version 11/12 */