From: David Woodhouse Date: Fri, 12 Jan 2018 17:49:25 +0000 (+0000) Subject: x86/retpoline: Fill RSB on context switch for affected CPUs X-Git-Tag: v4.1.12-124.31.3~1168 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=fdf98b0e18037d58c0450bf7b80b69272fc7b4a8;p=users%2Fjedix%2Flinux-maple.git x86/retpoline: Fill RSB on context switch for affected CPUs commit c995efd5a740d9cbafbf58bde4973e8b50b4d761 upstream. On context switch from a shallow call stack to a deeper one, as the CPU does 'ret' up the deeper side it may encounter RSB entries (predictions for where the 'ret' goes to) which were populated in userspace. This is problematic if neither SMEP nor KPTI (the latter of which marks userspace pages as NX for the kernel) are active, as malicious code in userspace may then be executed speculatively. Overwrite the CPU's return prediction stack with calls which are predicted to return to an infinite loop, to "capture" speculation if this happens. This is required both for retpoline, and also in conjunction with IBRS for !SMEP && !KPTI. On Skylake+ the problem is slightly different, and an *underflow* of the RSB may cause errant branch predictions to occur. So there it's not so much overwrite, as *filling* the RSB to attempt to prevent it getting empty. This is only a partial solution for Skylake+ since there are many other conditions which may result in the RSB becoming empty. The full solution on Skylake+ is to use IBRS, which will prevent the problem even when the RSB becomes empty. With IBRS, the RSB-stuffing will not be required on context switch. [ tglx: Added missing vendor check and slighty massaged comments and changelog ] [js] backport to 4.4 -- __switch_to_asm does not exist there, we have to patch the switch_to macros for both x86_32 and x86_64. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner Acked-by: Arjan van de Ven Cc: gnomes@lxorguk.ukuu.org.uk Cc: Rik van Riel Cc: Andi Kleen Cc: Josh Poimboeuf Cc: thomas.lendacky@amd.com Cc: Peter Zijlstra Cc: Linus Torvalds Cc: Jiri Kosina Cc: Andy Lutomirski Cc: Dave Hansen Cc: Kees Cook Cc: Tim Chen Cc: Greg Kroah-Hartman Cc: Paul Turner Link: https://lkml.kernel.org/r/1515779365-9032-1-git-send-email-dwmw@amazon.co.uk Signed-off-by: Jiri Slaby Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 18bb117d1b7690181346e6365c6237b6ceaac4c4) Orabug: 27477743 CVE: CVE-2017-5715 Signed-off-by: Daniel Jordan Conflicts: arch/x86/include/asm/cpufeature.h (dmj: bumped all uek4-specific microcode features up one) arch/x86/include/asm/switch_to.h arch/x86/kernel/cpu/bugs_64.c (dmj: - patch had arch/x86/kernel/cpu/bugs.c - preserved X86_FEATURE_RSB_CTXSW check in case of IBRS) Signed-off-by: Konrad Rzeszutek Wilk Reviewed-by: Darren Kenny Reviewed-by: Pavel Tatashin --- diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 8d535853081a..cb6294e2b810 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -197,14 +197,15 @@ #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ -#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Control Speculation Control */ -#define X86_FEATURE_STIPB ( 7*32+20) /* Single Thread Indirect Branch Predictors */ -#define X86_FEATURE_IA32_ARCH_CAPS ( 7*32+21) /* Control Speculation Control */ -#define X86_FEATURE_IBRS_ATT ( 7*32+22) /* IBRS all the time */ +#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ +#define X86_FEATURE_SPEC_CTRL ( 7*32+20) /* Control Speculation Control */ +#define X86_FEATURE_STIPB ( 7*32+21) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_IA32_ARCH_CAPS ( 7*32+22) /* Control Speculation Control */ +#define X86_FEATURE_IBRS_ATT ( 7*32+23) /* IBRS all the time */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13. * But thanks to kABI we have to jam it somewhere else. */ -#define X86_FEATURE_IBPB (7*32+23) /* Indirect Branch Prediction Barrier */ +#define X86_FEATURE_IBPB (7*32+24) /* Indirect Branch Prediction Barrier */ #define X86_FEATURE_STUFF_RSB (7*32+28) /* "" Whether to stuff the RSB (usually dependent on !SMEP) */ diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index d7f3b3b78ac3..53ff351ded61 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -1,6 +1,8 @@ #ifndef _ASM_X86_SWITCH_TO_H #define _ASM_X86_SWITCH_TO_H +#include + struct task_struct; /* one of the stranger aspects of C forward declarations */ __visible struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next); @@ -24,6 +26,23 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, #define __switch_canary_iparam #endif /* CC_STACKPROTECTOR */ +#ifdef CONFIG_RETPOLINE + /* + * When switching from a shallower to a deeper call stack + * the RSB may either underflow or use entries populated + * with userspace addresses. On CPUs where those concerns + * exist, overwrite the RSB with entries which capture + * speculative execution to prevent attack. + */ +#define __retpoline_fill_return_buffer \ + ALTERNATIVE("jmp 910f", \ + __stringify(__FILL_RETURN_BUFFER(%%ebx, RSB_CLEAR_LOOPS, %%esp)),\ + X86_FEATURE_RSB_CTXSW) \ + "910:\n\t" +#else +#define __retpoline_fill_return_buffer +#endif + /* * Saving eflags is important. It switches not only IOPL between tasks, * it also protects other tasks from NT leaking through sysenter etc. @@ -46,6 +65,7 @@ do { \ "movl $1f,%[prev_ip]\n\t" /* save EIP */ \ "pushl %[next_ip]\n\t" /* restore EIP */ \ __switch_canary \ + __retpoline_fill_return_buffer \ "jmp __switch_to\n" /* regparm call */ \ "1:\t" \ "popl %%ebp\n\t" /* restore EBP */ \ @@ -100,6 +120,23 @@ do { \ #define __switch_canary_iparam #endif /* CC_STACKPROTECTOR */ +#ifdef CONFIG_RETPOLINE + /* + * When switching from a shallower to a deeper call stack + * the RSB may either underflow or use entries populated + * with userspace addresses. On CPUs where those concerns + * exist, overwrite the RSB with entries which capture + * speculative execution to prevent attack. + */ +#define __retpoline_fill_return_buffer \ + ALTERNATIVE("jmp 910f", \ + __stringify(__FILL_RETURN_BUFFER(%%r12, RSB_CLEAR_LOOPS, %%rsp)),\ + X86_FEATURE_RSB_CTXSW) \ + "910:\n\t" +#else +#define __retpoline_fill_return_buffer +#endif + /* Save restore flags to clear handle leaking NT */ #define switch_to(prev, next, last) \ asm volatile(SAVE_CONTEXT \ @@ -108,6 +145,7 @@ do { \ "call __switch_to\n\t" \ "movq "__percpu_arg([current_task])",%%rsi\n\t" \ __switch_canary \ + __retpoline_fill_return_buffer \ "movq %P[thread_info](%%rsi),%%r8\n\t" \ "movq %%rax,%%rdi\n\t" \ "testl %[_tif_fork],%P[ti_flags](%%r8)\n\t" \ diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c index 44a2177a4b62..d1e84a93f70a 100644 --- a/arch/x86/kernel/cpu/bugs_64.c +++ b/arch/x86/kernel/cpu/bugs_64.c @@ -17,6 +17,7 @@ #include #include #include +#include /* * use IBRS @@ -67,6 +68,23 @@ void __init check_bugs(void) set_memory_4k((unsigned long)__va(0), 1); } +/* Check for Skylake-like CPUs (for RSB handling) */ +static bool __init is_skylake_era(void) +{ + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && + boot_cpu_data.x86 == 6) { + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_SKYLAKE_MOBILE: + case INTEL_FAM6_SKYLAKE_DESKTOP: + case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_KABYLAKE_MOBILE: + case INTEL_FAM6_KABYLAKE_DESKTOP: + return true; + } + } + return false; +} + /* The kernel command line selection */ enum spectre_v2_mitigation_cmd { SPECTRE_V2_CMD_NONE, @@ -250,7 +268,7 @@ static void __init spectre_v2_select_mitigation(void) break; /* Not needed but compilers may complain otherwise. */ } pr_err("kernel not compiled with retpoline; retpoline mitigation not available"); - return; + goto out; retpoline_auto: if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { @@ -283,6 +301,25 @@ display: spectre_v2_enabled = mode; pr_info("%s\n", spectre_v2_strings[mode]); +out: + /* + * If neither SMEP or KPTI are available, there is a risk of + * hitting userspace addresses in the RSB after a context switch + * from a shallow call stack to a deeper one. To prevent this fill + * the entire RSB, even when using IBRS. + * + * Skylake era CPUs have a separate issue with *underflow* of the + * RSB, when they will predict 'ret' targets from the generic BTB. + * The proper mitigation for this is IBRS. If IBRS is not supported + * or deactivated in favour of retpolines the RSB fill on context + * switch is required. + */ + if ((!boot_cpu_has(X86_FEATURE_PTI) && + !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { + setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); + pr_info("Filling RSB on context switch\n"); + } + /* IBRS is unnecessary with retpoline mitigation. */ if (mode == SPECTRE_V2_RETPOLINE_GENERIC || mode == SPECTRE_V2_RETPOLINE_AMD) {