From: Andrew Davis Date: Tue, 5 Dec 2023 16:23:58 +0000 (-0600) Subject: arm64: dts: ti: k3-am65: Add AM652 dtsi file X-Git-Tag: dma-mapping-6.9-2024-03-11~339^2~15^2~30 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=fcb97d190c3ca411b37d8dd0b2650fa1378f08d4;p=users%2Fhch%2Fdma-mapping.git arm64: dts: ti: k3-am65: Add AM652 dtsi file The AM652 is basically a AM654 but with 2 cores instead of 4. Add a DTSI file for AM652 matching AM654 except this core difference. This removes the need to remove the extra cores from AM654 manually in DT files for boards that use the AM652 variant. Do that for the IOT2050 boards here. Signed-off-by: Andrew Davis Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20231205162358.23904-1-afd@ti.com Signed-off-by: Nishanth Menon --- diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6cbdf370cfcc..61a634afaa4f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -9,7 +9,6 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 */ -#include "k3-am654.dtsi" #include #include diff --git a/arch/arm64/boot/dts/ti/k3-am652.dtsi b/arch/arm64/boot/dts/ti/k3-am652.dtsi new file mode 100644 index 000000000000..0f22e00faa90 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am652.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM65 SoC family in Dual core configuration + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am65.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + + thermal_zones: thermal-zones { + #include "k3-am654-industrial-thermal.dtsi" + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index e4d7cba7c62f..1d6cddb11991 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -9,6 +9,7 @@ * Common bits of the IOT2050 Basic variant, PG1 and PG2 */ +#include "k3-am652.dtsi" #include "k3-am65-iot2050-common.dtsi" / { @@ -17,16 +18,6 @@ /* 1G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; - - cpus { - cpu-map { - /delete-node/ cluster1; - }; - /delete-node/ cpu@100; - /delete-node/ cpu@101; - }; - - /delete-node/ l2-cache1; }; &main_pmx0 { diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index a847209c3df5..3864ec54e371 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -11,6 +11,7 @@ /dts-v1/; +#include "k3-am654.dtsi" #include "k3-am65-iot2050-common.dtsi" / {