From: chris hyser Date: Thu, 18 May 2017 18:18:33 +0000 (-0600) Subject: sparc64: cache_line_size() returns larger value for cache line size. X-Git-Tag: v4.1.12-102.0.20170530_1700~1 X-Git-Url: https://www.infradead.org/git/?a=commitdiff_plain;h=f7fef3fdf4af3073f99d44dca39ff810b1f3cded;p=users%2Fjedix%2Flinux-maple.git sparc64: cache_line_size() returns larger value for cache line size. SPARC currently returns L1 data cache line size (as low as 32 bytes on some systems) though L2 and L3 cache line sizes may be higher. As cache_line_size() is used by code to align memory requests to prevent unnecessary cache line sharing, this patch returns the max of L2 and L3 sizes, currently 64 bytes. OraBug: 26045057 Signed-off-by: Chris Hyser Reviewed-by: Rob Gardner Signed-off-by: Shannon Nelson --- diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 3bbce983243cf..83820b13a8b61 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -135,6 +135,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK config NEED_PER_CPU_PAGE_FIRST_CHUNK def_bool y if SPARC64 +config ARCH_HAS_CACHE_LINE_SIZE + def_bool y if SPARC64 + config MMU bool default y diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h index 5bb6991b48575..0bc9e0c42f121 100644 --- a/arch/sparc/include/asm/cache.h +++ b/arch/sparc/include/asm/cache.h @@ -12,6 +12,11 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES 32 +#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE +#define cache_line_size() max(local_cpu_data().l3_cache_line_size, \ + local_cpu_data().ecache_line_size) +#endif + #ifdef CONFIG_SPARC32 #define SMP_CACHE_BYTES_SHIFT 5 #else